Category Archives: Semiconductors

The smartphone is a subset of the total cellphone handset marketplace. One basic difference between an enhanced cellphone and a smartphone is the ability of the smartphone to incorporate third-party applications. Smartphones also typically connect to leading-edge cellular network services and are at the forefront of the convergence of data, telecom, and consumer-oriented functions (such as video games, camera, music player, mobile TV, etc.) in a single handheld device.  Most smartphones include touchscreens with built-in wireless modems and GPS/GNSS, and are capable of Web browsing, sending and receiving e-mail, voice recognition, video and audio streaming, running office applications, and over-the-air synching with a PC.

Many in the cellphone industry believe new smartphone designs are reaching the point where they have enough performance to become the primary computing device for many consumers.  If so, the market could be on the verge of entering into “the post-PC era,” as previously identified by the late Steve Jobs, who stirred up controversy with his provocative prediction in June 2010.

The new consumer/Web emphasis in the cellphone market has been a challenge for a number of top-ranked smartphone suppliers (e.g., RIM, Nokia, etc.), which have struggled to refocus their handset designs, software platforms, and business strategies to address the current phase of the fast-growing smartphone segment.

Figure 1 shows that total smartphone shipments grew 47% in 2012 to 712 million units, after surging by 67% to 485 million in 2011.  Moreover, smartphone shipments are forecast to grow by another 37% in 2013 and fall only 25 million units shy of 1.0 billion.  Smartphones are expected to account for over 50% of quarterly shipments for the first time ever in 2Q13.  In fact, smartphone shipments are forecast to reach 300 million units in 4Q13 and represent 60% of total cellphones shipped that quarter.  Smartphones are expected to surpass the 50% penetration level on an annual basis this year and hold 85% of total cellphone shipments in 2016.

In contrast to smartphones, total cellphone unit shipments grew only 1% in 2012 and are forecast to grow only 3% in 2013 (Figure 2).  As shown, non-smartphone cellphone sales were flat in 2011 but showed a 17% decline in 2012.  Moreover, IC Insights expects another 20% drop in non-smartphone handset sales in 2013.

 

Between 2011 and 2016, smartphone shipments are expected to rise at a very strong CAGR of 29% to 1,760 million units in the final year of the forecast period (the 2011-2016 CAGR for non-smartphone unit shipments is -24%).  Overall, the smartphone 2011-2016 unit shipment CAGR is greater than 7x the expected CAGR for total cellphone unit shipments in that same five-year timeframe (4%).

Competition in smartphones intensified in 2012 as suppliers rolled out new handset designs with larger touch-screen displays, more powerful processors, better operating systems, higher-resolution cameras, and new radio-modem connections to the faster “4G” cellular networks, which were quickly spreading in the U.S., South Korea, Europe, and Japan.  In the next few years, new high-speed “4G” networks are planned for China, India, Brazil, the Middle East, and other fast-growing developing markets.

Samsung and Apple dominated the smartphone market in 2012 and are expected to do so again in 2013.  In total, these two companies shipped 354 million smartphones (218 million for Samsung and 136 million for Apple) and held a combined 50% share of the total smartphone market last year.  For 2013, these two companies are forecast to ship 480 million smartphones (300 million for Samsung and 180 million for Apple) and see their combined smartphone unit marketshare slip only one percentage point to 49%.

In 2012, smartphone sales from China-based ZTE, Lenovo, and Huawei surged.  Combined, the three top-10 China-based smartphone suppliers shipped about 80 million smartphones in 2012, more than a 3x increase from the 24 million smartphones these three companies shipped in 2011.  Moreover, these three companies are forecast to ship 142 million smartphones in 2013 and together hold a 15% share of the worldwide smartphone market.  In contrast to the success of the large China-based smartphone suppliers, IC Insights expects RIM and HTC to continue to struggle in the smartphone marketplace in 2013 with both companies forecast to show a double-digit decline in smartphone unit shipments as compared to 2012.

Smartphone suppliers under pressure include Nokia, RIM, and HTC, each of which registered steep double-digit year-over-year declines in smartphone sales in 2012.  Until several years ago, Nokia held a 50% marketshare in smartphones, but in 2008 and 2009, the company saw its share fall below 40% due to increased competition from suppliers targeting consumers with interactive touch-screen handsets that are capable of running multimedia applications.  In 2012, Nokia’s smartphone shipments declined by 55% (to only 35 million units) and represented only a 5% share of the total smartphone market.  Other smartphone producers that have fallen on hard times recently include RIM and HTC.  While each of these companies had about a 10% share of the 2011 smartphone market, IC Insights forecasts that each of them will have only about a 3% share of the 2013 smartphone market.

 Report Details:  IC Market Drivers 2013

IC Market Drivers 2013—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits examines the largest, existing system opportunities for ICs and evaluates the potential for new applications that are expected to help fuel the market for ICs.

IC Market Drivers is divided into two parts.  Part 1 provides a detailed forecast of the IC industry by system type, by region, and by IC product type through 2016.  In Part 2, the IC Market Drivers report examines and evaluates key existing and emerging end-use applications that will support and propel the IC industry through 2016.  Some of these applications include the automotive market, cellular phones (including smartphones), personal/mobile computing (including tablets and Ultrabooks), wireless networks, digital imaging, and a review of many applications to watch—those that may potentially provide significant opportunity for IC suppliers later this decade.  The 2013 IC Market Drivers report is priced at $3,190 for an individual-user license and $6,290 for a multi-user corporate license.

Fraunhofer Institute for Solar Energy Systems ISE has joined forces with EV Group (EVG) to develop equipment and process technology to enable electrically conductive and optically transparent direct wafer bonds at room temperature.  The new solutions, developed in partnership with Fraunhofer ISE based on EVG’s recently announced ComBond technology, aim to enable highly mismatched material combinations like gallium arsenide (GaAs) on silicon, GaAs on indium phosphide (InP), InP on germanium (Ge) and GaAs on gallium antimonide (GaSb).  Direct wafer bonding provides the ability to combine a variety of materials with optimal properties for integration into multi-junction solar cells, which can lead to new device architectures with unparalleled performance.

"Using direct semiconductor bond technology developed in cooperation with EVG, we expect that the best material choices for multi-junction solar cell devices will become available and allow us to increase the conversion efficiency toward 50 percent," stated Dr. Frank Dimroth, Head of department III-V – Epitaxy and Solar Cells of Fraunhofer ISE.  "We are excited to partner with EVG, a leading supplier of wafer bonding equipment, to develop industrial tools and processes for this application."

Fraunhofer ISE has developed III-V multi-junction solar cells for more than 20 years and has reached record device efficiencies of up to 41 percent with its metamorphic triple-junction solar cell technology on Ge.  Higher efficiencies require the development of four- and five-junction solar cells with new material combinations to span the full absorption range of the sun’s spectrum between 300-2000 nm.  Integration of III-V solar cells on silicon opens another opportunity to reduce manufacturing cost, especially when combined with modern substrate lift-off technologies.  Direct wafer-bonding is expected to play an important role in the development of next-generation III-V solar cell devices with applications in space as well as in terrestrial concentrator photovoltaics (PV).

"We are excited about refining our new process technology together with Fraunhofer ISE, the largest solar energy research institute in Europe," stated Markus Wimplinger, corporate technology development and IP director for EVG.  "Fraunhofer ISE’s broad expertise in the area of PV, specifically in concentrated PV cell manufacturing and photonics, will allow us to characterize bonding interfaces with respect to PV applications on our new ComBond equipment platform."    

EVG’s ComBond technology has been developed in response to market needs for more sophisticated integration processes for combining materials with different lattice constant and coefficient of thermal expansion (CTE).  The process and equipment technology enables the formation of bond interfaces between heterogeneous materials—such as silicon to compound semiconductors, compound semiconductors to compound semiconductors, Ge to silicon and Ge to compound semiconductors—at room temperature, while achieving excellent bonding strength.  The ComBond technology will be commercially available later this year on a new 200-mm modular platform currently in development, called EVG580 ComBond, which will include process modules that are designed to perform surface preparation processes on both semiconductor materials and metals. 

In addition to PV, other potential application areas for processes developed in cooperation between EVG and Fraunhofer ISE include light emitting diodes (LEDs) and silicon photonics.

By Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc., San Jose, Calif.

Random process variations and layout-dependent effects are a fact of life for designers working at the more advanced process nodes and become critical at 45nm. Besides random and systematic variation effects, reliability effects, such as bias-temperature-instability (BTI), also become prevalent, introducing another dimension of variations that impact parametric yield.

These variations are unavoidable and, in fact, increasing as we move to more advanced nodes, where circuit designers encounter yield problems and need to spend extra effort on variation analysis for yield and performance trade-off. 

On one side, foundries have to double or even triple their efforts to make complicated model libraries to characterize different types of variations, despite having to cover variation sources across the full statistical space –– an impracticality.

Conversely, efficiently running variation analysis with the best use of foundry models becomes critical for circuit designers, and is one of the more challenging aspects of system-on-chip (SoC) design that project teams face daily.

This means design-for-yield (DFY) considerations are more important than ever. And yet, we as an industry may not fully understand device modeling and its impact on DFY results. This is due in large measure to no clear definition of DFY. Some people are confused by DFY and design-for-manufacturing (DFM), and consider DFY a foundry’s responsibility or do not know what the role of DFY is. The value of DFY highly relies on how “good” the foundry models are and how efficient the tool can leverage model information to run needed analysis, such as statistical circuit simulations.

Foundry models can never be perfect, but represent process information that a DFY analysis requires. Designers need to have an appropriate expectation on models, especially for advanced technologies, and also understand model limitations. With this understanding, extracting information from models and making good use of this information together with DFY tools is becoming more critical.

Of course, DFY is not a new phenomenon and tools being categorized for DFY have been available commercially for some time now. They haven’t been widely adopted because they have not provided enough value to project teams due to the lack of information or confidence in the analysis results. Statistical simulation, such as Monte Carlo analysis, has been costly and time consuming, even for a 3s problem. Designers either skip Monte Carlo or often run a small number of samples that can limit the confidence level, making DFY analysis results unreliable and less valuable. Other types of analysis, including process-voltage-temperature (PVT) analysis, also run into similar problems if designers want to cover all corner cases that can easily increase up to hundreds of corners. A faster simulation engine, intelligent statistical analysis algorithms, and better use of foundry model information are the key components that EDA companies need to provide to make DFY tools more practical and reliable.

The final key would be on the application side. Circuit designers need to understand when and where they can apply DFY on top of their traditional design flow, and how to leverage DFY to achieve an optimal yield versus performance-power-area (PPA) trade-off.

Please join Solid State Technology’s own Pete Singer who will moderate a panel discussion on this topic, “Learn the Secrets of Design for Yield,” during the 50th Design Automation Conference (DAC). It will be held Wednesday, June 5, from 1:30 p.m. until 2:15 p.m. in Booth #509 on the Exhibit Floor at the Austin Convention Center in Austin, Texas.

A panel of foundry experts will weigh in with their opinions: Dr. Min-Chie Jeng from Taiwan Semiconductor Manufacturing Co. (TSMC); Dr. Luigi Capodieci from GLOBALFOUNDRIES; and Dr. Bruce McGaughy from ProPlus Design Solutions, Inc. They will share best practices and techniques to manage these sub-nanometer effects to improve manufacturability and yield. You can expect some insights into how foundries handle variations and how models are created. They will discuss how EDA companies handle variations in their tools, making variation analysis faster yet still reliable. And finally, attendees can expect to get some guidance and advice on how to better use foundry models and how to better use DFY tools in real designs.

As an organizer, along with Tom Wong of GLOBALFOUNDRIES, I expect to learn plenty and will share some of the conclusions in future blogs, including whether design for yield is the same as design for manufacturing.

About Zhihong Liu

Dr. Zhihong Liu is executive chairman of ProPlus Design Solutions, Inc. He was most recently corporate vice president for CSV R&D at Cadence Design Systems Inc. Dr. Liu co-founded BTA Technology Inc. in 1993 and invented BSIMPro, the leading SPICE modeling product. He also served as the president and chief executive officer of BTA Technology Inc. and later Celestry Design Technology Inc., acquired by Cadence in 2003. Dr. Liu holds a Ph.D. degree in Electrical Engineering from the University of Hong Kong and co-developed the industry’s first standard model (BSIM3) for IC designs as one of the main contributors at the University of California at Berkeley.

by Debra Vogler, SEMI

In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.

Likely enhancements on the logic roadmap below 20nm are a move to FinFET, improved FinFET implementation, high mobility channel, and gate all around (GAA) structures, noted Adam Brand, senior director, Transistor Technology Group at Applied Materials. He told SEMI that, “The increased complexity of the FinFET, high mobility channel, and GAA devices in combination with continued scaling requires more precision in structure formation and improved materials to address structure formation and parasitic effects.”

The key steps for maintaining the structural integrity of the fin are precision etch, void-free STI fill, recess, and precisely tailored corner rounding through dummy gate oxidation. Dummy gate oxidation addresses the challenge of ensuring that electric fields can be avoided in the corner explained Brand, who will present at SEMICON West 2013 (http://www.semiconwest.org). “The dummy gate serves two purposes,” said Brand. “It’s a structural element and it’s there when you do the transistor formation so it can serve roles such as being the etch stop for the gate etch. It’s also able to play a role in shaping the fin.” The fin can be shaped by changing the oxidation rate depending on the amount of oxidation needed for the side vs. for the corner.

Precision again comes into play when forming the gate — precision CMP is required to control the dummy gate and replacement metal gate height. The dummy gate material must also be easily removed. “Advanced CVD materials offer more choices in materials for differentiating selective removal,” said Brand. “Implant-based precision material modification (PMM) has been effective in changing selectivity to obtain better structure control.” He noted that in the past, CMP had not played a role in directly affecting the geometry of the transistor, but now, it is playing a much more direct role in determining the size of the transistor features. For example, in the replacement metal gate step, CMP is used to polish the metals used for the replacement gate structure and it’s also used for the self-aligned contact polish. “So now, you’re polishing the gate at least three times in order to form it, and you need very precise gate height control because it affects the overall stack height and contact height.”

Further complicating transistor scaling is that the 3-D structure adds complexity in strain-related mobility enhancement. “Source/drain stressor shaping is needed to optimize strain and control unwanted increase in the Miller capacitance,” said Brand.  “Lower k dielectrics are also needed to manage the Miller capacitance.” He further explained that when strain is implemented in a FinFET, each source/drain area is a separate fin — as opposed to when strain is being implemented on planar devices. “When you grow the source/drain [in a FinFET], it grows both horizontally and vertically, so when you scale the pitch of the fins, there’s the challenge that eventually those source/drain stressors come very close to each other and they might merge.” The solution, therefore, has to allow the stressors to grow without having them merge between the transistors and still obtain the amount of strain that is wanted. The solution must also address the Miller capacitance. 

The SOI value proposition changes below 20nm

Gary Patton, VP at IBM’s Semiconductor Research and Development Center, told SEMI that in order for the full benefit of the FinFET to be realized below 20nm, a dielectric isolation scheme is necessary to counter the uniformity and variability challenges. “The arrival of the FinFET era has brought about a fundamental paradigm shift in the SOI value proposition such that the advantages of SOI-based innovation now extend well beyond just device performance as in the planar case,” said Patton.  Indeed, Soitec, and others, such as STMicroelectronics, are betting that SOI-based technology will be used as a bridge enabling the industry to get the performance benefits of a fully-depleted transistor while staying with a planar transistor all the way from 28nm down to 14nm, or perhaps even sub-14nm.

To those who question the added cost of going with an SOI-based platform, Patton said that the cost of dealing with the isolation challenge offsets the cost of using SOI substrates. “Offset costs are due to both additional process steps required for bulk, and increases to die area,” said Patton. “An STI isolation module must be added for bulk FinFETs, as well as a series of masking steps and implants for isolation-leakage control and latch-up avoidance. Estimated additional processing costs of bulk isolation offsets the cost advantage of bulk substrates over SOI.” He also pointed out that die area increases are driven by the need for well contacts, and I/O guard-rings (latch-up avoidance). “We also anticipate the overall die yield to be challenging for the bulk FinFET process due to variability and the need for matching performance of critical circuit paths in a chip.”

Another consideration for proponents of SOI-based technology is the issue of process variability. “A buried oxide layer (BOX) in SOI fins is responsible for three areas of improvement in variability over bulk-isolated FinFETs,” Patton told SEMI. “First, the top silicon layer is terminated by the buried oxide, is proven to be extremely uniform in thickness, and defines the height of the fin both physically and electrically, since any fin over etch does not contribute to the fin height.” He further explained that the source and drain are completely separated by the gated channel, unlike in a bulk FinFET, where there is a continuous path for leakage, requiring a highly doped punch-through stop.

“The non-abrupt nature of doping introduces a non-uniform doping profile, and hence, turn-on current, between the top and bottom of the fin, further eroding the FinFET advantage.” Patton noted that a more practical consideration is the slope or taper of the fin itself. “From an electrical point of view, the ideal fin would be perfectly vertical and of uniform thickness from top to bottom. In a bulk fin process, a degree of taper must allow for the subsequent oxide fill and etch-back, and also to accommodate a reduced spacer over-etch budget (vs. an SOI fin). The fin taper introduces further non-uniformity to the FinFET, which reduces switching speed.”

EDA tackles variability

Reducing/mitigating process variability is ever more critical to yield as the industry scales transistors below 20nm, and much can be done in the design arena to help. For example, EDA considerations can mitigate “noise” in the optical system [lithography] that is a source of variability.

Mike Rieger, group director, R&D, Silicon Engineering Group at Synopsys, uses communication theory to analyze certain aspects of a lithographic system. He told SEMI that when there are optical systems [lithography] without tuning, i.e., a “plain vanilla” system — all the spatial frequencies in the visible limit are present. Conversely, when the design is friendly to specific spatial frequencies and you then try to print that design with an optical system that is friendly to all spatial frequencies, there are other frequencies that leak through. This “leakage” causes a lowering of the contrast in the optical image. “With the lower contrast, the image is more susceptible to other sources of variation like defocused variation, or dose variation, and that translates into your printed features having more variation in their dimensions,” said Rieger, another speaker at the upcoming SEMICON West (http://www.semiconwest.org).

Rieger added that, if you can prevent the unwanted frequencies from even being passed through the optical system, the net result is that the contrast is improved. Additionally, by tuning these frequencies, the diffraction orders in the stepper (the rays of light used to form the image) are manipulated. “You can eliminate the zero order ray. This zero order ray reduces contrast and it also limits the maximum frequency that you can image.” The tuning process – also known as source mask optimization (SMO) – really isn’t the end game, noted Rieger. “It’s source design optimization that is the end game. You tune the configuration of your design to be consistent with the optimization of the source.”

Regarding the parallel paths the industry is taking – extending optical lithography while developing EUVL — Rieger is realistic in his assessment of what EDA can bring to the table. “We’re going to be using 193i for the foreseeable future — it will be years before 193i is replaced,” said Rieger. But, “Optical lithography on a single exposure is maxed out in terms of the density it can print, so if you want to get more transistors per chip or more details per chip, you must do a couple of things.” Those are: tuning the optics, which comes at a cost, and using multiple exposures. “To get an effective result, the whole process of the tuned optics and the multiple exposures must be comprehended in the physical layout software, and some of the things that need to be done go beyond what you can accomplish with the traditional rule-based constraint that you put on the layout.”

For more information on SEMICON West 2013, visit http://www.semiconwest.org. To view all the TechXPOT info, visit http://www.semiconwest.org/SessionsEvents/TechXPOTs.

Register through June 7 at only $50 here: http://www.semiconwest.org/registration. Note that registration fees increase on June 8.

 

Critical trends and developments in the technologies, methodologies, and applications challenges in semiconductor test will be presented at the 6th annual IEEE Test Vision 2020 Workshop held in conjunction with SEMICON West 2013, on July 10-11 at the San Francisco Marriot Marquis Hotel. The one and one-half day workshop will feature speakers from Flextronics, Broadcom, Qualcomm, Texas Instruments, AMD, ON Semiconductor, Mentor Graphics, Micron, along with those from key semiconductor test industry suppliers. Organized by SEMI and sponsored by the IEEE Instrumentation and Measurement Society, Test Vision 2020 is a two-time winner of the ATE Test Technology Technical Council’s “Most Successful Event” Award.  Registration for Test Vision 2020 is now open at www.testvision2020.com, and includes free admission to SEMICON West.

Test Vision 2020’s purpose is to facilitate learning, forecasting and debate on the future of semiconductor test and serves as a valuable platform where leading foundries, IDMs and fabless companies discuss their critical test requirements with leading test equipment and solution providers.  This year’s program will feature panel discussions and leading industry experts that focus on the following key questions:

  • How can we achieve faster time to market with lower product costs?
  • What are the Test challenges in emerging technologies?
  • How much Test is enough?
  • What are the possible paths to economical high-speed test?
  • What are the next big innovations in Semiconductor Test?
  • What will be the new skills and competencies needed by future test engineers?

The keynote speaker for Test Vision 2020 will be Dr. Erik Volkerink, chief technology officer at leading end-to-end supply chain powerhouse, Flextronics.  He will present on the topic, “Product Foundry: Next Paradigm in Product Design and Engineering.” Featured speaker will be Sri Jandhyala, Strategic Marketing Director for ON Semiconductor, whose presentation will be, “LED Lighting — Opportunities, Challenges and the Future.”  Leading test equipment and solution providers will also highlight the latest test developments and trends, including speakers from Advantest, LTX-Credence, Roos Instruments, and Teradyne.

Starting at 3:00 p.m. on Wednesday, July 10 and concluding at 4:45pm on Thursday, July 11, Test Vision 2020 will also include a networking and casual social event on Wednesday evening.

GLOBALFOUNDRIES plans to unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes at next week’s 50th Design Automation Conference (DAC) in Austin, Texas. The sign-off ready flows, jointly developed with the leading EDA providers, offer robust support for implementing designs using sophisticated multi-die packaging techniques, leveraging through-silicon vias (TSVs) in 2.5D silicon interposers and new bonding approaches.

Multi-vendor support is available, with full implementation flows from Synopsys and Cadence Design Systems. Physical verification with Mentor Graphics’ suite of tools is included in the flow.

The GLOBALFOUNDRIES 2.5D technology addresses the challenges of multi-die integration with solutions for front-end steps such as via-middle TSV creation, and flexibility for the backend steps, like bonding/debonding, grinding, assembly, and metrology.

“Our 2.5D technology provides designers with a path to enable heterogeneous logic and logic/memory integration, offering increased performance and reduced power consumption, without the need for additional packages,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “These benefits can now be realized very efficiently with certified design flows that provide support for the additional steps and design rules involved in the design process. By working closely with our EDA partners, we can greatly reduce the development time and time-to-production using the most advanced multi-die approaches.”

The flows allow designer to quickly and reliably address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing. The flows support the need for additional verification steps brought on by 2.5D design rules.

The design flows work with GLOBALFOUNDRIES’ process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

The flows come with a CPU core and memory IP and all the scripts and settings to execute a Synopsys Galaxy Implementation Platform-based flow or Cadence Encounter-based implementation flows with the GLOBALFOUNDRIES PDK. Similarly, the Mentor Calibre 3DSTACK tool is exercised in the flow to verify DRC, LVS and extraction within and between the various die stacks leveraging the same golden design kits as used inside of GLOBALFOUNDRIES .

At next week’s 50th Design Automation Conference (DAC) in Austin, Texas, GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support its most advanced manufacturing processes. The flows, jointly developed with the leading EDA providers, offer support for implementing designs in the company’s 20nm low power process and its 14nm-XM FinFET process. Working closely with Cadence Design Systems, Mentor Graphics and Synopsys, GLOBALFOUNDRIES has developed the flows to address the most pressing design challenges, including support for analog/mixed signal (AMS) design, and advanced digital designs, both with demonstration of the impact of double patterning on the flow.

The GLOBALFOUNDRIES design flows work with its process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

“As the developer of the industry’s first modular 14nm FinFET technology and one of the leaders at 20nm, we understand that enabling designs at these advanced process nodes requires innovative methodologies to address unprecedented challenges,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “By working with a new level of collaboration with EDA partners, we can provide enhanced insight into our manufacturing processes in order to fully leverage the capabilities of 20nm and 14nm manufacturing. This provides our mutual customers with the most efficient, productive and risk-reduced approach to achieving working silicon.”

Production ready AMS flow from specification to verification

To address the unique requirements of analog/mixed signal (AMS) design at advanced processes, GLOBALFOUNDRIES has enhanced its design flows to provide production quality scripts and packaged methodologies. The new reference flow establishes a working flow from specification to physical verification that has been taped out to be verified on working silicon.

The AMS reference flow provides comprehensive double pattern design guidelines. It gives overview of decomposition flow for both block level and chip level. The flow also addresses decomposition for different design styles. Recommendations for color balancing, hierarchical decomposition, ECO changes are discussed. The flows also present decomposition impact on DRC run time and resulted database size.

Notably, the reference flow includes support for efficiency and productivity improvements in the Cadence Virtuoso environment specifically for designing in a double patterned process. The flow includes support for Virtuoso Advanced Node 12.1 and provides efficient access to the tool’s productivity benefits for physical design with real-time, color-aware layout. Circuit designers can assign “same net” constraints in the schematic, and the layout designers can meet these requirements as they create the physical view. Additionally, layout designers can take advantage of Virtuoso tool support for local interconnect, and advanced layout dependent effect management.

The flow also features interoperability with Mentor’s Calibre nmDRC, nmLVS, and extraction products which address multipatterning requirements for both double and triple patterning. In addition special settings for analog design; auto-stitching and when to use it; and fill and color balancing are described in detail.

The AMS flow provides detailed information on parasitic extraction and layout dependent effects, both of which introduce new challenges at 20nm and 14nm. For parasitic extraction, the flows are described in detail and customizable scripts and examples demonstrate OA and DSPF back annotation. In addition the flows illustrate methodologies to predict layout-dependent effects during schematic design and methods to include full models in post layout extraction. PEX flows for Synopsys StarRC extraction, Cadence QRC and Mentor CalibrexRC are supported.

These flows serve as references to validate the correctness of the accompanying PDK as well as the vendor tools setup.

Sign-off ready RTL2GDSII flows that address double patterning

GLOBALFOUNDRIES is also making available new flows that support a complete RTL-to-GDSII design methodology for targeting its 20nm and 14nm manufacturing processes. The company worked with EDA vendors to certify the flows in their respective environments and provide a platform for optimized, technology-aware methodologies that take full advantage of the performance, power and area benefits of the processes.

The result is a set of fully executable flows containing all the scripts and template files required to develop an efficient methodology. The flows serve as a reference to validate the correctness of the accompanying PDK as well as the vendor tool setup. In addition the flows offer access to other critical and useful information, such as methodology tutorial papers; guidelines and methodologies for decomposition of double patterned layouts; PEX/STA methodology recommendations and scripts; and design guidelines and margin recommendations.

A critical aspect of manufacturing at this level is the use of double patterning, an increasingly necessary technique in the lithographic process at advanced nodes. Double patterning extends the ability to use current optical lithography systems and the GLOBALFOUNDRIES flows provide comprehensive double pattern design guidelines. They address design for double patterning and the added flow steps for different design styles and scenarios.

This includes support for odd cycle checking, a new type of DRC rule that must be met to allow for legal decomposition of the metals into two colors. This check is detailed in the flow and guidelines are provided to make sure it is met.

Synopsys and GLOBALFOUNDRIES worked together to minimize the impact of changes associated with the 3-D nature of FinFET devices as compared to planar transistors.  The two companies focused on making FinFET adoption transparent to the design team.  The collaboration on Synopsys’ RTL to GDSII flow includes 3-D parasitic extraction with the Synopsys StarRC tool, SPICE modeling with the Synopsys HSPICE product, routing rules development with the Synopsys IC Compiler tool and static timing analysis with the Synopsys PrimeTime tool.

Cadence contributed a complete RTL-GDSII flow, including physical synthesis, and planning and routing developed with the Encounter Digital Implementation (EDI) System foundation flow. The seamless implementation flow, using Cadence Encounter RTL Compiler and EDI System, supports double patterning and advanced 20- and 14-nm routing rules.

Mentor’s Olympus-SoC place and route system is supported in the flow, providing support for new DRC, double patterning, and DFM rules. The Olympus-SoC router has its own native coloring engine along with verification and conflict resolution engines that detect and automatically fix double patterning violations. Expanded features include DP-aware pattern matching, coloring aware pin access, pre-coloring of critical nets, and DP aware placement. The Calibre InRoute product allows Olympus-SoC customers to natively invoke Calibre signoff engines during design for efficient and faster manufacturing closure.

Double patterning also impacts LVS and other DRC issues, and the flows provide methodology details to address these areas, including hierarchical decomposition to reduce data base explosion. Parasitic extraction methodologies and scripts are provided as well, offering ways to address double patterning-induced variations via DPT corners or with maskshift PEX features.

Peregrine Semiconductor Corporation, a fabless provider of high-performance radio frequency integrated circuits (RFICs), today announced the signing of a collaborative agreement with Murata Manufacturing Company on a multi-sourcing arrangement for RF switches based on Peregrine’s proprietary UltraCMOS technology. Under the collaboration agreement, Murata agrees to source a majority of its RF switching requirements from Peregrine in exchange for being granted a license to purchase or manufacture RF CMOS switches utilizing Peregrine’s technology and intellectual property (IP). The parties expect this agreement to result in an expanded source of supply for these critical RF components and to assure global OEMs broad access to RF CMOS products.

Peregrine Semiconductor pioneered RF CMOS-based devices with its UltraCMOS technology, a form of silicon-on-insulator (SOI) process, and more than 20 years of research and development have resulted in 150 patents issued and pending. With this strong IP portfolio, Peregrine has established its position in the RF front-end section of mobile devices for RF switches and tunable RF components.

Murata is a supplier of RF front-end (RFFE) modules for the global mobile wireless marketplace. RF front-end modules are products that incorporate RF switches and tuning devices with SAW filters, passive components, and advanced packaging techniques.

“Global OEM customers of both Peregrine and Murata have for some time requested that the companies implement an independent source of supply for the critical switching elements that are widely utilized in today’s smart phones and other wireless-communications products,” said Jim Cable, Peregrine’s president and CEO. “This agreement marks the first license of Peregrine’s switch-based intellectual property to a third party; we look forward to working collaboratively with Murata to expand the deployment of UltraCMOS technology.”

Aptina’s board of directors yesterday announced that Phil Carmack has joined Aptina as chief executive officer and as a member of the board of directors. Aptina is a provider of CMOS image sensor solutions.

“We are extremely pleased that Phil is joining Aptina. Phil’s impressive industry experience and leadership skills will unleash Aptina’s potential and take the company to the next level,” said Nicholas Brathwaite, chairman of the board of Aptina.

Carmack most recently served as the senior vice president for NVIDIA’s Mobile Business Unit, which he established in 2003. Prior to his 13 years at NVIDIA, Carmack was the executive vice president of Research and Development at 3DFX Interactive, Inc. which was acquired by NVIDIA. His professional experience also includes leadership positions with innovative Silicon Valley companies including senior vice president and COO for Gigapixel and chief executive officer and founder of Raydiant, Inc. Carmack earned a Bachelor of Science degree in Electrical Engineering at Brigham Young University and a Master of Science degree in Electrical Engineering from Stanford University.

Carmack succeeds Nicholas Brathwaite who has been Aptina’s interim CEO since August 2012. Brathwaite will continue in his role as the chairman of the board of directors for Aptina, a position he has held since July 2009.

Aptina is a global provider of CMOS imaging solutions that enable Imaging Everywhere.

Association Connecting Electronics Industries announced today the April findings from its monthly North American Printed Circuit Board (PCB) Statistical Program. Notable among the month’s findings is the PCB book-to-bill ratio, which reached 1.10, its highest level since July 2010.

PCB bookings gain strength

Total North American PCB shipments were down 7.0 percent in April 2013 from April 2012, but bookings increased 7.2 percent year over year. Year to date, PCB industry shipments were down 5.1 percent and bookings were down 2.3 percent. Compared to the previous month, PCB shipments in April decreased 9.9 percent, and bookings declined 14.3 percent. Bookings have outpaced shipments for the past five months.

“North American PCB sales in April continued to lag behind 2012 levels, although sales in the flexible circuit segment are strengthening,” said Sharon Starr, IPC director of market research.  “Rigid PCB orders for the month exceeded last year’s orders and continued to push the book-to-bill ratio up to a strong 1.10. This is the fifth consecutive monthly increase in the ratio, which reinforces our hope that PCB sales will strengthen during the coming months.”

The book-to-bill ratios are calculated by dividing the value of orders booked over the past three months by the value of sales billed during the same period from companies in IPC’s survey sample. A ratio of more than 1.00 suggests that current demand is ahead of supply, which is a positive indicator for sales growth over the next three to six months.

Domestic production holds steady

IPC’s monthly survey of the North American PCB industry tracks bookings and shipments from U.S. and Canadian facilities, which provide indicators of regional demand. These numbers do not measure U.S. and Canadian PCB production. To track regional production trends, IPC asks survey participants for the percent of their reported shipments that were produced domestically (i.e., in the USA or Canada). In April 2013, 85 percent of total PCB shipments reported by survey participants were domestically produced. These numbers are significantly affected by the mix of companies in IPC’s survey sample, which change slightly in January, but are kept constant through the remainder of the year.

Interpreting the data

Year-on-year and year-to-date growth rates provide the most meaningful view of industry growth. Month-to-month comparisons should be made with caution as they may reflect cyclical effects and short-term volatility. Because bookings tend to be more volatile than shipments, changes in the book-to-bill ratios from month to month may not be significant unless a trend of more than three consecutive months is apparent. It is also important to consider changes in bookings and shipments to understand what is driving changes in the book-to-bill ratio.