Category Archives: Semiconductors

Samsung Vice-President Kwon Oh-hyun released a statement today, apologizing for the fatal hydrofluoric acid spill that left one worker dead and four others injured. According to the Wall Street Journal, Kwon said that the company will “fundamentally change” its environmental safety system and investigate its processes to ensure that such an accident never happens again. Additionally, Samsung also plans to withdraw its application for the plant, located in Hwaseong, Korea, certified as “green,” with no intention of resubmitting the application for the next five years.  

The accident, which occurred in late January, has resulted in a fair amount of controversy for Samsung: after initially being investigated for covering up the leak, the Korean police denied Samsung’s statement that the accident that the leak was contained.

“We’ve always taken great pride in the high standards we set for our operations and the safety measures we have in place,” Samsung’s spokesperson told the Wall Street Journal. “In keeping with our commitment to operating high-quality facilities, we are committed to continually making enhancements to our protocols to ensure we are protecting the safety and well-being of our employees, partners and the local community.”

Hydroflouric acid, both in liquid and vapor forms, can cause severe burns, which may or may not be visible immediately after exposure. HF penetrates the skin, causing damage to the underlying tissues, including bones and organs, in severe cases. Inhalation of HF vapors can also cause burns in the mouth, esophagus and lungs. Click here to learn more about what your first response to an HF spill should be.

Are you prepared for cleanroom disaster?

Chances of a catastrophic cleanroom incident are typically slight, but even semiconductor giants like Samsung are not immune to the possibility. Bryan Swales is managing director of Relelectronic-Remech, which specializes in the recovery of technical equipment following contamination and damage events. He writes that developing an incident recovery plan pre-disaster is key to weathering both the immediate physical dangers and the public relations mess that can ensue after a cleanroom disaster. The plan, Swales said, should identify each type of disaster which could occur, and define how the organization will react to each.

“When properly developed and implemented, including ongoing training of all relevant personnel,” said Swales, “an incident recovery plan represents a pro-active, designed-in emergency response and management program unique to the organization and covering all ‘foreseeable’ disastrous events.”

200mm wafer processingDeposition Sciences, Inc. (DSI), manufacturer of highly durable thin film optical coatings, today introduced an enhanced capability to manufacture patterned optical filters. DSI has increased its capacity and resolution with the introduction of a new photolithography production line capable of patterning 200mm diameter wafers.

 “We are very excited to announce this enhanced capability,” said Michael Newell, director of sales and marketing.  “This new manufacturing line brings us better resolution, increased capacity, an ability to yield and coat more parts per wafer, and ultimately better pricing for our customers. And we are keeping pace with the semiconductor industry. Customers are looking to integrate their electronics with the optical filters. DSI can pattern populated wafers containing active devices, and semi-conductor fab houses are doing more and more at the 200mm wafer scale.”

The new patterning capability provides an enhanced view or enhanced detection in multi-spectral imaging tasks by fusing together information from different wavelength bands.  Other applications include satellite imaging, UAV overhead reconnaissance, machine vision, food and industrial inspection, automotive, biomedical sensing, color filter arrays for CCD and CMOS cameras, reticles, and more. 

For over 25 years, Deposition Sciences has produced optical thin film filter coatings.  DSI’s coating capability ranges from the ultraviolet (UV), through the visible and includes near-infrared (NIR), midwave-infrared (MWIR) and out to the longwave-infrared (LWIR). 

laser for wafer processingCoherent, Inc. (Nasdaq: COHR) has expanded its family of industrial ultrafast lasers with the new Talisker 1000 series. This new series of high power picosecond lasers is designed for high-throughput, precision materials processing applications in the semiconductor, solar (photovoltaics), medical devices, consumer electronics and automotive industries. The Talisker 1000 has three single wavelength versions available – near infrared (1064 nm), green (532 nm) and ultraviolet (355 nm) – all at 1000 kHz.  The near IR is ideal for scribing and engraving stainless steel and other metals.  The green wavelength delivers higher precision, perfect for several high value exotic metals.  The UV is optimal for processing glass and other transparent or brittle materials.  Specific examples include glass cutting for smartphone touchscreens; drilling injector nozzles for automotive and medical dispensing; processing plastic electronics such as OLEDs; engraving steel for printing fabrics and currency, or patterning metals on ceramic substrates for high power RF electronics.

Picosecond lasers enable precision materials process with superior spatial resolution and virtually no peripheral thermal effects. The new Talisker 1000 offers pulse repetition rates as high as 1 MHz, which helps enable higher throughput in many applications.  With average powers as high as 25 Watts, this new laser series is identical in form, fit and function to earlier lower power Talisker models, simplifying tool redesign cycles.

Founded in 1966, Coherent, Inc. provides photonics-based products to the commercial and scientific research markets, and is part of the Standard & Poor’s SmallCap 600 Index and the Russell 2000. 

Global sales of semiconductors in January rose year-over-year, yet fell on a sequential basis as ongoing economic uncertainty is holding back more robust growth, iStockAnalyst today reported.

Worldwide sales of semiconductors were $24.05 billion the month of January, up 3.8% from January 2012 and down 2.8% from December 2012, according to the Semiconductor Industry Association (SIA).

"The across-the-board spending cuts that hit last week and the threat of a government shutdown later this month are just the latest examples of fiscal disruptions that sidetrack economic growth," said SIA CEO Brian Toohey.

On a regional basis, semiconductor sales rose 10.5% and 7.8% in the Americas and Asia Pacific respectively, but dropped 4.9 percent and 12.3 percent in Europe and Japan from the same period last year.

North and South America post best January of the last decade, the SIA noted.

Compared with December 2012, sales inched up 0.4 percent in Europe, while declining 5.5% in Japan, 3.5% in the Americas and 2.5 percent in Asia Pacific.

Semiconductor sales in the United States totaled more than $146 billion in 2012.

After experiencing a slowdown in 2012, the global semiconductor market is set for growth. The World Semiconductor Trade Statistics predicts the global semiconductor market to grow by 4.5% in 2013 after declining 3.2 percent in 2012. The SPDR S&P Semiconductor ETF (XSD) has gained over 7% year-to-date. Five Star Equities examines the outlook for companies in the semiconductor industry and provides equity research on Avago Technologies Ltd. and NVIDIA Corporation.

The global semiconductor industry posted total sales of $291.6 billion in 2012, according to the Semiconductor Industry Association. The total was the third highest ever, but a decline of 2.7 from the record $299.5 billion set in 2011. The industry began to show some strength in the fourth quarter as it posted sales of $74.2 billion, which was a year-over-year increase of 3.8%.

"Despite substantial macroeconomic challenges, the global semiconductor industry outperformed forecasts and posted one of its highest yearly sales totals in 2012," said Brian Toohey, president and CEO, Semiconductor Industry Association. "Recent momentum, led by strength in the Americas, has the industry well-positioned for a successful 2013."

Avago Technologies serves three primary target markets: wireless communications, wired infrastructure, industrial and automotive electronics.

Five Star Equities provides market research focused on equities that offer growth opportunities, value, and strong potential return and was not compensated by any of the companies listed in its report.

Tensoft, an end-to-end ERP and supply chain solution provider for the semiconductor industry, announced today an agreement with GEO Semiconductor, the industry leader in high-performance, geometric processing solutions and inventor of the "eWarp" and "Realta" technology platform, to implement Tensoft’s integrated solution for the semiconductor industry, including Microsoft Dynamics and Tensoft Fabless Semiconductor Management (FSM). Tensoft’s FSM is a web-based product that supports semiconductor and related industry manufacturing processes.

GEO Semiconductor recently grew dramatically through its acquisition of Maxim Integrated’s Digital Video Processing Business. While this acquisition helps accelerate their market and corporate growth, it has also presented the need for additional infrastructure to support this growth, including an ERP and supply chain system that can be deployed very quickly.

"We needed a way to instantly scale in order to service our new customers following the Maxim product acquisition. Tensoft FSM has a known track record that we’re confident will allow us to meet this need," said Eric Erdman, GEO’s CFO. "Tensoft’s solution will enable our company to service our customers and to seamlessly manage all aspects of GEO’s production and financial operations."

"We’re really pleased to be working with Eric for a second time," said Bob Scarborough, Tensoft President and CEO. "It’s great to get the confirmation of repeat business — it’s a solid endorsement of our ability to be a trusted partner and to add value to rapidly growing companies. And, we really thrive on the challenge of delivering our products and adding our expertise in this kind of environment."

GEO Semiconductor develops programmable, high-performance geometric processor ICs, H.264 CODECS, video, audio and human interface technologies, focusing on smartphone peripherals, automotive cameras & HUDs, Smart TV, cloud and Skype communications as well as surveillance & video communication markets. The company is located in Santa Clara, CA with offices in Toronto and Orlando, and sales channels around the globe.

The adsorption of ions in microporous materials governs the operation of technologies as diverse as water desalination, energy storage, sensing and mechanical actuation. Until now, however, researchers attempting to improve the performance of these technologies haven’t been able to directly and unambiguously identify how factors such as pore size, pore surface chemistry and electrolyte properties affect the concentration of ions in these materials as a function of the applied potential.

Georgia Tech researchers
Georgia Tech associate professor Gleb Yushin (left) and graduate research assistant Sofiane Boukhalfa examine experimental results from their study of the adsorption of ions. (Credit: Gary Meek)

To provide the needed information, researchers at the Georgia Institute of Technology and the Oak Ridge National Laboratory have demonstrated that a technique known as small angle neutron scattering (SANS) can be used to study the effects of ions moving into nanoscale pores. Believed to be the first application of the SANS technique for studying ion surface adsorption in-situ, details of the research were reported recently in the journal Angewandte Chemie International Edition.

Using conductive nanoporous carbon, the researchers conducted proof-of-concept experiments to measure changes in the adsorption of hydrogen ions in pores of different sizes within the same material due to variations in solvent properties and applied electrical potential. Systematic studies performed with such a technique could ultimately help identify the optimal pore size, surface chemistry and electrolyte solvent properties necessary for either maximizing or minimizing the adsorption of ions under varying conditions.

“We need to understand this system better so we can predict the kind of surface chemistry required and the kinds of solvents needed to control the levels of ion penetration and adsorption in pores of different sizes,” said Gleb Yushin, an associate professor in the Georgia Tech School of Materials Science and Engineering. “Understanding these processes better could lead to the development of improved energy storage, water purification and desalination systems. This new experimental methodology may also give us paths to better understand ion transport in biological systems and contribute to the development of improved drugs and artificial organs.”

Georgia Tech associate professor Gleb Yushin (left) and graduate research assistant Sofiane Boukhalfa assemble a test cell used to study the adsorption of ions. (Credit: Gary Meek)

The research was supported partially by the U.S. Army Research Office, the Georgia Institute of Technology and the Oak Ridge National Laboratory (ORNL).

“The advantage of neutron scattering is that it can be used to study real systems,” said Yushin. “You can study most electrode materials and electrolyte combinations as long as they have a high sensitivity for neutron scattering.”

Yushin and his collaborators – Georgia Tech graduate research assistant Sofiane Boukhalfa, and Oak Ridge scientists Yuri Melnichenko and Lilin He – conducted the research using ORNL’s High Flux Isotope Reactor, which produces a beam of high-energy neutrons. Their experimental setup allowed them to immerse activated carbon fabric samples – each sample containing pores of different sizes – in different electrolyte materials while varying the applied electrical potential.

By measuring how the neutron beam was scattered when it passed through the carbon fabric and electrolytes, the researchers could determine how the solvent, pore size and electrical potential affected the average ion concentration in the carbon material samples.

This schematic shows the experimental setup for in-situ studies of ion adsorption on the surface of microporous carbon electrodes. (Credit: Gleb Yushin)

“You can learn whether the ions get adsorbed into small pores or large pores by simply comparing the changes in the neutron scattering,” Yushin explained. “This experimental technique allows us to independently change the surface chemistry to see how that affects the ion concentrations, and we can use different solvents to observe how the interaction between electrolyte and pore walls affects the ion adsorption in pores of different sizes. We can further identify exactly where the ion adsorption takes place even when no potential is applied to an electrode.”

Earlier work in this area had not provided clear results.

“There have been multiple prior studies on the pore size effect, but different research groups worldwide have obtained contradictory results depending on the material selection and the model used to determine the specific surface area and pore size distribution in carbon electrodes,” Yushin said. “Neutron scattering should help us clarify existing controversies. We have already observed that depending on the solvent-pore wall interactions, either enhanced or reduced ion electro-adsorption may take place in sub-nanometer pores.”

In their experiments, the researchers used two different electrolytes: water containing sulfuric acid and deuterium oxide – also known as heavy water – which also contained sulfuric acid. The two were chosen for the proof-of-concept experiments, though a wide range of other hydrogen-containing electrolytes could also be used.

Now that the technique has been shown to work, Yushin would like to expand the experimentation to develop better fundamental understanding about the complex interactions of solvent, ions and pore walls under applied potential. That could allow development of a model that could guide the design of future systems that depend on ion transport and adsorption.

“Once you gain the fundamental knowledge from SANS experiments, predictive theoretical models could be developed that would guide the synthesis of the optimal structures for these applications,” he said. “Once you clearly understand the structure-property relationships, you can use materials science approaches to design and synthesize the optimal material with the desired properties.”

Information developed through the research could lead to improvements in supercapacitors and hybrid battery-capacitor devices for rapidly growing applications in hybrid electrical vehicles, energy efficient industrial equipment, smart grid-distributed energy storage, hybrid-electric and electrical ships, high-power energy storage for wind power and uninterruptible power supplies.

GLOBALFOUNDRIES last week announced additional enhancements to the foundry’s 55nm Low-Power Enhanced (LPe) process technology platform – 55nm LPe 1V – with qualified, next-generation memory and logic IP solutions from ARM. The 55nm LPe 1V is the industry’s first and only enhanced process node to support ARM’s 1.0/1.2V physical IP library, enabling chip designers to use a single process that supports two operating voltages in a single SoC.

“The key advantage of this 55nm LPe 1V offering is that the same design libraries can be used whether you are designing at 1.0 voltage or 1.2 voltage power option,” said Bruce Kleinman, Vice President of Product Marketing at GLOBALFOUNDRIES. “What it means is that same set of design rules and models can be adopted, with no extra mask layer or special process required. This translates into cost saving and design flexibility without compromising on the power and optimization features.”

Based on ARM’s 1.0V/1.2V standard cells and memory compilers, GLOBALFOUNDRIES 55nm LPe 1V enables designers to optimize their design for speed, power and/or area and is especially beneficial for designers who are faced with power constraints in designing System-on-Chip solutions.

ARM offers a comprehensive, silicon-validated platform of 8-track, 9-track and 12-track libraries along with high-speed and high-density memory compilers for GLOBALFOUNDRIES’ advanced 55nm LPe process.

“The combination of 1V and 1.2V operation along with supporting level shifting logic provides the best combination of low power, high performance and reduced chip area,” said Dr. John Heinlein, vice president of marketing, Physical IP Division at ARM. “Dual-voltage domain characterization support coupled with Artisan next-generation memory compiler architecture reduces dynamic and leakage power by more than 35 percent, compared to previously available solutions.”

The 55nm LPe 1V is especially suited for high-volume, battery-operated mobile consumer devices, as well as a broad range of green or energy-saving products. PDK and EDA tools are available now, along with MPW shuttle availability.

Artisan memories offer flexible manufacturing options and are shipping in billions of products worldwide. Part of a broader platform of Artisan physical IP from 65nm to 20nm, these next-generation memories include low voltage and stand-by modes enabling extended battery life, ultra high-speed caches for maximum processor speed, and proprietary design techniques resulting in reduced area for low-cost SoC designs.

This week, India’s Finance Minister P Chidambaram offered incentives to chip makers to set up headquarters in India, in an effort to encourage local electronics manufacturing. However, the response from the industry has been less than positive. Many believe that it is a good start, but far from sufficient.

While presenting the Union Budget for 2013-14, Chidambaram said the Indian government will waive customs duty for plants and machinery in the semiconductor sector.

"We recognize the pivotal role of semiconductor wafer fabs in the ecosystem of manufacture of electronics. I propose to provide appropriate incentives to semiconductor wafer fab manufacturing facilities, including zero customs duty for plant and machinery," Chidambaram said, while presenting the budget.

"A company investing Rs.100 crore or more in plant and machinery during the (next fiscal) period will be entitled to deduct an allowance of 15 percent of the investment," he continued. "This will be in addition to the current rates of depreciation. There will be enormous spill-over benefits to small and medium enterprises."

While India has held its own in terms of semiconductor design, very little manufacturing is currently done in the country. Today, India has close to 4,000 electronics manufacturing units and about 300,000 units directly or indirectly supporting the electronics manufacturing industry. The Indian semiconductor design market is anticipated to grow to $14.5 billion by 2015, according to a report, but India’s electronic products manufacturing sector could shrink by as much as 7% in revenue during that same time, indicating that government efforts may not succeed.

As many in the industry know, the semiconductor industry lives and dies by Moore’s law, making fab-launching business ventures a risky move for any start-up.  With the need for constant equipment upgrades, many companies have turned to “fabless” business models, farming out their chip-making to established foundries.

“Building and running a fab is a complex business that is very sensitive to utilization and improvements in technology,” says Satya Gupta, chairman of the Indian Semiconductor Association. “Somebody who knows the fab business has to run it, not the government.”

Many experts point to India’s rising middle class as the main reason to consider India as a potential location for fabs. Much of India’s electronics are imported, meaning India is currently footing a huge import bill to meet the growing demand. As much as 65% of electronic products demand is currently met by imports, which is estimated to grow from $28 billion in 2011 to $42 billion in 2015, according to industry body Indian Electronics and Semiconductor Association, which also report that local manufacturers could lose out on nearly $200 billion of potential revenue by 2015.

But the import bill isn’t the only factor discouraging potential fab-owners.

"I wish it was as simple as offering an import duty exemption. What about availability of land, power and all other government clearances?" said a senior executive at one of the large computer manufacturers told the India Times, requesting anonymity.

What do you think of India’s efforts to encourage fabs? Let us know your thoughts in the comment section below.

At the International Semiconductor Strategy Symposium (ISS Europe), the European semiconductor industry affirmed its ability to innovate. More than 170 top industry representatives agreed on a number of joint steps and strategic measures to strengthen their competitiveness and sustainability. The controversial question whether the best way to attack future challenges will be "More Moore" or "More than Moore," ended in an expected compromise, namely that the industry should pursuit both strategies concurrently, the participants of a panel expressed. Whilst the More than Moore sector is traditionally strong in Europe, going on with More Moore is important for two to three device makers in Europe and in particular for the European equipment suppliers which export 80% of their products.

In a global scale, the semiconductor industry is approaching the move to 450mm wafer processing technology – a step that promises to greatly boost the productivity of semiconductor manufacturers. However, since the investment to build a 450mm fab easily exceeds the 10 billion dollar mark, this move is regarded as risky and, for this reason, reserved to only the very largest enterprises. In the past, this perspective divided the European industry into two camps – the "More Moore" group that advocates taking on the 450mm challenge, and the "More than Moore" group which shunned this risky investment and preferred to rely on application-oriented differentiation instead.

At the event SEMI Europe, an industry association embracing enterprises that represent the entire value chain and organizer of the ISS Europe, set up a high-ranking panel discussion on options and choices of a single European semiconductor strategy. The panel proved that entrepreneurial spirit is well alive among Europe’s chipmakers, technology suppliers and researchers.

Time is ripe to close the ranks and take on the challenges, as the speakers in the panel pointed out. Judged on the basis of its expertise and abilities, the European semiconductor and equipment industry has remarkable strengths, the experts said unanimously.

"We have to think in European terms," said Luc Van den hove, CEO of the Belgian research center Imec. "Talking in a common voice allows the European Commission to act and support this industry".

Jean-Marc Chery, Chief Manufacturing & Technology Officer of chipmaker STMicroelectronics, reminded that a holistic approach is necessary. "We have to push the full value chain cooperatively," he said.

The panel participants recognized that the European semiconductor industry possesses the necessary expertise. So far, the willingness to jointly face these challenges has been affected adversely by the macroeconomic environment and the Euro crisis, which discouraged far-reaching strategic decisions. The members of the European Commission that recently signalized understanding the needs of the semiconductor industry’s vital role for the high-tech location Europe, certainly contributed to the optimism in the industry.

"We have all the knowledge, the materials and the equipment," said Rob Hartman, Director Strategic Program for leading equipment manufacturer ASML, during the panel. "Let’s do it in the EU."

European Commissioner Neelie Kroes’ idea of creating an "Airbus for chips," a European initiative for the semiconductor industry comparable to the initiative that once led to the launch of the Airbus in the aviation industry, was strongly hailed by the panel.

"An Airbus for chips could be a very powerful tool," Van der hove said. "It does not need to be a single company, it also can be a framework of companies," added Laurent Malier, CEO of French research centre CEA-LETI.

The main concern of the industry is the slow decision process of the European institutions due to a complex political approval process inside of the European Union, the participants agreed. This industry is moving fast and so the decisions have to be taken fast, too. The strong Euro and the lack of qualified labor are further regarded as potential stumbling blocks for the technological progress and the business competitiveness.

At the panel the European Commission signalized its support for the industry as well.

“If policy instruments would be combined on EU and national levels, a critical mass of support for R&D for both More than Moore and More Moore could be achieved,” said Khalil Rouhana, Director Components & Systems at the European Commission.