Category Archives: Semiconductors

Luminescent Technologies Inc., a provider of computational metrology and inspection solutions for the global semiconductor manufacturing industry, and Dai Nippon Printing Company, Ltd. announced today the successful completion of the first phase of a three-year joint development program for computational metrology and inspection using Luminescent’s Automated Image Processing Hub (LAIPH) platform.  The goals of the collaboration are to dramatically reduce photomask defect review and analysis cycle time while simultaneously improving overall mask quality. The first phase resulted in the successful implementation of LAIPH Aerial Image Analyzer (AIA) software in DNP’s Kami-Fukuoka photomask production plant.

“Today’s advanced design technologies for semiconductors require sophisticated software to enable quick and accurate disposition of reticle defects for state-of-the-art lithography tools,” said Mr. Hideyoshi Takamizawa, deputy general manager of Photomask Technical Department, 1st Production Division, Fine Electronics Business Operationsof DNP.  “We are impressed with results obtained from Luminescent’s AIA software and look forward to extending the use of the LAIPH platform for further applications.”

"We are proud DNP has chosen Luminescent to assist with their world class performance in mask cycle time and quality," added Dr. Linyong (Leo) Pang, Sr. Vice President of Luminescent.  “Our contribution to DNP’s manufacturing success is further proof of the power of computational methods in defect metrology and inspection.”

Aerial Image Analyzer (AIA) is one of the applications on Luminescent’s LAIPH platform to address the growing challenges of inspection in advanced mask shops and wafer fabs. It provides precise quantitative analysis of defect images captured by Carl Zeiss SMT’s Aerial Image Measurement System (AIMSTM) and Applied Materials AeraTM series mask inspection systems. AIA automatically dispositions the defect based on its simulated wafer contour, CD, and location. It improves the equipment’s utilization while offering 100X faster, more comprehensive and consistent analysis than operator’s manual measurements.

Toshiba develops CMOS image sensorToshiba Corporation announced the development of a CMOS image sensor with a small area and low power pixel readout circuits. A sample sensor embedded with the readout circuits shows double the performance of a conventional one. Toshiba presented this development at ISSCC 2013 in San Francisco, CA on Feb. 20.

As demand for commodity mobile phones takes off in emerging markets, CMOS image sensor need to be smaller, consume less power and offer low noise performance. The pixel readout circuits of CMOS image sensors are largely noise reducing correlated double sampling (CDS) circuits, along with a programmable gain amplifier (PGA) and an analog to digital converter (ADC). Serial signal processing architecture is best suited for securing conventional CMOS image sensors with a small area and low power pixel readout circuits, because a PGA and ADC can be shared by many CDS circuits placed in each column area of the sensor. However, smaller size and lower power are still challenges, since noise reduction circuits occupy a large area in the readout circuits, and PGA and ADC have high power consumption.

Key key technologies to overcome these challenges:

1) Column CDS circuits primarily made up of aria-efficient PMOS capacitors. The area of the CDS circuits is reduced to about half that of conventional circuits.

2) In the readout circuits, a level shift function is simultaneously achieved by a capacitive coupling through the PMOS capacitors, allowing adjustment of the signal dynamic range between the column CDS circuits and the PGA and the ADC. This achieves low power and low voltage implementation of the PGA and ADC, reducing their power consumption by 40%.

3) Implementation of a low power switching procedure in the ADC suited to processing the pixel signals of CMOS image sensors. This reduces the switching power consumption of the ADC by 80%.

Toshiba has integrated the three technologies in a sample sensor and confirmed that they double the overall performance of the sensor core. The company now plans to apply CMOS image sensors with the readout circuits to low cost mobile phones and medical cameras in fiscal year 2013.

Toshiba Corporation today announced the development of an innovative low-power technology for embedded SRAM for application in smart phones and other mobile products. The new technology reduces active and standby power in temperatures ranging from room temperature (RT) to high temperature (HT) by using a bit line power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A prototype has been confirmed to reduce active and standby power consumption at 25°C by 27% and 85%, respectively.

Toshiba presented this development at the 2013 International Solid-State Circuit Conference (ISSCC) in San Francisco, CA on February 20.

Longer battery life requires lower power consumption in both high performance and low performance modes (MP3 decoding, background processing, etc.). As low performance applications require only tens of MHz operation, SRAM temperature remains around RT, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from HT to RT.

Toshiba’s new technology applies a BLPC and DCRC. The BLPC predicts power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits. The DCRC greatly decreases standby power in the retention circuit by periodically activating itself to update the size of the buffer of the retention driver.

Toshiba will continue to develop technologies that contribute to high performance, low power system LSI for mobile products.

TESEC Corporation today announced the development and sales of the ULTRA MEMS handler, targeting Inertial (Accelerometer, Gyroscope and Magnetometer) MEMS devices. The ULTRA handler was designed jointly by TESEC and FocusTest, Inc. The ULTRA is a carrier based system with parallel test capabilities for 16, 32, 64 and 96 devices. The system will be available for demonstration and shipment mid-2013.

The overall MEMS market is the fastest growing portion of the semiconductor market, with 2012 revenues of $11.5B and an expected growth rate exceeding 10% for the next several years. According to TESEC’s Director of Sales, Keizo Yamaguchi, “the MEMS handling market is expanding rapidly and with the introduction of the ULTRA, TESEC intends to become a significant supplier to this segment.”

The ULTRA handler provides MEMS device suppliers with a significant throughput enhancement, as a significant portion of devices are being tested today on systems that provide only four to sixteen parallel processing. In addition to significantly higher parallel performance, the ULTRA offers a host of features aimed at higher performance and lower test time. With ±360 degree, 3 axis rotation the ULTRA is capable of providing stimulus for accelerometers and gyroscopes. A magnetic stimulus unit adds magnetometer test capability, making the ULTRA the industry’s first 9 degrees of freedom (DOF) capable system.

Future versions of the ULTRA are planned to expand coverage to address pressure sensor and high G MEMS devices.

“FocusTest brings 20 years of MEMS handling, stimulus and test experience to the ULTRA,” said Richard Chrusciel, ULTRA Product Development Manager, adding: “our partnership with TESEC brings over 40 years of experience and achievement in semiconductor handling, as well as a worldwide organization. The fusion of FocusTest and TESEC will bring world class automation to the MEMS handling market.”

The ULTRA handling and stimulus system is available in ambient and full tri-temperature configurations. Best of all, the unit is priced to avoid sticker shock, with base system configurations targeted to be of equal to or lower cost than current market products.

TESEC will provide world-wide sales/distribution, manufacturing and support for the ULTRA. FocusTest will provide MEMS and test cell specific engineering and applications.

Only light, aerial oxygen, and a catalyst are needed to remove pollutants from water. Ruhr-Universitat Bochum researchers led by Professor Radim Beránek are collaborating with colleagues from seven different countries in order to develop a photocatalyst that is efficient enough to be profitable. For that purpose, they combine sunlight-absorbing semiconductors and nanostructured materials which they optimize for electron transfer processes. The aim is to implement the newly developed photocatalysts into a liquid paint with which photoreactors can easily be coated. The EU supports the project within its 7th Framework Programme (FP7) with 3.7 million Euro funding for three years.

Current problems of photocatalysis

People from many countries of the world extensively use pesticides, which contaminate drinking and irrigation water with toxic organic compounds. In rural areas of Vietnam, herbicides and dioxins, resistant to degradation, made their way into the water cycle during the Vietnam War. The results can be devastating. People who drink this contaminated water are at a higher risk of developing cancer, and pregnant women may put their newborn at risk for birth defects, in worst case scenarios.

“Photocatalysis is potentially one of the cheapest and most efficient methods for purifying water from pollutants,” Radim Beránek says.

Sunlight and oxygen establish oxidizing conditions, under which toxins are easily degraded into non-harmful substances like water and carbon dioxide. Up until now, the process, however, faces two problems: degradation rates are too low and assembly of the needed photoreactors is too expensive.

The aim: cheeper and more efficient catalysts

Within the project “4G-PHOTOCAT,” the researchers aim to develop cost-efficient photocatalysts with a considerably improved degradation rate. They fabricate innovative composite materials consisting of semiconductors and nanostructured metal oxides. In order to achieve the optimal architecture for the product, they employ advanced chemical deposition techniques with a high degree of control over composition and morphology.

“Our ultimate goal is to implement the newly developed photocatalysts into a liquid paint,” Radim Beránek says. “Photoreactors painted with that liquid can be used, for example, for water decontamination in remote rural areas of Vietnam.”

Collaborators

“4G-PHOTOCAT “allies the expertise of seven academic and three industrial partners from five European countries and two Southeast Asian countries. At the RUB, Beránek collaborates with Professor Dr. Roland A. Fischer (Inorganic Chemistry II), Professor Dr. Martin Muhler, and Dr. Jennifer Strunk (Industrial Chemistry). The international collaborators include scientists from the University College London, J. Heyrovský Institute of Physical Chemistry in Prague, Jagiellonian University Krakow, University of Helsinki, Universiti Teknologi Malaysia, and Hanoi University of Agriculture. Furthermore, industrial partners from Finland (Picosun), Czech Republic (Advanced Materials), and Vietnam (Q&A) have joined the team.

ultra-low power processorAt this week’s International Solid State Circuits Conference (ISSCC 2013), imec and Holst Centre presented an ultra-low power processor that operates reliably at near-threshold voltages. The processor delivers clock speeds up to 1MHz at voltages down to 0.4 V. In tests based on a Fast Fourier Transform use case, it consumed only 79 µW – a fraction of the power consumption at standard voltages.

“Energy-efficient data processing will be vital for a wide range of emerging applications from Body Area Networks to building automation and equipment monitoring. Reducing active power consumption and standby leakage are thus increasingly important considerations for digital design,” said Harmke de Groot, Program Director at Holst Centre/imec. “Yet much of the industry’s research is still aimed at improving performance rather than increasing battery lifetime by higher energy efficiency.  At Holst Centre, we focus on low power and low voltage to enable battery-powered and energy scavenging smart devices.”

The new energy-efficient processor platform is customized for biomedical applications such as ECG and EEG monitoring. This was realized by creating an interface architecture around a general-purpose processor core to enable ultra-low voltage operation and automatic scaling of performance to improve energy efficiency, plus in-situ monitoring to guarantee reliability and high yield.

One of the key developments was the ability to reduce the operating voltage while delivering enough performance to meet application needs, and maintaining that performance over a range of operating voltages and temperatures. That was achieved by forward biasing the transistors within the processor, allowing it to operate at voltages just above the threshold for the CMOS process used.  The operating voltage can be adjusted between the processor’s nominal voltage of 1.1 V and a minimum voltage of 0.4 V depending on the current performance requirements.

Natural variations in manufacturing processes can lead to voltage fluctuations when a processor is being used. At near-threshold voltages, these fluctuations can be enough to stop the processer working. To avoid this and ensure reliability, the team connected “canary flip-flops” to the most timing-critical parts of the processor. These are designed to fail before the processor’s circuits do and can be monitored – allowing the operating voltage to be scaled up before noise affects the processor. In addition, automatic bias control eliminates the usual voltage drop across the power switches that control the processor, further enhancing energy efficiency and reliability under near-threshold conditions.

To reduce energy consumption even further, the interface can control the state of individual components on the chip separately, for example turning off the processor core or reducing the voltage in the memory when these components are not required. The software interface can also dynamically switch the processor between various performance modes, optimizing the number of active functional units in the core to suit the algorithm being performed. Unused functional units are switched off to reduce power consumption.

ultra-low power multi-standard 2.3/2.4GHz short range radioImec and Holst Centre presented at ISSCC an ultra-low power multi-standard 2.3/2.4GHz short range radio. The 1.9nJ/b radio is compliant with three wireless standards: Bluetooth Low Energy, ZigBee and Medical Body Area Networks. A proprietary 2Mbps mode is also implemented to support data-streaming applications like hearing aids. The radio is three to five times more power-efficient than current Bluetooth Low Energy solutions.

“From health care to smart buildings, adding sensors to our environment will support and enhance our day-to-day life.  Applications are numerous and restricted mainly by our imagination… and by the power consumption of the mostly battery-operated sensor devices,” said Harmke De Groot, program director of Ultra Low Power Circuits at Holst Centre/imec.  “The radio often consumes between 50-85% of the overall power consumption of a sensor system. And for autonomous devices, with only a small battery and thus limited battery energy, the power consumption of commercially available short-range radios is rather high (>15mW DC power).”

Imec and Holst Centre developed an ultra-low power multi-standard radio with sensitivity. The radio significantly reduces the power consumption of the overall sensor system compared to off-the-shelf radios. As a result, the autonomy of the device is increased, or more functionality can be added to the sensor device, increasing its quality, functionality and/or performance. Or, the battery size can be reduced, resulting in a smaller device, which in case of wearable systems, adds to the comfort of the user.

The 2.4GHz radio is implemented in 90nm CMOS technology. Using a highly energy efficient architecture and optimizing the most power hungry building blocks, resulted in a 2.4GHz radio with world-class energy efficiency while supporting the most common standards for mobile sensor networks. Imec and Holst Centre’s energy-efficient radio architecture has a suitable LO frequency plan and several efficiency-enhancement techniques for the critical RF circuits. As a result, the radio achieves a DC power of only 3.8mW at 1.2V supply for the receiver and 4.6mW for the transmitter. This is 3 to 5 times more power-efficient than the current state-of-the-art Bluetooth Low Energy solutions. The measured RX noise figure is 6dB, resulting in an excellent sensitivity in each standard (-100/-98/-96.5dBm for Zigbee/BLE/MBAN). With a measured IIP3 of -19dBm at the maximum front-end gain, the RX can accommodate the BLE intermodulation test level to -40dBm (spec. >-50dBm).

These results were presented at the 2013 IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco.

Tim Turner, the Reliability Center Business Development Manager at the College of Nanoscale Science and Engineering (CNSE), Albany, NY, blogs about the potential of resistive memory and the reliability challenges the must be overcome.

Resistive Memory, RRAM or Memristors is a hot topic right now.  RRAM has the potential for single digit nano parameters (speed as fast as 1 ns, area per bit as small as 5 square nm) and is non-volatile.

The technology is based on the formation of a small conductive filament inside an insulator.  The filament is formed the first time using a high voltage.  After that, set or reset transformation (conductive to non-conductive or visa versa) is accomplished by moving one or a few atoms an atomic scale distance.  This can be done with a low voltage (less than a volt).    This small movement gives a repeatable set or reset that can withstand many cycles.

Conduction in the filament appears to be due to oxygen vacancies existing in a percolation path through the insulator.  A small electric field in the reverse direction causes the migration of these oxygen vacancies in a mechanism similar to electromigration of Al or Cu atoms in a metal line.  Momentum exchange between electrons and the vacancies appears to be the driving force.  The vacancies do not have to move far to open the small filament.  An oxygen vacancy moves an atomic scale distance and the tiny filament opens, allowing an insulator to exist between points in the filament.  Forcing a forward voltage can move the oxygen vacancy back into the area where the filament is conductive.  This small movement can give a 100X change in the conduction through the dielectric.  This is the state change that can be interpreted as the digital signal stored on the memory cell.

The material set used for RRAM is CMOS compatible.  RRAM cells have been made out of Cu/HfOx [1], Al/AlOx/Pt, TiN/AlOx/Pt or even Al/AlOx/CNT (Carbon Nano Tubes)[2].  Most of the work reported to date has been on arrays where the cell is similar to a DRAM, using one transistor and one capacitor [3].  The RRAM cell starts with a capacitor, then forms the filament in the capacitor dielectric.  The advantage  this technology has is the smaller size of the capacitor.  There is no need for deep trenches in the silicon or for thick vertical stacks.   The technology is also non-volatile, so there is no need to refresh the charge every few milliseconds.

In polycrystalline materials, the filaments appear to form along grain boundaries between crystals [7].  For amorphous material there are no grain boundaries, but the material is reported to be able to withstand more cycles before failure [1].

RRAM might also be produced with a simple single resistor cross-point array (no transistor per cell required).  Figure 1 shows an array where the each cell is addressed by a row and a column.  The conduction in the row/column pair determines if the cell is set or reset (conductive or insulating).  This arrangement has the distinct advantage of allowing the memory array to be printed on top of a logic circuit.  Active circuits are required only for the address circuitry, allowing a large memory array to be added with little additional silicon area. 

Figure 1: Cross-point RRAM cell

That is the good news.  Now for the bad news.  What are the technology challenges that prevent you from enjoying this technology today?

The first issue is one of measurement noise.  With atomic spacing causing the difference between a set and a reset state, there is some uncertainty in the answer.  Sometimes, a bit will not program.  Nimal Ramaswamy of Micron [3] reported that random bits in a large array failed any given write operation.  There was an average number of failures for each write of a large array, but different bits failed each time.  Every bit apparently has the same probability of failure. 

Random Telegraph Noise (RTN) is another issue.  The state of the bit will most likely be read by forcing voltage and measuring current.  RTN is caused by trap states in the gate dielectric of a transistor that might address the bit.  These traps randomly fill or emit, changing the conduction of the channel.  The noise generated by this increases as the transistors are scaled.  Originally, this was thought to be just the larger impact of a single trap on a smaller area gate [4], but Realov and Shepard [5] showed that shorter L transistors show a greater noise than longer transistors with the same total area (below 40nm).  Thus, this is a problem that will increase as the technology is scaled.  There is also a chance that RTN will be generated by the movement of oxygen vacancies in the filament itself.

Degraeve et. Al. [6] reported a highly voltage sensitive disturb in the reset state.  Their RRAM cell could withstand 100 thousand disturb pulses (100ns) at -0.5 volts, but at -0.6 volts the cell could only withstand a little over 100 pulses.  They also showed that the sensitivity to disturb could be reduced significantly by balancing and optimizing the set and reset pulses.

Figure 2: Disturb in Reset State

Optimization of the Set and reset pulses also has a strong impact on the set/reset cycling endurance of the cell.  Degraeve was able to show up to 10 G set/reset pulses after optimization. 

Wu et. Al [2] showed the impact of scaling on a cross-point array.  According to their model, scaling the technology from 22nm to 5 nm resulted in an increase for the parasitic word and bit line resistance from under 10 ohms to almost 100,000 ohms as the lines width and thickness are reduced.  Adding to the significance of this is the variation in resistance between the closest cell in the array and the furthest call in the array.  This variation could be over 4 orders of magnitude while the difference between the set and reset resistance is only 2 orders of magnitude.  This issue could restrict the size of sub arrays, compromising the potential area savings using this technology.

As the metal lines are scaled to obtain higher memory densities, the filament that generates the conduction in the cell does not scale.  That means the set and reset pulse currents remain about the same as the array is scaled.  This results in an electromigration issue in the scaled metal lines.

Figure 3: Oxygen Vacancy Filament Determines Set or Reset State of RRAM Memory Cell

RRAM is certainly an appealing technology with its ability to scale the cell to tiny dimensions, good speed, CMOS compatible material set and the possibility of mounting the technology above a logic array.  Unfortunately, the devil is in the details and the list of advantages is balanced by a list of problems that must be overcome before this technology can carve out a space as a memory solution.

References:
1] Jihan Capulong, Benjamin Briggs, Seann Bishop, Michael Hovish, Richard Matyi, Nathaniel Cady, College of Nanoscale Science and Engineering, “Effect of Crystallinity on Endurance and Switching Behavior of HfOx based Resistive Memory Devices”, Proceedings of the International Integrated Reliability Workshop 2012
2] Yi Wu, Jiale Liang, Shimeng Yu, Ximeng Guan and H. S. Philip Wong, Stanford University, “Resistive Switching Random Access Memory – Materials, Device, Interconnects and Scaling Considerations”, Proceedings of the International Integrated Reliability Workshop, 2012
3] Nirmal Ramaswamy, Micron, “Challenges in Engineering RRAM Technology for High Density Applications”, Proceedings of the International Integrated Reliability Workshop, 2012
4] K.K. Hong, P.K Ko, Chemming Hu and Yiu Cheng,  Random Telegraph Noise of Deep Sub-Micrometer MOSFETs, 1990 IEEE 1741-3106/90/0200-0090 http://www.eecs.berkeley.edu/~hu/PUBLICATIONS/Hu_papers/Hu_JNL/HuC_JNL_167.pdf
5] Simeon Realov and Kenneth L. Shepard, “Random telegraph noise in 45nm CMOS: Analysis Using an on-Chip Test and Measurement System,  IEDM10-624, 978-1-4244-7419-6/10/$26.00 ©2010 IEEE, http://bioee.ee.columbia.edu/downloads/2010/S28P02.PDF
6] R. Degraeve, A. Fantini, S. Clima, B. Guvoreanu, L. Goux, Y. Y. Chen, D. J. Wouters, Ph. Rousset, G. S. Kar, G. Pourtois, S. Cosemans, J. A. kittl, G. Groeseneken, M. Jurczak, l. Altimime, IMEC, “Reliability of Low Current Filamentary HfO2 RRAM Discussed in the Framework of the Hourglass set/reset Model”, Proceedings of the Integrated Reliability Workshop, 2012.
7] Gennadi Bersuker, SEMATECH, “Origin of Conductive Filaments and Resistive Switching in HfO2 based RRAMS” Proceedings of the International Integrated Reliablity Workshop, 2012, 1.2-1

BioMEM for cardiac resynchronization therapyImec demonstrated a low-power (20µW), intra-cardiac signal processing chip for the detection of ventricular fibrillation at this week’s International Solid State Circuits Conference (ISSCC 2013) in San Francisco with Olympus. An important step toward next-generation cardiac resynchronization therapy solutions, the new chip delivers innovative signal processing functionalities and consumes only 20µW when all channels are active, enabling the miniaturization of implantable devices.

Robust and accurate heart rate (HR) monitoring of the right and left ventricles and right atrium is essential for implantable devices for cardiac resynchronization therapy. And accurate motion sensor and thoracic impedance measurements to analyze intra-thoracic fluid are critical for improving clinical research and analysis of the intra-cardiac rhythm. Moreover, extreme low-power consumption is required to further reduce the size of cardiac implants and improve the patient’s quality of life.

Imec’s low-power integrated circuit features three power-efficient, intra-cardiac signal readout channels (or in short: ECG channels). Each of the three ECG channels is equipped with a precision ECG signal readout circuit with very low-power consumption and an analog signal processor to extract the features of the ECG signal for detection of ventricular fibrillation. The feature extractor achieves only 2ms latency to facilitate responsive cardiac resynchronization therapy.

Additionally, the chip includes unique features that improve the functionality of cardiac resynchronization therapy devices. First, the low-power accelerometer readout channel enables rate adaptive pacing. Secondly, to handle intra-thoracic fluid analysis, the chip includes a 16-level digital sinusoidal current generator and provides 82db wide dynamic range bio-impedance measurement, in the range of 0.1Ω－4.4kΩ with 35mΩ resolution, and achieves best-in-class accuracy (>97%).

Click here to view slideshow of more highlights from ISSCC 2013.

Imec, in collaboration with Panasonic Corporation, has presented at the IEEE International Solid-State Circuits Conference (ISSCC 2013) a 60GHz radio transceiver chipset with low power consumption that delivers high data rates over short distances. Imec drastically boosted the link budget of the system by introducing beamforming into the radio architecture. This multi-Gbit 60GHz chipset paves the way toward small size, low-power, low-cost, high-data rate solutions for battery-operated consumer devices, such as smart phones and tablets.

“Exchange of gigabytes of data between mobile devices requires a viable 60GHz technology that balances cost, size and power consumption,” said Liesbet Van der Perre, program director of green radios at imec. “Imec’s prototype transceiver chipset enables multi-gigabit wireless connectivity for ‘true mobile’ devices thanks to its very low power consumption. More demanding applications such as high-definition video streaming and gaming with low latency, proximity computing and wireless docking can also be built on our technology.” 

The prototype chipset consists of a receiver and a transmitter chip, and these are based on a direct conversion architecture combined with an on-chip phased-array architecture. This makes it suited for implementation in 40nm low-power digital CMOS technology targeting low-cost, mass market production. The receiver and transmitter chips are implemented for 4 antenna paths, but they are easily extendible to more antenna paths thanks to the beamforming at analog baseband, rather than at RF. The chip size is kept low through the use of lumped components even at 60GHz, and very compact mm-wave CMOS layout techniques. The transmitter chip consumes 584mW and the receiver chip 400mW at 1.1V power supply. The chipset is integrated with a 4 antenna array in a compact module and demonstrated in a wireless link. With QPSK modulation, a data rate of 2.31Gbps is obtained, and with QAM16 modulation, a data rate of 4.62Gbps is achieved. No bit errors were found when transmitting packets of 32,768 symbols over a distance of 3.6m with QPSK modulation and 0.7m with QAM16 modulation. Thanks to the beamforming a 3dB scan angle range around 120º is achieved with 11dBi antenna gain.

The imec receiver and transmitter chips are designed for the IEEE802.11ad  standard. The receiver and transmitter chipset has been tested with a IEEE 802.11ad PHY/MAC baseband chip developed by Panasonic, demonstrating the complete system for IEEE 802.11 applications. The beamforming functionality is also verified in these system tests.