Category Archives: Semiconductors

SEMI announced that Joung Cho (JC) Kim, chairman, Edwards Korea Limited, is the recipient of the 14th annual SEMI Sales and Marketing Excellence Award, inspired by the late Bob Graham. This award for outstanding contributions in semiconductor equipment and materials marketing was presented today to JC Kim during SEMICON Korea 2013 in Seoul.

Over his 30+ year career, JC Kim has had a major impact on the industry. In 1985, semiconductor manufacturers used rotary pumps. JC Kim introduced Fomblin oil from Italy to the Korean market, which reduced pump process problems and resulted in substantial process improvement, higher productivity and cost savings. He was also involved in marketing a new vacuum pump design, called the "Dry pump" and he demonstrated the pump’s value by providing overseas references and reliability data.  He persuaded manufacturers to try the dry pump on their production lines, contributing to higher productivity and a more stable process. In addition, he improved service efficiency for Dry pumps by establishing 24-hour/day on-site field service offices in or near customer fabs, preventing large production losses from process interruption. JC Kim continues to advocate for understanding the importance of vacuum p umps in semiconductor manufacturing and their considerable impact on semiconductor process development.

JC Kim is a champion for the development of the vacuum industry. He held the position of vice chairman of the Korea Vacuum Society (KVS) and chairman of the Korean Vacuum Research Association (KOVRA) from 2000 to 2004, serving as a bridge between industry and the academic world so that university vacuum R&D could be used in the semiconductor industry.  Also, in 2007, JC Kim became vice chairman of the Korea Semiconductor Industry Association (KSIA) which consists of 235 semiconductor industry related companies in Korea. In this role, he encouraged semiconductor business growth through vacuum industry development by active exchange of technology and information among KSIA members. He continues to build university-industry collaboration to connect technology and human resources from universities to semiconductor companies.
 
In July 2002, JC Kim was appointed to the SEMI Board of Directors, becoming vice chairman in 2008 and chairman in 2009.  He has provided the board with valuable guidance and direction — for tradeshows, executive events, emerging markets, EHS services and Standards — during some of the most complex times in SEMI’s history.

"JC’s unique sales and marketing leadership in vacuums and his contributions to various industry associations have made an indelible mark on the global semiconductor industry," said Denny McGuirk, president and CEO of SEMI. "Today, SEMI and its membership officially recognize JC for his contributions to the success of our industry."

The SEMI Sales and Marketing Excellence Award was inspired by the late Bob Graham, the distinguished semiconductor industry leader who was part of the founding team of Intel and who helped establish industry-leading companies Applied Materials and Novellus Systems.  The Award was established to honor individuals for the creation and/or implementation of marketing programs that enhance customer satisfaction and further the growth of the semiconductor equipment and materials industry.

Eligible candidates are nominated by their industry peers and are selected by an award committee. Previous recipients include: Art Zafiropoulo (2000), Jim Healy and Barry Rapozo (2001), Jerry Hutcheson and Ed Segal (2002), Steve "Shigeru" Nakayama (2003), Edward Braun (2004), Archie Hwang (2005), Aubrey C. (Bill) Tobey (2006), Richard Dyck (2007), Richard Hong (2008), Peter Hanley (2009), Martin Van Den Brink (2010), Franz Janker (2011) and Dan Hutcheson (2012).

Chip inventory held by semiconductor suppliers reached alarmingly high levels in the third quarter of 2012 amid weak market conditions, according to an IHS iSuppli Semiconductor Inventory Insider Market Brief from information and analytics provider IHS (NYSE: IHS).

Overall semiconductor revenue declined by 0.7 percent sequentially during the fourth quarter last year. The poor results came after inventory reached exceedingly high levels by the end of the third quarter in 2012, amounting to 49.3 percent of total semiconductor revenue—more elevated than at any point since the first quarter of 2006.

Chip stockpiles among semiconductor suppliers had actually gone down during the final two quarters of 2011, showing a promising drawdown, as depicted in the figure attached. But then inventories steadily ticked up again after that, reaching 47.5 percent of total revenue in the second quarter before hitting the current peak in the third—the latest time for which full figures are available.

The inventory level being measured refers to chip stockpiles specifically in the hands of semiconductor suppliers, not to inventory throughout the electronics supply chain. Chip level at the supplier level is then compared against combined revenue from a sample of 75 semiconductor supplier companies excluding memory, which is tracked separately because of that market’s typical late results. A low inventory-to-revenue ratio is preferable, given that higher levels indicate not only unsold stockpiles but also unrealized revenue tied up with the stagnant inventory.

 “The uncomfortably high level of inventory among semiconductor manufacturers of nearly all stripes is a result of key demand drivers failing to materialize,” said Sharon Stiefel, analyst for semiconductor market intelligence at IHS. “Demand for semiconductor devices has typically come from new products that consumers feel compelled to purchase. But going into the holiday season last year, no such new products marshaled enough impetus to overcome consumer fears about lingering economic woes. Two months prior to Christmas, consumer purchases of electronics had grown by only 0.7 percent, the worst performance since 2008.”

Also contributing to depressed conditions was the poor performance of the industry’s data processing segment, traditionally the largest user of semiconductors. In fact, mobile PCs were projected to decline in 2012 when final figures are tallied, toppled from dominance by media tablets. Ultrabooks and other ultrathin PCs, meanwhile, did not produce the demand for semiconductors originally expected as the year progressed.

Despite the collective rise in inventory stockpiles, some semiconductor segments performed better than others. For instance, with feature-rich smartphones and tablets taking the place of traditional PCs among consumers and eroding PC market share, the devices were anticipated to provide the strongest demand in the final quarter of 2012. As a result, semiconductor revenue for the wireless segment was expected to climb almost 4 percent. Semiconductor sectors benefiting from the tremendous growth of handsets and tablets included logic, analog and NAND flash memory, with those semiconductor channels refilling following strong shipments even into the beginning of this year.

The first quarter of 2013 likely will see growth in the industrial and automotive electronics segments. Other semiconductor markets, for their part, will overcome the seasonal decline normally expected at this time of year and then start to rebound around the second and third quarters. Such assumptions, however, rest on the even larger factor of the global economy, currently a volatile variable itself with no set outcome. If global economic forecasts perform according to positive expectations, semiconductor revenue could grow by 4 percent in the second quarter and by a very solid 9 percent in the third. However, if demand evaporates, semiconductor suppliers will find themselves in a deplorable oversupply situation, which would then lead to inventory write-downs throughout the year.

Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, San Jose, Calif., blogs about dealing with increased random variations and layout-dependent effects.

How to manage process variations or DFY (or variation-aware design) has been a hot topic in the past several years, ever since the industry started moving to 45nm and smaller geometries. Engineers are concerned about yield problems, especially 28nm. Moving forward, it will continue to be a major worry.

Process variations are becoming one of the biggest challenges that both process development engineers and circuit designers must deal with in advanced process nodes. The increased random variations and layout-dependent effects inevitably and significantly impact the yield of a chip. Therefore, these process effects must be physically understood and accurately modeled up front in SPICE models that can be used later by the circuit designers during various circuit design stages, including simulation and verification.

To reduce risks for low-yield wafer manufacturing and design re-spins or even re-design, accurate yield prediction and realistic design optimization between performance and yield are urgently needed. The keys here are the accurate statistical models and useful design tools with high prediction accuracy and superior simulation performance.

Traditionally, engineers selectively run process, voltage and temperature (PVT) corner analysis and Monte Carlo analysis. Unfortunately, the process information given by the foundry models are sometimes either too conservative or too optimistic, and the foundry models may be used inappropriately or incorrectly on an application-specific basis. Compounding the problem are selective corner models and Monte Carlo analysis approaches often employed by circuit designers may give limited information, giving them low confidence on the yield prediction and design optimization. As a result, the overall design efforts may lead to loose conclusions. What’s worse, the information and value given to circuit designers are, in fact, limited.

In another scenario, the variation model in the SPICE model library of a process design kit (PDK) is the only channel where designers can understand the complexity of variations and its relation to design. Its accuracy, completeness and quality can impact the final simulation and analysis results and confidence level. Having good model knowledge and properly using and applying it in the design flow offers increasing value, not to mention that improper usage of models may lead to deviated results.

Since the lack of integration can lead to a loose integration to simulators, one remedy would be to enhance the link between design and manufacturing by integrating modeling, simulation and statistical analysis software tools. A set of elements for yield analysis can make the yield analysis more reliable and realistic.

There are three key components for handling process variations for circuit designs, i.e., accurate SPICE models considering process variations, a fast and reliable statistical simulation engine and hardware-validated sampling technologies. Performance can be improved and the license cost can be reduced immediately with an integrated SPICE engine instead of using an external engine. Having none of those components can lead to a loss in accuracy and degradation in simulation performance as well.

The software solution should focus on how efficiently yield analysis can be done in two different areas: regular 3-sigma Monte Carlo runs for analog circuit designs and special High Sigma runs. For example, 5~6 sigma for memory designs.

An integrated flow could enable designers to better use foundry corner models or help them re-generate corners, representative of the applications to improve efficiency and confidence levels for PVT analysis. Another analysis tool needed for yield prediction is Monte Carlo, which requires good statistical models. An integrated SPICE engine and hardware validated sampling technologies help designers here as well because they make the DFY more practical and faster, yet accurate because SPICE accuracy is preserved and sampling technologies are validated.

Managing process variations is something the semiconductor industry needs to pay more attention to, while the design community and foundries need to work more collaboratively to expand on the foundry-fabless model. The answer could come by more closely linking design and manufacturing with a rich software suite of SPICE modeling, circuit simulation and statistical analysis tools.

Newport Corporation introduced long-lived deep ultraviolet (UV) excimer laser mirrors with projected lifetimes greater than 30 billion pulses when used in the proper photocontamination controlled environment.  The advanced new mirrors feature all dielectric high reflector coatings to minimize absorption and maximize reflected energy at 193nm.

The high energy laser mirrors are designed with excimer-grade UV-fused silica substrates which are polished to better than λ/10 flatness to preserve wavefront quality and maintain excellent stability.  All coating and testing are done in a special photocontamination controlled deep UV cleanroom that has been qualified to 193nm standards.

According to Optics product manager at Newport, Anna Sansan Wang,“Extensive analysis, research and testing have been done to better understand the conditions at these short wavelengths. Our coating scientists have investigated various conditions including thermal issues, densification of materials, and wavelength shift in order to properly optimize the performance of the mirrors at 193 nm under long term use.”

Newport’s new laser mirrors offer exceptionally high laser damage resistance.  Special Pet-G and metal foil packaging ensure that parts are delivered clean and protected from any environmental photocontamination.  The long-lived deep UV Excimer laser mirrors will be featured at SPIE Photonics West in Newport’s booth #1301 at Moscone Center, San Francisco, CA, February 5 – 7, 2013. 

 

China’s rapid transition from a low-cost manufacturing hub to an innovation hotspot with growing foreign ambitions represents both a threat and an opportunity for companies and investors around the globe, according to Lux Research.

Chinese firms in such sectors as energy storage, advanced lighting, emerging electronics and red-biotechnology industries are more likely to pursue both overseas growth and introduction of foreign capabilities into China.

During 2009-2011, Chinese companies’ foreign merger and acquisition (M&A) deals grew 75% to $28.1 billion. Simultaneously, M&A deals by foreign companies in China increased 16 times – from $400 million to $6.9 billion, suggesting new momentum in opportunities inside the world’s fastest growing country. All indications are that this is only the beginning.

“From Chinese companies’ perspectives, acquiring advanced technologies globally and entering foreign markets are major goals as they seek to shed the tag of a low-cost manufacturing hub,” said Zhuo Zhang, Lux Research Associate and the lead author of the report titled, “From the Horse’s Mouth: How Chinese Companies Value Foreign Partners and Opportunities.”

“Entities around the globe need to navigate the new reality of an increasingly crowded market in China where global leaders must learn to operate while developing strategies to face the imminent threat in their own backyard,” he added.

Lux Research analysts studied China’s complex emerging technology ecosystem, surveying and analyzing 380 entities. Among their findings:

  •  Sectors to watch. Energy storage, advanced lighting, emerging electronics and red-biotechnology all sat in the upper-right quadrant of the grid on Lux’s China Innovation Partnership Grid. This indicates that companies in these sectors have both strong foreign growth inclination and strong willingness to introduce appropriate foreign partners into China. In comparison, water treatment and construction material industries are closed to foreign growth and introduction.
  • IP drives openness. Chinese companies with a strong IP portfolio are more open to foreign partnerships. Contrary to conventional wisdom regarding China, it is the companies that value IP, rather than just those looking to infringe upon the IP of others, who are most open. Specifically, 51% of companies with strong IP are open to partnering with foreign entities in China, compared to only 31% of those with weak IP.
  • Government relationships enable growth introverts. Companies with poor government relationships are driven to look overseas, with 54% of these companies having meaningful foreign growth activities compared with only 44% percent of the companies with good government relationships. In many of China’s emerging technology industries, government relationships represent domestic sales channels, reducing the urgency for foreign growth.

The report, titled “From the Horse’s Mouth: How Chinese Companies Value Foreign Partners and Opportunities,” is part of the Lux Research China Innovation Intelligence service.

Cadence Design Systems, Inc. (NASDAQ: CDNS) announced the availability of Virtuoso® Advanced Node, a new set of custom/analog capabilities designed for the advanced technology nodes of 20nm and below.Built on the industry-leading Cadence® Virtuoso custom/analog technology, Virtuoso Advanced Node features capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter® RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of mixed-signal chips that power today’s consumer electronics devices.

The new and advanced Virtuoso technologies address layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. They integrate with the Cadence Integrated Physical Verification System (IPVS) to conduct on-the-fly checks that reduce layout iterations.

LDE analysis using incremental layout — Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end.  It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle.  LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics — are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.

When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time.  By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way.

Double patterning and color-aware layout—Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring” challenges to designers. Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.

New routing layers—Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors. Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.

Developed specifically for the most cutting-edge designs, the Virtuoso Advanced Node options do not replace the industry-leading 6.x version of the Virtuoso technology, which targets mature and mainstream geometries, and which will continue to be enhanced by Cadence.

“Moving to smaller geometries always creates new obstacles, but the move to 20 nanometers has been especially challenging for our customers, many of whom are reporting that layout is taking two to five times as long as for 28nm on the same circuit,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “Virtuoso Advanced Node enables design teams to optimize their designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.”

ProPlus Design Solutions, Inc., announced it is shipping a new wafer-level, 1/f noise measurement system. Increasingly, circuit designers are interested in 1/f noise data at higher frequencies. They are concerned also about variation effects at leading-edge process nodes, increasing the need for statistical noise models. Generating statistical noise models requires massive amounts of data collection that is particularly challenging at low frequencies.

The 9812D low-frequency 1/f noise measurement system is designed to measure low-frequency noise characteristics of on-wafer or packaged semiconductor devices, including MOSFETs, bipolar junction transistors (BJTs), junction field effect transistors (JFETs), diodes and diffusion resistors. In addition to frequency domain measurement, 9812D can measure device noise in the time domain and can be used to perform on-wafer auto measurement for flicker (1/f) noise and Radom Telegraph Signal (RTS) analyses.

9812D improves upon 9812B, the company’s 1/f measurement system used for more than a decade by foundries, integrated device manufacturers (IDMs) and research organizations. The system, which has a frequency range that exceeds 10 Megahertz (MHz), has a built-in dynamic signal analyzer (DSA) with multi-threaded processing for improved performance and reduced cost.

“Noise is a key figure of merit for semiconductor process quality and also an intrinsic characteristic impacting circuit performance,” said Dr. Zhihong Liu, executive chairman of ProPlus Design Solutions. “To meet the new challenges at 28 nanometer and beyond, we worked with leading foundries on significant improvements of the 1/f system.”

Wafer fabrication facilities use 7*24 1/f noise measurement data to assess process quality. A three-to-10X throughput improvement of the 9812D system means faster data collection and early detection of process issues.

When a 300mm wafer is vacuum mounted onto the chuck of a scanner, it needs to be flat to within about 16nm over a typical exposure field, for wafers intended for 28nm node devices.1 A particle as small as three microns in diameter, attached to the back side of the wafer—the dark side, if you will—can cause yield-limiting defects on the front side of the wafer during patterning of a critical layer. The impact of back side particles on front side defectivity becomes even more challenging as design rules decrease.

Studies have shown that a relatively incompressible particle three microns in diameter or an equivalent cluster of smaller particles, trapped between the chuck and the back surface of the wafer, can transmit a localized height change on the order of 50nm to the front side of the wafer.2 With the scanner’s depth-of-focus reduced to 50nm for the 28nm node, the same back side particle or cluster can move the top wafer surface outside the sweet spot for patterning. The CD of the features may broaden locally; the features may be misshapen. The result is often called a defocus defect or a hotspot (Figure 1). These defects are frequently yield-limiting because they will result in electrical shorts or opens from the defective feature to its neighbors.

A particle on the back side of the wafer may remain attached to the wafer, affecting the yield of only that wafer, or it may be transferred to the scanner chuck, where it will create similar defects on the next wafer or wafers that pass through the scanner.

At larger design nodes, back side defects were not much of an issue. The scanner’s depth of focus was sufficient to accommodate a few microns of localized change in the height of the top surface of the wafer. At larger design nodes, then, inspection of the back side of the wafer was performed only after the lithography track and only if defects were found on successive wafers, indicating that the offending particle remained on the scanner chuck, poised to continue to create yield issues for future wafers. In this case corrective measures were undertaken on the track to remove any suspected contamination. The track was re-qualified by sending another set of wafers through it and looking for defectivity at the front side locus of the suspected back side particle. This reactive approach was economically feasible for most devices throughout volume production of 32nm devices.

At the 28nm node, however, lithography process window requirements are such that controlling back side particles requires a more proactive approach. Advanced fabs now tend to inspect the wafer back side before the wafer enters the scanner, heading off any potential yield loss. Scanner manufacturers are also encouraging extensive inspection of the back side of wafers before they enter the track. As we see what lithography techniques unfold for the 16nm, 10nm nodes and beyond, it’s entirely possible that 100% wafer sampling will become the best-known method.

As with inspection of the front side of the wafer, sensitivity to defects of interest (DOI) and the ability to discriminate between DOI and nuisance events are important. Even though particles need to be two to three microns in diameter before they have an impact on front side defectivity, the inspection system ought to be able to detect sub-micron defects, since small defects can agglomerate to form clusters of critical size. Sub-micron sensitivity is beneficial for identifying process tool issues based on the spatial signature of the defects—while high-resolution back side review enables imaging of localized defects, so that appropriate corrective actions can be taken to protect yield. Sub-micron sensitivity also serves to extend the tool’s applicability for nodes beyond 28nm.

For further information on back side inspection equipment or methodologies, please consult the second author.

Rebecca Howland, Ph.D., is a senior director in the corporate group, and Marc Filzen is a product marketing manager in the SWIFT division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

Notes:

1.       Assuming 193nm exposure wavelength, NA = 1.35 and K2 = 0.5, then depth of field = 50nm. Normally 30% of the DOF is budgeted for wafer flatness.

2.       Internal studies at KLA-Tencor.

January 24, 2012 – Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique. The method also can be applied to detect voids in TSVs during processing, they claim.

The initial focus of their work was to develop metrology for detecting voids after temporary wafer bonding of 3D wafers, which remains challenging because development of interface particles and voids can impact subsequent wafer thinning processes, as well as overall wafer thinning and tool performance.

To address this, PVA Tepla and imec developed an automated foup-to-foup, wafer-level process based on 200MHz SAM using Tepla

January 24, 2012 – Protecting intellectual property, protecting federal funding for R&D, and enabling friendlier export, tax, and other policies are the top priorities for the Semiconductor Industry Association (SIA) in 2013.

Top items on the SIA’s 2013 policy roadmap, presented this week by president/CEO Brian Toohey:

  1. Facilitate open markets and protect intellectual property. As the semiconductor industry expands globally, promoting free and open international trade and safeguarding IP rights are paramount. Of particularly importance to the semiconductor industry: the updated Information Technology Agreement (ITA), Trans-Pacific Partnership (TPP) negotiations, and the World Semiconductor Council (WSC).

  2. Support federal funding for university research. The fiscal cliff was averted only for a few months; looming concerns remain on federal spending for R&D investments in jeopardy. Key semiconductor research programs are in the spotlight the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), the Defense Advanced Research Projects Agency (DARPA), and the Department of Energy (DOE) Office of Science.

  3. Streamline export control regulations. The semiconductor industry is one of the nation’s top exporters, and the SIA supports "appropriate controls" on technologies tied to national security — but wants relief on areas that "stifle" US competitiveness abroad, such as "troublesome rad-hard requirements" and satellite decontrol legislation, while pushing for reform of IC controls..

  4. Reform the corporate tax system. America’s tax structure blocks possible pathways to innovation to enhance America’s competitiveness, and the SIA wants any tax legislation to "reflect the semiconductor industry’s core tax priorities: adoption of a lower rate, a territorial system, and incentives for innovation." Extension of the R&D tax credit through 2013 is a start, but needs to be expanded and made permanent.

  5. Improve security and authentication of semiconductor products. Proliferation of counterfeit semiconductors is a growing economic and national security concern. The SIA pledges to work with industry and government to advance legislation that stops counterfeit semiconductors from entering the US, promote stricter government procurement guidelines, enhance international efforts to stop counterfeiting at its source, and explore various research opportunities and technology solutions.

  6. Support sustainability practices and innovation development. "Certain environmental regulations, when applied broadly to all industries, could inappropriately undermine semiconductor design and manufacturing processes in the US," the SIA says. The semiconductor industry will keep working on environmental "stewardship" with an eye to keeping regulation of chemicals and other materials from limiting operations, product design, or future innovation.

"Through hard work and ingenuity, the semiconductor industry creates American jobs, drives U.S. economic growth and leads the global market. By enacting SIA’s Policy Roadmap in 2013, policymakers can further strengthen the industry and help unlock its full potential," Toohey writes.