Category Archives: Semiconductors

January 15, 2013 – The semiconductor industry is undergoing massive transformation as the rise in mobile computing, changes to the fabless-foundry model, uncertainties in technical innovation, and global macroeconomic trends become the dominant forces in 2013 and beyond, according to industry leaders speaking at the SEMI Industry Strategy Symposium (ISS), opening this week in Half Moon Bay, CA.

Ajit Manocha, CEO of GlobalFoundries, during his keynote presentation discussed the dynamic technology and economic needs of mobile computing that is driving new approaches to the chip design-to-production cycle. Calling it "Foundry 2.0," he sees outsourced semiconductor manufacturing moving toward a more IDM-like model, creating new collaboration models and techniques to close the gap between process teams at foundries and design teams at the fabless companies. With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the uncertainties to lithography-based scaling, product development paths with virtual teams will evolve and adapt rapidly in the coming months and years.

With new fabs now costing upwards of $8 billion and leading-edge manufacturing investments expected to exceed $40 billion this year alone, global economic trends and forces — increasingly influenced by uncertain consumer spending in both developed and emerging markets — have never been more important to the semiconductor ecosystem. Dr. John Williams, president and CEO of the Federal Reserve Bank of San Francisco, said "Many businesses are locked into a paralyzing state of anxiety."

Williams used the ISS conference to lessen uncertainty and anxiety in the capital markets, pledging to keep interest rates near zero until the unemployment rate drops to 6.5%, as long as inflation expectations do not climb above 2.5%.

Bruce Kasman, chief economist and managing director of global research at JP Morgan, shared a positive economic outlook, especially in the second half of the year, that is "bumpy, better and less risky." He sees Asia leading the economic rebound, as China demand accelerates with the change in leadership and improved access to credit. University of Texas Austin Churchill scholar, Matthew Gertken, however, discussed the simmering "Asian cold war" developing as territorial disputes with China generate an emerging "containment policy" by many of China’s neighbors.

How these macroeconomic dynamics are impacting the semiconductor industry was discussed by speakers who saw both perils and opportunities. Andy Oberst, senior VP, strategy and corporate development at Qualcomm, looked at what mobile phones would likely look like in 2020, but also pointed out how disruptive changes — not incremental changes — have always driven the mobile phone market.

Satya Kumar, vice president at Credit Suisse, discussed how original equipment makers like phone and computer manufacturers have always benefitted from the declining cost of transistors and pondered, "Could stopping Moore’s Law be a good thing?"

As the world’s largest semiconductor company, Intel’s view is different. Michael Bell, vice president and general manager, mobile and communications group at Intel, brought the audience up to date on the company’s mobile strategy, offering confidence that Intel’s portfolio of RF baseband technologies, leading-edge scaling performance, and supply chain excellence will ultimately deliver significant success.

Conference speakers on Day 2 and Day 3 of ISS will discuss how these and other mega-trends are specifically impact the R&D, product development, manufacturing, investment, and supply-chain challenges impacting various sectors of IC and microelectronics industry.

The SEMI Industry Strategy Symposium (ISS) examines global economic, technology, market, business and geo-political developments influencing the semiconductor processing industry along with their implications for your strategic business decisions. For more than 35 years, ISS has been the bellwether semiconductor conference for senior executives to acquire the latest trend data, technology highlights and industry perspective to support business decisions, customer strategies and the pursuit of greater profitability.

January 11, 2012 – The annual Consumer Electronics Show in Las Vegas has become a mecca for all things electronic and digital, from useful to cool to just plain bizarre. Among the technologies at the confluence of cool and useful were two things that aim to rethink the PC model. (And for the cool/bizarre side of the CES spectrum, behold eatART’s rideable robot Mondo Spider.)

This year’s CES emphasized "designs that defied or pushed the limits of convention," with two clear examples, points out DisplaySearch’s Richard Shim: size-defying "phablets," and even more size-defying "table PCs."

The phablet — a combination of phone and tablet — got its start with Samsung’s Galaxy Note, which offered an expanded 5-in. OLED screen; the Galaxy Note II was even bigger at 5.5-in. At this year’s CES, the phablet took another screen-size step up thanks to China’s Huawei, which unveiled its Ascend Mate ,which has a 6.1-in. 1280 × 720 screen. (Huawei also touted its Ascend D2 with a 5-in., 1920 × 1080 display.) The Ascend D2 will be available in China later this month, followed by the Ascend Mate in February.

The "table PC," meanwhile, is essentially a supersized tablet, with the screensize of a large computer monitor. Sony’s Vaio Tap 20 (20-in. display) is now joined by Lenovo’s IdeaCentre Horizon with a 27-in. resistive touch-based display, and the company has a prototype 39-in. version planned for later this summer. Each of these "table PCs" can stand upright like an all-in-one desktop PC, but also laid down flat, Shim notes.

"Both the phablet and the table PC categories represent the extreme end of a form factor trend that we expect to see throughout 2013," Shim explains. "The traditional lines that have been used to define, categorize, and track devices are expected to only become more difficult to maintain," and suppliers will increasingly tinker with formfactors to find what resonates with consumers. (In his own CES research note, Barclays analyst CJ Muse acknowledged the interest shown in phablets, and likely reverberations they should cause among suppliers, along with "large screen touch, Next Gen TVs, and the Internet of everything.") Shim doesn’t expect these design tinkerings will greatly impact shipment trends in the near-term (DisplaySearch still sees notebook PC shipments dipping 5% Y/Y in 2013), but "we anticipate that brands can score image points and credibility with consumers for willing to be bold with design. That has translated to good fortune for Apple so it should not be underestimated."

(photos via DisplaySearch; credit photo #1 to Lori Grunin/CNet)

January 10, 2012 – Reaffirming its earlier assertions about the health of fabless & foundry chipmakers vs. the rest of the industry, IC Insights says fabless IC suppliers saw sales rise 6% in 2012, compared with a -4% decline by IDMs (those with their own IC fabs), and the overall market’s -2% decline for the year.

Since 1999, the firm tracks, fabless company IC sales have outpaced IDMs (or the decline has been less severe) in every year except 2010. That year was an outlier largely because of strength in DRAM and NAND flash memory, areas in which fabless companies don’t have a presence, the firm points out.

Fabless vs. IDM company sales, 1999-2012. (Source: IC Insights)

Since 1999, fabless IC sales started out as roughly 7% of IDM sales, but have steadily risen and now make up about 27% of total IC sales. And fabless IC market CAGR from 1999-2012 was 16% vs. the overall industry’s 5% CAGR. More comparison metrics: fabless IC sales are at levels 7× what they were in 1999, vs. 50% for IDM IC sales, and IDM IC sales are now only 10% higher than 2000 and actually lower than they were in 2007.

By 2017, fabless IC companies will command a full third of the total IC market, IC Insights predicts, and this could be easily attained especially if larger companies (e.g. IDT, LSI Logic, Agere, and AMD) become entirely fabless. "Over the long-term, IC Insights believes that fabless IC suppliers, and the IC foundries that serve them, will continue to become a stronger force in the total IC industry," the firm notes.

These statistics are part of IC Insights’ annual McClean Report analysis of the entire IC industry, from technologies to applications. The firm is holding half-day seminars this month to release and discuss the findings. Contact the firm for more information about the report and the seminars.

by Todd Traylor, Vice President of Global Trading for Smith & Associates.

Consumer devices and cutting-edge tech make Consumer Electronics Show (CES) exciting; this year’s show stealers are the components that power it all. If you have any doubt look to center stage and Qualcomm’s opening keynote.

To those embedded (pun intended) in the semiconductor and electronics industry, Qualcomm is not a surprise keynote presenter. But CES is about the consumer, and their keynote highlighted what’s really at the core of consumer electronics’ (CE) success: powerful components. Components, after all, enable the innovative feature capabilities, mobility, power efficiency, and the integration of hardware and software, all which make CE devices "smart."   

Get smarter

The innovation behind the expanding class of smart devices (from phones to cars and all that is between) is the component breakthroughs from manufacturers – the processors, microelectromechanical sensors (MEMS) and sensor hubs, and the chips that are the brains, communication, and power of the devices.

Qualcomm unveiled their Snapdragon 800 and 600 series, processors designed for a range of mobile devices. The 800 series, manufactured using 28nm architecture, enables the integration of the new Krait 400, quad-core CPU with each core running at 2.3GHz, the new Adreno 330 GPU, 4G LTE, and 802.11ac WiFi, all with reduced power consumption, due in part to the smaller and more integrated chipset; the Snapdragon 600 series has similar architecture but slower speeds. The user experiences fast processing power for the next generation of smart devices, but at the level of traditional PCs, with the added benefits of always-on, always-connected plus the enhanced graphics and fast data communication speeds.

Nvidia’s latest Tegra 4 and Samsung’s Exynos 5 are among the direct competitors to the Snapdragon series . Nvidia’s Tegra 4 boasts 72 GPU cores in addition to the powerful quad-core Cortex A15 CPU, code-named "Wayne," for processing plus an additional low-power Cortex A15 running background tasks. The Tegra 4 CPU combination improves power use, essential in today’s devices, while integrating the CPU and GPU to improve performance and signal processing, important for graphics in digital cameras.

Tough competition improves CE field

At CES we see the envelope pushed to  be the  fastest, lightest, smallest, most efficient, best integrated, or first-mover. Intel scooped CES with the announcement of the new, quad-core, 22nm, Atom processor, Bay Trail, due this year to compete with ARM processors in mobile. Beyond speed, Bay Trail is only 8mm thick and enables all-day battery-life, essential to both mobile and Ultrabooks. AMD is showcasing its new Temash chip, based on the Jaguar CPU core, designed for tablets to support long battery life, HD graphics, powerful processing for full-applications for business productivity, as opposed to the reduced capabilities found mostly today. AMD’s Kabini chips are also on display, designed for the new line of low-powered laptops with A8 and A10 quad-core chips. These advances will support Ultrabook adoption in 2013 as prices decreases and features increase.

Expanded connectivity is also CES theme this year, such as Broadcom’s "Connected Life," enhancing consumer experiences in the home, car, and across wired and wireless devices. Pushing connectivity moves CE toward a unified experience as users move through environments. It also paves the growth path for NFC opportunities, content sharing, and allows for the latest in seamless "whole-home connectivity" through Broadcom’s  4th-generation, Gigabit DOCSIS system-on-chip (SoC) series, and dedicated SoC solutions for the fastest TV, internet, and mobile connected solutions.

Another set of breakthroughs comes from Atmel XSense™ flexible touch sensor, winner of CES’ Innovations Award in the Embedded Technologies. Flexible touchscreens are certain to be a desired feature in next-gen mobile devices, and Atmel’s expertise in sensor hubs and innovative material designs will ensure success.

Opportunities for everyone

One final note, it is not just the high-end CE devices that are targeted at CES. There is more attention this year to low-cost solutions designed for the emerging markets, which are set for double-digit growth for these devices, provided low-price points are met.

Author biography:

Todd Traylor began his career with Smith in 1997 in OEM sales, and was promoted to Trading Manager in 1999. In 2001, he transferred to The Netherlands to serve as General Manager of Smith’s Amsterdam office, and was promoted to Managing Director of Europe for Smith in 2002. Todd was named CPU Commodity Manager upon returning to Houston in 2003, and in 2012 was promoted to Vice President of Global Trading. Todd is a 1991 graduate of Texas A&M University, where he earned his bachelor’s degree in Business Management.

January 9, 2012 – SEMI’s HB-LED Standards Committee has approved its first standard, specifying sapphire wafers used in making high-brightness light-emitting diode (HB-LED) devices.

Sapphire wafers are used in producing HB-LED devices for multiple applications: LCD backlights, signage and solid-state lighting. Development of industry standards, in collaboration with the global LED manufacturing supply chain, will help eliminate costs and better enable equipment and process innovation.

Five categories of single-crystal, single-side polished c-axis sapphire wafers are covered by the new HB1 standard:

  • Flatted 100mm diameter, 650μm thick,

  • Flatted 150mm diameter, 1,000μm thick,

  • Flatted 150mm diameter, 1,300μm thick,

  • Notched 150mm diameter, 1,000μm thick, and

  • Notched 150mm diameter, 1,300μm thick

SEMI’s HB-LED Standards Committee was formed in late 2010, comprised of companies involved in HB-LED devices, sapphire wafers, MOCVD wafer processing, and equipment and materials suppliers. Among its various individual efforts:

— The HB-LED Wafer Task Force already is seeking refinements to the HB1 standard, including specs for patterned sapphire substrates, double-sided polished wafers, impurities and defects (wafer and bulk), laser marking and identification, and bow and warp measurements. This group also is beginning a second round of experiments with wafer marking to characterize mark survivability, width, and depth; a first round conducted this year "showed promising results" on 100mm and 150mm wafers with front and back-surface marks (i.e., data matrix and OCR) were subjected to various surface modifications (e.g., slicing, grinding, polishing, GaN Ep). For 2013, the group plans to explore core and wafer defect inspection on ultrasonic technology, and conduct surveys on patterned sapphire substrates and double-side polishing.

— The HB-LED Equipment Automation Task Force plans to reballot a SEMI Draft Document on cassettes for 150mm sapphire substrates, seeking revisions to allow interoperability with existing equipment, taking into account cassette pocket size and spacing. This also will help standardization of load ports and transport systems.

— Meanwhile, a Software Working Group continues to develop a spec for an automation communication interface between process, automation, and metrology equipment. Another new standard, submitted and approved last October at the SEMI NA Standards Fall 2012 meetings, builds on that automation spec to address materials management and job management.

SEMI also plans to begin experiments and test methods based on a survey deployed last summer about defect vs. inspection techniques, aiming to identify sapphire wafer defects and inspection techniques catering to HB-LED manufacturing.

The wafer, automation, and impurities/defects task forces will be meeting at the Strategies in Light conference Feb. 12-14 in Santa Clara, CA. The NA HB-LEB committee and task forces will meet at the NA Standards Spring 2013 meetings April 1-4 in San Jose.

By Rebecca Howland, Ph.D., and Tom Pierson, KLA-Tencor.

Is it time for high-brightness LED manufacturing to get serious about process control?  If so, what lessons can be learned from traditional, silicon-based integrated circuit manufacturing?

The answer to the first question can be approached in a straight-forward manner: by weighing the benefits of process control against the costs of the necessary equipment and labor.  Contributing to the benefits of process control would be better yield and reliability, shorter manufacturing cycle time, and faster time to market for new products. If together these translate into better profitability once the costs of process control are taken into account, then increased focus on process control makes sense.

Let’s consider defectivity in the LED substrate and epi layer as a starting point for discussion. Most advanced LED devices are built on sapphire (Al2O3) substrates. Onto the polished upper surface of the sapphire substrate an epitaxial (“epi”) layer of gallium nitride (GaN) is grown using metal-organic chemical vapor deposition (MOCVD).

Epitaxy is a technique that involves growing a thin crystalline film of one material on top of another crystalline material, such that the crystal lattices match—at least approximately. If the epitaxial film has a different lattice constant from that of the underlying material, the mismatch will result in stress in the thin film. GaN and sapphire have a huge lattice mismatch (13.8%), and as a result, the GaN “epi layer” is a highly stressed film. Epitaxial film stress can increase electron/hole mobility, which can lead to higher performance in the device. On the other hand, a film under stress tends to have a large number of defects.

Common defects found after deposition of the epi layer include micro-pits, micro-cracks, hexagonal bumps, crescents, circles, showerhead droplets and localized surface roughness. Pits often appear during the MOCVD process, correlated with the temperature gradients that result as the wafer bows from center to edge. Large pits can short the p-n junction, causing device failure. Submicron pits are even more insidious, allowing the device to pass electrical test initially but resulting in a reliability issue after device burn-in. Reliability issues, which tend to show up in the field, are more costly than yield issues, which are typically captured during in-house testing. Micro-cracks from film stress represent another type of defect that can lead to a costly field failure.

Typically, high-end LED manufacturers inspect the substrates post-epi, taking note of any defects greater than about 0.5mm in size. A virtual die grid is superimposed onto the wafer, and any virtual die containing significant defects will be blocked out. These die are not expected to yield if they contain pits, and are at high risk for reliability issues if they contain cracks. In many cases nearly all edge die are scrapped. Especially with high-end LEDs intended for automotive or solid-state lighting applications, defects cannot be tolerated: reliability for these devices must be very high.

Not all defects found at the post-epi inspection originate in the MOCVD process, however. Sometimes the fault lies with the sapphire substrate. If an LED manufacturer wants to improve yield or reliability, it’s important to know the source of the problem.

The sapphire substrate itself may contain a host of defect types, including crystalline pits that originate in the sapphire boule and are exposed during slicing and polishing; scratches created during the surface polish; residues from polishing slurries or cleaning processes; and particles, which may or may not be removable by cleaning. When these defects are present on the substrate, they may be decorated or augmented during GaN epitaxy, resulting in defects in the epi layer that ultimately affect device yield or reliability (see figure).

Patterned Sapphire Substrates (PSS), specialized substrates designed to increase light extraction and efficiency in high-brightness LED devices, feature a periodic array of bumps, patterned before epi using standard lithography and etch processes. While the PSS approach may reduce dislocation defects, missing bumps or bridges between bumps can translate into hexes and crescent defects after the GaN layer is deposited. These defects generally are yield-killers.

In order to increase yield and reliability, LED manufacturers need to carefully specify the maximum defectivity of the substrate by type and size—assuming the substrates can be manufactured to those specifications without making their selling price so high that it negates the benefit of increased yield. LED manufacturers may also benefit from routine incoming quality control (IQC) defect measurements to ensure substrates meet the specifications—by defect type and size.

Substrate defectivity should be particularly thoroughly scrutinized during substrate size transitions, such as the current transition from four-inch to six-inch LED substrates. Historically, even in the silicon world, larger substrates are plagued initially by increased crystalline defects, as substrate manufacturers work out the mechanical, thermal and other process challenges associated with the larger, heavier boule.

A further consideration for effective defect control during LED substrate and epi-layer manufacturing is defect classification. Merely knowing the number of defects is not as helpful for fixing the issue as knowing whether the defect is a pit or particle. (Scratches, cracks and residues are more easily identified by their spatial signature on the substrate.) Leading-edge defect inspection systems such as KLA-Tencor’s Candela products are designed to include multiple angles of incidence (normal, oblique) and multiple detection channels (specular, “topography,” phase) to help automatically bin the defects into types. For further information on the inspection systems themselves, please consult the second author.

Rebecca Howland, Ph.D., is a senior director in the corporate group, and Tom Pierson is a senior product marketing manager in the Candela division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

By Gandharv Bhatara, product marketing manager for OPC technologies, Mentor Graphics.

For nearly three decades, semiconductor density scaling has been supported by optical lithography. The ability of the exposure tools to provide shorter exposure wavelengths or higher numerical apertures have allowed optical lithography to play such an important role over such an extended time frame. However, due to technical and cost limitations, conventional optical lithography has reached a plateau with a numerical aperture of 1.35 and an exposure wavelength of 193nm.  Although intended for the 32nm technology node, it has been pushed into use for the 20nm technology node.

The continued use of 193nm optical lithography at the 20nm technology node brings with it significant lithography challenges – one of the primary challenges being the ability to provide sufficient process window to pattern the extremely tight pitches. Several innovations in computational lithography have been developed in order to squeeze every possible process margin out of the lithography/patterning process.  In this blog, I will talk about two specific advances that are currently in deployment at 20nm.

The first such innovation is in the area of double patterning. As the pitch shrinks to below 80nm, double patterning becomes a necessary processing/patterning technique. One of the impacts of double patterning on the manufacturing flow is that foundries now have to perform optical proximity correction (OPC) on two separate masks after the layout has been decomposed. There are two approaches available to do this. In the first approach, each mask undergoes a separate OPC process, independent of each other. In the second approach—developed, deployed, and recommended by Mentor Graphics—the two masks are corrected simultaneously. This approach allows critical information, like edge placement error and critical dimension, to be dynamically shared across the two masks. This concurrent double patterning approach (Figure 1) ensures the best quality optimal correction, good stitching across the two masks, and significantly reduces the risk of intra-mask bridging.

 

 

Caption: Concurrent double patterning OPC corrects the two decomposed masks at the same time, sharing information between them.

The second innovation is in the area of technical advances in OPC techniques. As the process margin gets tighter, traditional or conventional OPC may not be sufficient to process difficult-to-print layouts. These layouts are design rule compliant but require a more sophisticated approach in order to make them manufacturable. We developed two approaches to deal with this situation. The first is to perform a localized in-situ optimization. This is a computationally expensive approach, which precludes it from being a full chip technique that improves printing by enhancing the process margin for extremely difficult-to-print patterns (Figure 2).

Caption: Hotspot improvement with in-situ optimization. The simulated contour lines show an improvement in line width after optimization.

In-situ optimization is integrated within the OPC framework so it’s seamless from an integration standpoint.  The second approach is a technique for post-OPC localized printability enhancement. OPC at 20nm typically uses conventional OPC and simple SRAFs. We developed an inverse lithography technique in which the OPC and the SRAFs have greater degrees of freedom and can employ non-intuitive but manufacturable shapes. This is also a computationally expensive approach, but it allows for significant process window improvement for certain critical patterns and allows for the maximum possible lithography entitlement. In this approach, you first run OPC and identify lithography hotspots (difficult-to-print patterns), then apply the localized printability enhancement techniques on the hotspots. All the necessary tooling and the infrastructure to enable this approach for all major foundries are available.

Both these advances in computational lithography are critical enablers for the 20nm technology node. In my next blog, I will talk about extension of these techniques to the 14nm technology node.

Author biography

Gandharv Bhatara is the product marketing manager for OPC technologies at Mentor Graphics.

 

 

January 8, 2012 – Cymer has hired Klaus Schuegraf, former exec in Applied Materials’ semiconductor technology group, to lead its EUV engineering and development programs.

"Klaus’ deep industry experience and proven product development track record add significantly to the strength of our EUV management team, especially important as we transition from 3100 pilot sources to the first 3300 production sources," stated Cymer founder/CEO Bob Akins.

Schuegraf previously was corporate VP and CTO for AMAT’s Silicon Systems Group, responsible for overseeing the company’s semiconductor products technology roadmap. Prior to that was VP of technology at SanDisk where he similarly defined and executed their roadmaps for nonvolatile NAND flash and 3D memory. His prior work in product and technology development includes positions at Cypress Semiconductor, Conexant, and Micron Technology.

January 7, 2012 – As the annual Consumer Electronics Show and hordes of techie enthusiasts descends over Las Vegas this week, one display technology — 4K × 2K — is expected to grab most of the attention, says NPD DisplaySearch.

4K LCD TV shipments will exceed OLED TV shipments through 2015, the firm says, due to both delays by OLED TV makers and increased promotion of 4K LCD TVs. Many Chinese brands are currently launching their own products domestically. OLED TVs should start hitting the market in 2013, but with low volumes and high prices. Note that 4K technology can be applied to OLED TVs as well, and eventually will be introduced for some premium TV segments, the firm points out.

"The global TV market—and North America in particular—are experiencing either slow or negative growth in 2012, and brands are eager to demonstrate new technologies that might create a spike in demand," stated Paul Gagnon, Director for Global TV Research at NPD DisplaySearch. Gagnon added, “OLED TV was prominently featured during the previous two CES shows as the next-generation TV display technology, but the lack of market launch so far has caused several set makers to start emphasizing 4K×2K resolution TVs for premium market segments."

Forecast for OLED TV and 4K LCD TV. (Source: NPD DisplaySearch)

Overall TV demand is expected to fall in 2012, as consumers worldwide grapple with tough economic conditions and TV prices fall at only marginal rates. DisplaySearch estimates LCD TV shipments in 2012 were 205 million, slightly lower than in 2011, while plasma TV shipments sunk 24% to 13 million. The firm sees 2013 initially taking shape as a flat market due to persistent economic uncertainty, but ultimately smoothing into gradual growth as conditions improve and as price declines in the TV market accelerate.


TV shipment growth by technology. (Source: NPD DisplaySearch)

By Dr. Ravi Kanjolia, Chief Technology Officer, SAFC Hitech

We are in an age where chemistry is center stage in the race to advance Moore’s Law and More Than Moore. The continued drive towards smaller feature sizes, increased performance, and lower power consumption requires highly complex architectures using new materials and advanced process technologies. This is primarily true for processes in which physical vapor deposition (PVD) is being displaced by atomic layer deposition (ALD) and chemical vapor deposition (CVD). For example, materials are being developed to form high purity functional layers for applications in logic, memory, and interconnect areas, all within given thermal budgets. In many cases, the CVD process for extremely high-performance applications requires alternative chemistries to fabricate metal and dielectric layers at lower temperatures. All of this begins with the development of base chemistries for high-purity precursors and the R&D support to progress these materials to commercial maturity.  Additionally, the importance of further optimizing cost-of-ownership (COO) and efficiencies of high-purity materials used in semiconductor and LED manufacturing cannot be understated. In low-margin, high-volume product lines you compete on operational efficiency, not necessarily on innovation. This will require close collaboration between materials manufacturers, equipment suppliers, OEMS, IDMs, and foundries; the complexity of the products requires the entire value chain to work together.

While there is some industry-wide sentiment about lackluster CAPEX in 2013, we are positive about growth in the materials market segment. There has already been a noticeable increase in utilization rates across semiconductor manufacturing lines, as ever smaller feature sizes required for advanced CMOS and beyond CMOS technologies fall more on the shoulders of materials providers than equipment manufacturers. Therefore, demand for advanced chemistries is expected to increase even beyond that observed in 2012, and we expect much of that growth to come from Korea and the Chinese-speaking world.

Looking ahead to 2013 and beyond, the future is bright for the semiconductor materials market.  Roadmaps for advanced chemistries that will address the needs of next generation semiconductor manufacturing should reflect that.