Category Archives: Top Story Right

CEA-Leti and EV Group (EVG) have launched a three-year common lab to optimize temporary- and permanent-bonding technologies related to 3D TSV integration and all direct bonding heterostructures. 

The lab, which continues more than 10 years of collaboration between the two organizations, is focusing on hardware, software and process development.

“Temporary and permanent bonding equipment and process solutions are key product offerings for EVG,” said Markus Wimplinger, EVG’s corporate technology development and IP director. “This project leverages CEA-Leti’s global leadership in wafer-bonding research and EVG’s unparalleled expertise in developing wafer bonding equipment and process technology.”

“Like all common labs that Leti creates with its partners, this project is designed to produce specific, practical solutions that address current and future market requirements,” said Laurent Malier, CEA-Leti CEO. “This collaboration is targeting results that will make 3D TSV integration more efficient and cost effective and open new areas of wafer bonding using covalent bonding at room temperature.”

“Bringing these approaches to high-volume manufacturing with reliable wafer bonding requires innovative fabrication processes,” said Fabrice Geiger, head of Leti’s Silicon Technology division. “The new equipment and process technology developed within the common lab will allow exciting possibilities, especially for heterogeneous materials stacks, that require very low-temperature wafer bonding.”

Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Leti is focused on creating value and innovation through technology transfer to its industrial partners. It specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. NEMS and MEMS are at the core of its activities. CEA-Leti operates 8,000-m² of clean room space on 200mm and 300mm wafer platforms. It employs 1,700 scientists and engineers including 320 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 2,200 patent families.

EV Group (EVG) is a supplier of equipment and process solutions for the manufacture of semiconductors, microelectromechanical systems (MEMS), compound semiconductors, power devices, and nanotechnology devices.  Key products include wafer bonding, thin-wafer processing, lithography/nanoimprint lithography (NIL) and metrology equipment, as well as photoresist coaters, cleaners and inspection systems.  Founded in 1980, EV Group services and supports an elaborate network of global customers and partners all over the world.

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Boston University filed a lawsuit against Apple Inc. and several other big tech companies over an alleged patent infringement, a thin film semiconductor technology that they claim was developed by one of their professors.

The suit, which was filed on Tuesday in a federal district court in Boston, the school claims that Apple violated its patent on “highly insulating monocrystalline gallium nitride thin films.” BU says this technology is being used in products such as the iPhone, iPad and MacBook Air.

Boston University names Theodore Moustakas, a professor of electrical and computer engineering, as the inventor of the technology, and claims that the patent for the semiconductor film was issued in 1997.

The school is seeking financial compensation that will be determined by a jury, if the case goes to trial. However, the patent on Moustakas’ technology expires in 2015, leaving experts to speculate on what little impact a Boston University victory could have on Apple’s future.

Neither party has commented on the case.

For decades, electronic devices have been getting smaller, and smaller, and smaller. It’s now possible—even routine—to place millions of transistors on a single silicon chip. But transistors based on semiconductors can only get so small.

"At the rate the current technology is progressing, in 10 or 20 years, they won’t be able to get any smaller," said physicist Yoke Khin Yap of Michigan Technological University. "Also, semiconductors have another disadvantage: they waste a lot of energy in the form of heat."

Scientists have experimented with different materials and designs for transistors to address these issues, always using semiconductors like silicon. Back in 2007, Yap wanted to try something different that might open the door to a new age of electronics.

"The idea was to make a transistor using a nanoscale insulator with nanoscale metals on top," he said. "In principle, you could get a piece of plastic and spread a handful of metal powders on top to make the devices, if you do it right. But we were trying to create it in nanoscale, so we chose a nanoscale insulator, boron nitride nanotubes, or BNNTs for the substrate."

Electrons flash across a series of gold quantum dots deposited on a boron nitride nanotubes.

Yap’s team had figured out how to make virtual carpets of BNNTs, which happen to be insulators and thus highly resistant to electrical charge. Using lasers, the team then placed quantum dots (QDs) of gold as small as three nanometers across on the tops of the BNNTs, forming QDs-BNNTs. BNNTs are ideal substrates for these quantum dots due to their small, controllable, and uniform diameters, as well as their insulating nature. BNNTs confine the size of the dots that can be deposited.

In collaboration with scientists at Oak Ridge National Laboratory (ORNL), they fired up electrodes on both ends of the QDs-BNNTs at room temperature, and something interesting happened. Electrons jumped very precisely from gold dot to gold dot, a phenomenon known as quantum tunneling.

"Imagine that the nanotubes are a river, with an electrode on each bank. Now imagine some very tiny stepping stones across the river," said Yap. "The electrons hopped between the gold stepping stones. The stones are so small, you can only get one electron on the stone at a time. Every electron is passing the same way, so the device is always stable."

Yap’s team had made a transistor without a semiconductor. When sufficient voltage was applied, it switched to a conducting state. When the voltage was low or turned off, it reverted to its natural state as an insulator.

Furthermore, there was no "leakage": no electrons from the gold dots escaped into the insulating BNNTs, thus keeping the tunneling channel cool. In contrast, silicon is subject to leakage, which wastes energy in electronic devices and generates a lot of heat.

Other people have made transistors that exploit quantum tunneling, says Michigan Tech physicist John Jaszczak, who has developed the theoretical framework for Yap’s experimental research. However, those tunneling devices have only worked in conditions that would discourage the typical cellphone user.

"They only operate at liquid-helium temperatures," said Jaszczak.

The secret to Yap’s gold-and-nanotube device is its submicroscopic size: one micron long and about 20nm wide.

"The gold islands have to be on the order of nanometers across to control the electrons at room temperature," Jaszczak said. "If they are too big, too many electrons can flow." In this case, smaller is truly better: "Working with nanotubes and quantum dots gets you to the scale you want for electronic devices."

"Theoretically, these tunneling channels can be miniaturized into virtually zero dimension when the distance between electrodes is reduced to a small fraction of a micron," said Yap.

Yap has filed for a full international patent on the technology.

DRAM market grows up

June 19, 2013

It’s said that adversity breeds character—and that certainly seems to be the case for the global market for DRAM (dynamic random access memory). This market has achieved some maturity in the face of daunting challenges, allowing the industry to achieve a balance between supply and demand this year.

After DRAM wafer output peaked in 2008 at 16.4 million 300-millimeter-equivalent wafers, production is expected to decline by 24 percent to 13.0 million this year, according to an IHS DRAM Dynamics Market Brief from information and analytics provider IHS.

The projected cut will be the second straight year of deliberate downsizing following an 8 percent drop-off last year. This year’s output is expected to be slashed by 5 percent compared to 2012, as shown in the figure below.

Curtailing DRAM capacity is a positive move for the industry, resulting in a gradual normalization between supply and demand for DRAM. The industry is now believed to be perhaps slightly undersized relative to demand moving forward because of the intentional slash in output, and DRAM pricing can continue to remain firm if production remains slightly behind demand.

DRAM revenue in the first quarter rose to its highest level in nearly two years, thanks to a jump in commodity prices spurred by demand from the server PC and mobile PC segments. Pricing for the bellwether 4-gigabyte DDR3 module rose to $23 in March, up from $16 in December, an unusually large increase.

“The DRAM industry has struggled with major challenges in recent years, including chronic oversupply and slowing demand from its main market, the PC business,” said Mike Howard, senior principal analyst for DRAM and memory at IHS. “This has led to continued weak pricing, financial losses and market revenue declines. However, the DRAM industry has entered a more mature state, enacting structural changes that will allow it to grow even in challenging market conditions.”

DRAM market enters the post-PC era

In one major change, the DRAM market is adjusting to the fact that demand is diversifying away from PCs alone to servers and mobile devices.

Nearly 65 percent of all DRAM bit shipments went to a desktop or laptop 10 years ago, but that figure is less than 50 percent today and will fall further to south of 40 percent by the end of next year.

Meanwhile, servers and mobile gadgets like smartphones and tablets command an increasing share of DRAM bit shipments.

The overall result is that the travails of one segment—like the embattled PC space—won’t be able to disrupt the entire market, lacking the size and critical mass to do so. The server and mobile segments also help by using more specialized products that require a more involved design-in process, thereby reducing the commodity nature of the DRAM that the segments consume.

DRAM downsizing

In another change that has benefited the hypercompetitive industry, a number of DRAM suppliers in the past few years have either reduced their presence or have altogether exited the market.

The Taiwanese are no longer the powerhouse suppliers they used to be, while notable DRAM makers Qimonda of Germany and Elpida Memory of Japan have gone bankrupt and have been bought out by other players. By the end of this year, only three DRAM manufacturers will remain—Samsung and SK Hynix of South Korea, and U.S.-based Micron Technology. With fewer entities to influence the market, a more conservative approach toward capacity expansion is expected, and more stable growth can follow.

Process deceleration

A final factor helping the global DRAM business is the slower pace of advancement in DRAM manufacturing processes. Each new generation of DRAM manufacturing technology is now taking longer to arrive.

The engineering challenges associated with shrinking DRAM size smaller than 30nm— and eventually below 20nm—are considerable.

The slowing cadence in manufacturing process evolution is resulting in slower bit growth, which is keeping supply in better balance with demand.

The challenge of constant undersupply

While the current state of intermittent undersupply is favorable to the industry, a state of persistent undersupply could backfire and prove harmful. Large, obstinate supply shortfalls will result in broader adoption of competing technologies as devices seek alternatives besides DRAM, and possible regulatory intervention could occur over perceived anticompetitive concerns.

Clearly then, it is in the best interest of the industry to manage supply so that it more closely matches demand—and thereby control its own future. Next year, manufacturers will need to seriously look at options for expanding manufacturing capacity to accommodate demand. But properly managed, DRAM prospects can remain healthy, IHS believes.

At this week’s VLSI 2013 Symposium in Kyoto, Japan, imec highlighted new insights into 3D fin shaped field effect transistors (finFETs) and high mobility channels scaling for the 7nm and 5nm technology node.         

At the VLSI 2013 symposium, imec presented the first strained Germanium devices based on a Si-replacement process, where a Ge/SiGe quantum-well heterostructure is grown by epitaxially replacing a conventional Si-based shallow trench isolation (STI). The technique allows for highly-versatile means of heterogeneous material integration with Si, ultimately leading the way to future heterogeneous finFET/nanowire devices.  The device shows dramatically superior gate reliability (NBTI) over Si channel devices due to a unique energy band structure of the compressively-strained Ge channel.

 “We are facing significant challenges  to scale the MOSFET architecture towards 7nm and 5nm. Besides dimension scaling, enhancing the device performance, in the face of rising parasitics and power, is a major focus of the logic device research at imec,” said Aaron Thean, logic devices program director at imec. “Among the key activities are R&D efforts investigating both high-mobility channel material and new methods of enhancing Si-based finFET.” 

With options to introduce heterostructure into next-generation finFET, quantum-well channels based on a combination of materials that enhance both mobility and electrostatics, can be engineered. At VLSI 2013, imec also presented comprehensive simulation work that investigated material combinations of Si, SiGe, Ge and III-V channels to enhance device electrostatics, providing important process guidance to extend finFET scalability.

Moreover, imec presented novel highly scalable engineering approaches to tune gate workfunction and improve mobility, noise and reliability in Si nMOS finFETs. The impact on the performance of layout-induced stress effects in scaled finFETs and the impact of random telegraph noise (RTN) fluctuation in lowly doped devices was shown.

Imec’s research into next-generation finFETs is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.

In an industry where finer features are driving market needs, current deposition processes are no longer sufficient to address challenges like interconnect dimensions below 16/14nm or high aspect ratio TSVs (>8) without experiencing defects, voids, or low reliability. Beyond process performance, cost remains a critical consideration for manufacturing next-generation devices. Today, Alchimer is announcing a new collaboration with imec to validate its wet deposition technology.

Alchimer is a provider of wet deposition technologies for dual damascene, TSVs, MEMS and solar. The new joint development project with imec will evaluate and implement copper filling solutions for advanced nano-interconnect technologies. The focus of the project will be on Alchimer’s Electrografting products, which have demonstrated void-free filling on 7nm node devices and allow direct Cu fill on barrier with no seed layer required for damascene processes.

As CMOS scaling creates finer features, market requirements for copper damascene include smaller dimensions (≤16/14 nm) with a thin barrier layer, and thin or no Cu seed layer. Filling processes must be defect/void free to meet reliability specifications, and achieve high yields. Conventional physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes are not meeting these requirements. Alchimer’s wet deposition technologies are based on a molecular build-up process that breaks through the limitations of dry deposition processes.

"We believe that as the industry moves to smaller technology nodes, performance and cost will drive technology adoption," said Bruno Morel, CEO of Alchimer. "The performance of eG in advanced damascene applications, including single and dual damascene below 20nm, hasbeen very promising both in terms of performance and cost of ownership. Collaborating with imec gives us access to tremendous resources to validate our technology’s suitability at 300mm and understand what it would take to get ready for 450mm."

The goal of the JDP is to obtain reliability data and electrical performance for eG wet deposition processes in a 300mm manufacturing environment for sub-22nm technologies. As part of the JDP, the companies will assess the plating chemistry and work to identify the optimal process conditions for 300mm wafer-level advanced damascene plating applications.



Fraunhofer Institute for Solar Energy Systems ISE has joined forces with EV Group (EVG) to develop equipment and process technology to enable electrically conductive and optically transparent direct wafer bonds at room temperature.  The new solutions, developed in partnership with Fraunhofer ISE based on EVG’s recently announced ComBond technology, aim to enable highly mismatched material combinations like gallium arsenide (GaAs) on silicon, GaAs on indium phosphide (InP), InP on germanium (Ge) and GaAs on gallium antimonide (GaSb).  Direct wafer bonding provides the ability to combine a variety of materials with optimal properties for integration into multi-junction solar cells, which can lead to new device architectures with unparalleled performance.

"Using direct semiconductor bond technology developed in cooperation with EVG, we expect that the best material choices for multi-junction solar cell devices will become available and allow us to increase the conversion efficiency toward 50 percent," stated Dr. Frank Dimroth, Head of department III-V – Epitaxy and Solar Cells of Fraunhofer ISE.  "We are excited to partner with EVG, a leading supplier of wafer bonding equipment, to develop industrial tools and processes for this application."

Fraunhofer ISE has developed III-V multi-junction solar cells for more than 20 years and has reached record device efficiencies of up to 41 percent with its metamorphic triple-junction solar cell technology on Ge.  Higher efficiencies require the development of four- and five-junction solar cells with new material combinations to span the full absorption range of the sun’s spectrum between 300-2000 nm.  Integration of III-V solar cells on silicon opens another opportunity to reduce manufacturing cost, especially when combined with modern substrate lift-off technologies.  Direct wafer-bonding is expected to play an important role in the development of next-generation III-V solar cell devices with applications in space as well as in terrestrial concentrator photovoltaics (PV).

"We are excited about refining our new process technology together with Fraunhofer ISE, the largest solar energy research institute in Europe," stated Markus Wimplinger, corporate technology development and IP director for EVG.  "Fraunhofer ISE’s broad expertise in the area of PV, specifically in concentrated PV cell manufacturing and photonics, will allow us to characterize bonding interfaces with respect to PV applications on our new ComBond equipment platform."    

EVG’s ComBond technology has been developed in response to market needs for more sophisticated integration processes for combining materials with different lattice constant and coefficient of thermal expansion (CTE).  The process and equipment technology enables the formation of bond interfaces between heterogeneous materials—such as silicon to compound semiconductors, compound semiconductors to compound semiconductors, Ge to silicon and Ge to compound semiconductors—at room temperature, while achieving excellent bonding strength.  The ComBond technology will be commercially available later this year on a new 200-mm modular platform currently in development, called EVG580 ComBond, which will include process modules that are designed to perform surface preparation processes on both semiconductor materials and metals. 

In addition to PV, other potential application areas for processes developed in cooperation between EVG and Fraunhofer ISE include light emitting diodes (LEDs) and silicon photonics.

Shipments in March of large-sized liquid crystal displays (LCD) exceeded total production when measured in terms of area, the result of a deliberate move by panel manufacturers to digest accumulated inventory, according to an LCD Fab and Inventory Management Tracker from information and analytics provider IHS.

Large-sized LCD displays in March reached a total shipment area of 11.3 million square meters, a metric showing the expanse of shipped panels during the period and distributed among the panels’ four major applications for TVs, notebooks, monitors and tablets. In comparison, production area measuring the spread and breadth of manufactured panels equated to 11.0 million square meters—approximately 340,000 square meters less than the total shipment area.

“March represented the first time in four months that shipments outpaced production for large-sized LCD panels,” said Ricky Park, senior manager for large-area displays at IHS. “The last time the same phenomenon took place—when shipment was higher than production—occurred in November 2012, an understandable occurrence as manufacturers raced to pump out more displays in time for the December holiday season and Lunar New Year holiday season in China. In March, panel suppliers applied the same tactic to chip away at creeping inventory, the upshot of shipments falling below production levels from December 2012 to February 2013.”

After March, however, the current dynamic took a different turn. Pending final figures, forecasts show that production would catch up to shipments starting in April as both indices reach 11.0 million square meters, with production then exceeding shipments beginning in May, as shown in the figure below. The new movement starts as the industry ramps up for the higher demand anticipated in the second half of this year.

shipments of large-sized LCD display panels

Calculated efforts pay off

For all the vicissitudes of the market, panel manufacturers need to continually negotiate a delicate balancing act—between making sure there is enough inventory, and preventing the inventory at hand from ballooning and crossing into dangerous oversupply. A potent weapon in their arsenal is to turn the screws on production, intentionally limiting manufacturing capacity in fabs, while continually shipping out panels taken from both current assembly and leftover inventory in their possession. Constant vigilance is required in an industry where oversupply is usually the norm, with panel manufacturers always striving to perfect their game.

Utilization rates are also adjusted to achieve targets. In March, utilization rose to 80 percent from 72 percent in February, but the pace of fabrication remained lower than was originally intended, estimated at 82 percent and consistent with the plan to keep production lower than shipments. Fab utilization rates were expected to remain unchanged in April and then jump to 83 percent in May—again in keeping with plans for production to start growing and overtake shipments.

Even so, panel manufacturers are not expected to exceed 85 percent utilization and risk producing more than the channel can swallow. Inventory has been particularly problematic because of slow demand, but manufacturers are also careful that pricing doesn’t drop further even with anemic demand plaguing the system.

Tablet panels continue to reign

Overall, shipments for large-area LCD displays during the first quarter this year compared to year-ago levels fell for monitors and notebooks, but rose for TVs and tablets. Monitor panel shipments were down 17 percent to 38.7 million units, while notebooks suffered an even larger 20 percent contraction to 43.2 million units. Shipments for TV panels, however, climbed 10 percent to 55.9 million units, while tablets posted an outsized 175 percent increase to 60.3 million units.

The reason for such disparate movements is not hard to guess. Monitors and notebooks have been under a cloud for some time, overshadowed among consumers by more appealing devices like smartphones and tablets. TVs, while a mature commodity in advanced markets like the United States, Europe and other highly industrialized countries, continue to enjoy increasing demand in the vast China market, compensating for any losses that may occur elsewhere.

Tablets are in even more fortunate circumstances. The devices continue to shine with blockbuster sales, their powerful status also demonstrated in unbeatable panel shipment numbers.

Worldwide semiconductor revenues decreased by 2.2 percent year over year to $295 billion in 2012, according to the latest version of the International Data Corporation (IDC) Semiconductor Application Forecaster (SAF). The industry witnessed a slowdown during the second half of 2012 on weak consumer spending across PCs, mobile phones, and digital televisions (DTV), as well as in the industrial and other market segments. The European economic crises and a slowdown in China also had an impact on global demand while the lackluster launch of Windows 8 failed to stimulate PC sales and turn the tide. Meanwhile, competitive suppliers from China continued to pressure average selling prices, dragging down overall revenue growth. IDC expects the semiconductor market to return to growth in 2013 with revenues forecast to increase by 3.5 percent this year.

IDC’s SAF tracks more than 120 semiconductor companies. Most companies saw their revenues decline during the year, including eight of the top ten companies. Only 17 companies, with revenues of a billion or more, grew at a rate above 5 percent last year. Among the 25 largest companies covered in the SAF, only seven had positive top-line growth, including: Qualcomm, Broadcom, NXP, NVIDIA, MediaTek, Apple, and Sharp Electronics. AllWinner, a tablet application processor supplier, was the fastest growing company in 2012.

The largest semiconductor company, Intel, saw its revenues decline to $50.0 billion in 2012, down 3 percent from 2011 largely due to weak PC demand, and minimal traction in tablets and smartphones. Samsung Electronics, the second largest supplier, saw revenues drop 6 percent on weak DTV demand, loss of market share at Apple, and volatile memory prices. Meanwhile, Qualcomm, the largest fabless semiconductor supplier, ranked third last year as revenues grew 34 percent to $13.2 billion due to its leadership in modem technology and success of its Snapdragon application processor in smartphones. Texas instruments, the number four supplier, saw revenues decline by 6 percent due to falling analog, DSP, and MPU revenues and the company’s exit from its wireless business. Rounding out the top 5, Toshiba revenues were off by 13 percent from the previous year due to declining revenues for its analog, ASSP, and memory products. Renesas, Hynix, Broadcom, STMicroelectronics, and Micron filled out the top 10 spots. From this group of companies, only Broadcom saw revenues grow last year. Combined, the top 10 vendors represented 52 percent of worldwide semiconductor revenues, declining 3 percent when compared to 2011. The top 25 semiconductor firms brought in $206 billion, declining 3 percent year over year.

Within the semiconductor device types, performance was mixed. Sensors and actuators grew the fastest at 11 percent year over year, but with 2012 revenues of $7 billion the segment only accounted for 2 percent of industry revenues. ASSPs, the largest category of semiconductors with 32 percent of the overall opportunity, grew by 4 percent for the year on strength in media, graphics, and application processors and RF and mixed-signal ASSPs. Finally, optoelectronics, with 6 percent of total semiconductor revenues, grew 5 percent, mostly from image sensors and LEDs. Revenues for microcomponents declined by 5 percent, driven by lower revenues for MPUs and MCUs. Memory, representing 17 percent of the industry, saw its revenues decline by 10 percent. Finally, Analog, which accounted for 7 percent of revenues last year, declined by 7 percent.

"Beyond the slowdown in end-market demand, the challenge for semiconductor companies is to zero in on their key value propositions. Whether that is in modem or connectivity technologies, sensors, mixed-signal processing, or power management, there are areas of the market showing strong potential. However, competing in crowded segments with little differentiation has contributed to the slowdown in semiconductor revenues," said Michael J. Palma, research manager, Semiconductors at IDC, who led the study and compiled the SAF results. "Large vendors have been going through a process of narrowing their product portfolios to focus resources on profitable lines where their IP and experience provide an edge in the market."

"As we mentioned in our Top 10 Predictions for the 2013 worldwide semiconductor market, investment in R&D and capital in the semiconductor industry remains very high and focused on innovation and addressing the competitive dynamics of a diverse set of industries that semiconductors support. In fact, the overall market landscape and reach of semiconductors continues to expand with the rise of Intelligent Systems and will play a critical role in the overall health and growth of the market," said Mario Morales, program vice president for enabling technologies and semiconductors.

IDC’s Semiconductor and Enabling Technologies research team manages the Worldwide Semiconductor Applications Forecaster database, which is a focal point for IDC’s semiconductor research efforts. This database contains revenue data collected from more than 120 semiconductor companies and forecasts the markets to 2017. Revenue for over twelve semiconductor device areas, four geographic regions, six major vertical markets, and over 90 system devices markets are also part of the SAF coverage.

Leaders of the National Science Foundation (NSF) and the Semiconductor Research Corporation (SRC) today announced 18 new projects funded through a joint initiative to address research challenges in the design of failure-resistant circuits and systems.

failture resistant systems
Failure Resistant Systems

Credit: Subhasish Mitra, Stanford University

The three-year, $6 million collaborative program will support research being conducted by 29 faculty members at 18 U.S. universities. Their work focuses on a variety of aspects of resilient circuit and system design for future computing applications.

Miniaturized electronics form parts of today’s pervasive and increasingly efficient and complex electronic systems. Common examples include communication devices such as cell-phones and personal digital assistants (so-called PDAs), aircraft flight controls, autonomous vehicles, sophisticated weapon systems and tiny medical devices inside or outside of the human body, such as pacemakers and heart monitors.

The accurate functioning of these systems is often a matter of life and death. A small malfunction in a pacemaker could threaten the life of a patient; unexpected failures in flight control circuitry or in an autonomous vehicle may result in a crash.

A host of reasons could cause highly sensitive, automated mechanical devices to deviate from desired behavior or functionalities. These include design imperfections, faults resulting from uncontrolled physical phenomena, manufacturing variations, aging over time and other external disturbances, which even may include tampering or malicious design.

By funding fundamental research in the design of electronic chips, this joint NSF/SRC program on Failure Resistant Systems aims to ensure that at the outset systems are designed in such a way that they are self-corrective or self-healing with minimal or no external intervention during the entire life of its operation.

"As devices become smaller and approach fundamental limits, new design methodologies will be required to account for the wide variability which arises in the fabrication process" said Pramod Khargonekar, head of NSF’s Directorate for Engineering. "This joint program with SRC will allow our academic researchers to address pressing problems faced by our semiconductor industry."

"New fundamental design techniques have the potential to yield major advances in the reliability of electronic systems," said Farnam Jahanian, head of NSF’s Directorate for Computer and Information Science and Engineering. "This program builds on more than a decade of successful partnerships with SRC and provides the academic research community a new opportunity to do ground-breaking, long-term, basic research."

"This partnership of government, industry and academia helps our universities address critical computing challenges," said Steve Hillenius, SRC executive vice president. "This effort in resilient systems will have an effect on multiple industries and boost their competitiveness on a global scale, helping to transform market segments and translate research results into practice. Cooperative programs with NSF also help SRC deliver value to its industrial members’ capabilities, while allowing universities to continue to improve their understanding of the needs of the semiconductor industry."

Funding will support researchers at the following universities: the University of Texas (Austin, Dallas), the University of California (Riverside, Santa Barbara), the University of Southern California, Carnegie Mellon University, the University of Connecticut, the University of Utah, Texas A&M University, the University of Illinois, Stanford University, the University of Michigan, the University of Minnesota, the University of Rochester, Colorado State University, North Carolina State University, the University of Virginia and West Virginia University.