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January 5, 2012 — Haruo Matsuno, president and CEO of Advantest Corporation (TSE:6857, NYSE:ATE) announced the company’s major goals in his New Year’s address to employees and stakeholders.

By fiscal year (FY) 2014, Advantest plans to bring in revenue of 250 billion yen, over 20% operating margin, and have over 50% total market share of semiconductor test systems and test handlers. The $1B acquisition of Verigy in 2011 boosted Advantest’s offering for memory and SoC customers, Matsuno said when the deal was announced. It combined Advantest’s strength in memory semiconductor test systems and mass production lines and Verigy’s strength in non-memory semiconductor test systems and R&D.

"To reach out new targets above and maximize synergies from the Verigy integration, we will spark innovation in all areas," said Matsuno, pointing to a new business model utilizing cloud computing, flexible productions processes, and a global marketing and organizational structure.

Outside of semiconductor test products, Advantest will bring its measurement technologies into scanning electron microscopes (SEM), electron beam (e-beam) lithography, RF measurement devices, MEMS switches, terahertz analysis systems, and healthcare products.

Advantest manufactures electronic measuring instruments, automatic test equipment, and electron beam lithography systems. Learn more at www.advantest.co.jp.

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January 4, 2012 — Recent advances in micro electro mechanical system (MEMS) sensor technology and manufacturing have enabled high-performance, small, low-cost sensors. These attributes encourage integration into handheld devices, including smart phones and tablets. Features such as interrupts and first-in/first-out (FIFO) functions have been integrated into MEMS sensors. The new trend is to integrate multiple sensors and a microcontroller in a tiny single package with embedded algorithms. Some of the smart features built into digital MEMS inertial sensors available on the market today are explained here, with an overview of future trends of sensor integration.

Each MEMS sensor comprises the MEMS sensing structure, an application-specific integrated circuit (ASIC), and device package. The sensing structure is responsible for detecting capacitance or resistance change when the proof mass moves from the center position due to external motion or applied force [1]. The ASIC consists of a charge amplifier to convert the output of the mechanical sensing part into an analog output voltage that can be digitized through an A/D convertor and presented in a digital format. The package, in addition to housing the sensing and processing die, influences device performance, defining stability over temperature and time.

Figure 1 shows the typical internal structure of a MEMS accelerometer and a gyroscope as an example based on the capacitive principle technology.

Figure 1. Structure inside a MEMS accelerometer and gyroscope.

The host processors in smart systems, e.g., smart phones and tablets, have limited resources for sensor data acquisition and processing. Therefore, MEMS sensors need to include more computing power and embedded features to reduce the load of the host processors.

Embedded features

Self-test. Most MEMS sensors have built-in self-test (BIST). The self-test can be used to verify if the sensor is functioning or not after PCB assembly. This functional test (FT) doesn’t require physically tilting or rotating the PCB for inertial sensors.

Figure 2 shows an example self-test procedure for accelerometers and gyroscopes. The sensor data acquisition when self-test is enabled and disabled should be performed at the same arbitrary and stationary position.

Figure 2. Self test procedure for digital accelerometer and gyroscope.

Interrupt feature. Most MEMS sensors have one or two interrupt output pins available for connecting to the GPIO ports of the host processor. The host processor is not required to keep acquiring sensor data to determine the device’s current status; the sensor is running in the background. When the predefined criteria are met, the sensor will generate an interrupt signal on its output pin to notify the host processor. The host processor can then decide if this interrupt needs to be serviced or not.

FIFO feature. FIFO is another power-saving feature that can be implemented in ASICs. The host processor doesn’t need to acquire sensor data all the time. Instead, the sensor can collect data and store it into the FIFO in the background.

When the FIFO interrupts are generated, the host processor can wake up and read all FIFO data samples at once. Then the host processor can process the sensor data to see if further action needs to be taken.

Sensor integration trends

As some interrupt features embedded in an accelerometer cannot distinguish fake motion from the real one, the processor needs to acquire sensor data to determine the nature of the motion. Future smart sensors will have more advanced computing power such as finite state machine (FSM) for reliable interrupt generation.

A low-power microcontroller can be integrated into an inertial module unit to run the sensor fusion algorithms so that the final dynamic accurate pitch/roll/yaw angles can be available to the host processor directly [2].

With respect to the applications such as 3D gaming, indoor pedestrian dead reckoning, etc., 9- or 10-axis sensors are required. In the future, such MEMS sensors and the programmable microcontroller will be combined into a single package as shown in Fig. 3. The wireless link and some other sensors may be integrated in the same package too.

Figure 3. Multiple sensors integrated in one package.

Conclusion

Embedded features and computing power are required for future sensors and embedded features and sensor integration will determine the future applications of MEMS sensors. A dedicated microcontroller is needed to handle the complex algorithms of sensor fusion.

Driven by MEMS technology and market needs, the multiple sensors with lower power consumption and low-cost microcontroller in one package will appear soon.

References:

1. J. Esfandyari et al., Introduction to MEMS gyroscopes, November 2010, http://www.electroiq.com/articles/stm/2010/11/introduction-to-mems-gyroscopes.html.

2. J. Esfandyari et al., “Solutions for MEMS sensor fusion,” Solid State Technology, Volume 54, Issue 7, July 2011, http://www.electroiq.com/articles/sst/print/volume-54/issue-7/features/cover-article/solutions-for-mems-sensor-fusion.html.

Jay Esfandyari received his Master’s Degree and Ph.D. in EE from the University of Technology in Vienna and is MEMS Product Marketing Manager at STMicroelectronics, 750 Canyon Dr., Coppell, TX, 75019 USA; ph.: 972-971-4969; [email protected].

Fabio Pasolini received his Engineering Degree at the University of Pavia, Italy, in 1994 and is the General Manager of the Motion MEMS at STMicroelectronics.

Gang Xu received his Ph. D from Shanghai Jiao Tong University and is Senior Application Engineer at STMicroelectronics.

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January 4, 2012 — Chip inventories held by semiconductor suppliers declined in the third quarter of 2011, putting a halt to the steady expansion of the previous seven quarters, as the industry cut production in order to reduce oversupply, shows IHS iSuppli research.

As calculated by days of inventory (DOI), semiconductor stockpiles in the third quarter stood at 81 days, down 2.5% from 83 days in Q2, according to an IHS iSuppli Inventory Insider report.

 

  Q3 ’09 Q4 ’09 Q1 ’10 Q2 ’10 Q3 ’10 Q4 ’10   Q1 ’11  Q2 ’11 Q3 ’11 Q4 ’11 (est.)
DOI 65 67 69 73 73 77 80 83 81 79.3
Figure. Worldwide days of inventory (DOI) held by semiconductor suppliers. Source: IHS iSuppli Research, January 2012. See Q1’s report. See Q2’s report.

DOI had been increasing since Q3 2009, rising from 65 days. Late 2009 inventories were low due to the production cuts implemented during the recession. DOI crept upwards in efforts to replenish depleted stocks and meet growing demand. Recent weakness identified in the semiconductor market has made inventory levels a concern, notes IHS. Global semiconductor revenue in 2011 rose by 1.9% over 2010, well below the 7% forecast early in the year.

"For the third quarter, semiconductor suppliers began an inventory correction to alleviate an escalating oversupply situation on top of already inflated stockpiles," said Sharon Stiefel, semiconductor analyst at IHS. "With the global economy all but stalled, and in the face of declining orders as well as decreased visibility, many semiconductor manufacturers opted to reduce capacity utilization. And with lead times now declining to normal levels after extended periods of waiting in the past, manufacturers were more confident about trimming bloated inventories this time around without fear of causing too much pain to the supply chain."

Also read: More IC pessimism: Semi inventories "worrisome," says Gartner

Despite the inventory cutback, DOI in the third quarter remained elevated in absolute terms — the highest of the last 10 quarters (back to Q4 2008). The percentage of oversupply during the period rose to 12.1%, exceeding the 11.1% spike in oversupply during Q4 2008. Further inventory trimming is expected in Q4 2011, falling to 79.3 days (2.5% decline).

Inventory levels rose for handset OEMs (holiday season), distributors, and analog companies. Stockpiles fell for fabless semiconductor makers, memory suppliers, foundries (reduced capacity utilization rates), PC OEMs, storage gear companies and electronic manufacturing services providers.

Access the IHS iSuppli report, Inventories in the Semiconductor Supply Chain Finally Begin to Decline in Q3, at http://www.isuppli.com/Semiconductor-Value-Chain/Pages/Inventories-in-the-Semiconductor-Supply-Chain-Finally-Begin-to-Decline-in-Q3.aspx

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January 3, 2011 — The Semiconductor Industry Association (SIA), representing US semiconductor manufacturing and design, reports worldwide sales of semiconductors were $25.1 billion for the month of November 2011, a decrease of 2.4% from the prior month. On a year-to-date basis, worldwide semiconductor sales are 0.8% higher compared to the same period last year. Total semiconductor sales fell 8.0% year over year (Y/Y) compared with the 10-year average of +9.9% Y/Y. Units declined a steady 10 % Y/Y with ASPs higher by +2.2% Y/Y, added Barclays Capital, commenting on the SIA numbers. Barclays finds the November SIA numbers as-expected, given weak Q4 guidance by chip vendors.  
 
All monthly sales numbers represent a three-month moving average. The semiconductor industry closed 2011 with growth and looks towards 2012 for further improvement. See October’s SIA report here.

Table 1. Month-to-Month Sales in $Billion, November 2011. (SIA)
Market Last Month Current Month % Change
Americas 4.67 4.59 -1.8%
Europe 3.08 3.03 -1.8%
Japan 3.88 3.82 -1.7%
Asia Pacific 14.10 13.70 -2.9%
Total 25.74 25.13 -2.4%

—–

Table 2. Year-to-Year Sales in $Billion (SIA)
Market Last Year Current Month % Change
Americas 4.71 4.59 -2.5%
Europe 3.42 3.03 -11.5%
Japan 4.16 3.82 -8.2%
Asia Pacific 13.64 13.70 0.4%
Total 25.93 25.13 -3.1%

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Table 3. Three-Month-Moving Average in $Billion (SIA).
Market Jun/Jul/Aug Sep/Oct/Nov % Change
Americas 4.58 4.59 0.1%
Europe 3.07 3.03 -1.4%
Japan 3.64 3.82 4.7%
Asia Pacific 13.79 13.70 -0.6%
Total 25.08 25.13 0.2%

While the flooding in Thailand disrupted supply chains and impacted semiconductor sales in the near term, OEMs are expected to recover production losses over the course of the next few months, said Brian Toohey, president, SIA. The continuing European financial crisis also had an impact on semiconductor sales, as part of the broader economy.

Barclays Capital notes that an inventory correction will carry over into 2012, experiencing the trough in Q1. Demand will begin to outpace end-market growth beginning in Q2. Barclays slightly lowered its overall semiconductor growth forecast for 2012 to 0-4%.

Logic, discrete, analog, and NOR Flash memory figures declined month over month and year over year, Barclays notes. DSP stood out as a "clear outperformer," trending above average seasonally and improving year over year: revenues fell by 13% Y/Y compared to the 30% Y/Y decline seen in October. DRAM and MCU continued to post steady Y/Y declines while NAND and MPU were the only two sub-segments displaying positive Y/Y revenue trends, albeit at a slower pace.

Trends across key end markets were mixed with November SIA data, Barclays reports, noting a possible rebound for the automotive end market (units +4% month over month, M/M) and improving trends for computing. Shipments into communications end markets continued to decelerate after several months of above-trend growth with semi unit shipments in the consumer end markets sharply lower by -20% M/M.

Learn more about the SIA at www.sia-online.org.

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January 3, 2011 — Chalmers University of Technology researchers created a novel subharmonic graphene field-effect transistor (FET) mixer at microwave frequencies, which could serve as the basis of more compact circuit designer at high frequencies, integrated with silicon.

Figure 1. SEM of a graphene FET created at Chalmers.

A mixer combines two or more electronic signals into one or two composite output signals. At THz frequencies, mixers can be used in radar systems, radio astronomy, process monitoring, and environmental monitoring for high-resolution imaging and high-speed data acquisition. Large-scale mixer arrays or multi-pixel receivers require sensitivity, compact form factors, and power efficiency.

Graphene can switch between hole or electron carrier transport via the field effect, a symmetrical electrical characteristic that can benefit radio frequency (RF) applications. Chalmers researchers built the graphene FET (G-FET) subharmonic resistive mixer using only one transistor, circumventing the need for additional feeding circuits that take up space and power. The new type of mixer requires less wafer area when constructed and can open up for advanced sensor arrays, for example for imaging at millimeter waves and even sub millimeter waves as G-FET technology progress.

Further circuit optimization will improve the mixer’s performance, and by fabricating a G-FET device with a higher on-off current ratio, said Jan Stake, professor of the research team. "Using a G-FET in this new topology enables us to extend its operation to higher frequencies."

In addition to enabling compact circuits, the G-FET provides potential to reach high frequencies thanks to the high velocity in graphene, and the fact that a subharmonic mixer only requires half the local oscillator (LO) frequency compared to a fundamental mixer. This property is attractive especially at high frequencies (THz) where there is a lack of sources providing sufficient LO-power.

Moreover, the G-FET can be integrated with silicon technology. For example, it is compatible with complementary metal oxide semiconductor (CMOS), and could be used in CMOS electronics for backend processing on a single chip, or other applications.
 

Figure 2. Schematic picture of a subharmonic graphene-FET mixer. The LO and RF signals are fed to the gate and drain terminals, respectively, and the IF signal is extracted from the drain terminal. SOURCE: Chalmers.

The work is published in IEEE Electron Device Letters. Access it here: http://publications.lib.chalmers.se/cpl/record/index.xsql?pubid=146694
 
Swedish Foundation of Strategic Research (SSF) supported the work.
 
Chalmers University of Technology conducts research and offers education in technology, science and architecture with a sustainable future as its global vision. Chalmers is well-known for providing an effective environment for innovation and has eight priority areas of international significance – Built Environment, Energy, Information and Communication Technology, Life Science, Materials Science, Nanoscience and Nanotechnology, Production, and Transportation. Read more about the active research into graphene at Chalmers:
http://www.chalmers.se/en/news/Pages/Millions-in-research-to-take-graphene-out-of-the-lab.aspx

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December 30, 2011 — As the semiconductor industry moves into the 22nm silicon technology node, device fabrication is not the only challenge that the industry will face. According to the International Technology Roadmap for Semiconductors (ITRS), a porous ultra-low-k (ULK) material will replace the traditional silicon dioxide. Stresses within the die must be controlled, not only during wafer fabrication, but also in packaging and assembly.

This will be even more challenging than the industry

December 29, 2011 — The updated IEST "Garment System Considerations for Cleanrooms and Other Controlled Environments" recommended practice document includes new sections on measuring cleanroom footwear, frocks and other garments, as well as a new subsection for tracking system use, such as RFID chips and barcodes.

A new edition of IEST-RP-CC003.4, Garment System Considerations for Cleanrooms and Other Controlled Environments, includes a 20-page supplement on recommended garment measurement specifications. The supplement, Guide to Measuring Cleanroom Garments, provides illustrated instructions for measuring coveralls, frocks, hoods, and footwear.

The revised Recommended Practice (RP) is published by the Institute of Environmental Sciences and Technology (IEST).

Also read: ISO Cleanroom standards update

IEST-RP-CC003.4 addresses the gowning of personnel as a critical aspect of cleanroom contamination control. Specification and use of an appropriate gowning system is essential in preventing human-generated contamination from reaching and affecting product or processes in the cleanroom. The RP provides non-mandatory guidance for the selection, specification, maintenance, and testing of garments or apparel and accessories appropriate for use in non-aseptic and aseptic environments.

The RP defines required performance criteria, test methods, and procedures for gowning system use and maintenance. It also features guidelines for developing a quality control (QC) plan for the apparel and accessories that may be part of the system. This edition includes a new subsection on the use of advanced tracking systems, such as barcodes and radio-frequency identification (RFID) chips, to monitor garment service life. Also provided is a section describing types of fabrics and relevant properties and methods of testing of the materials used in cleanroom garments, as well as the design and construction of appropriate configurations and special features of such garments.

Appendix B explains the Helmke drum test method, introduced in an earlier edition of the RP and based on round-robin testing performed by the IEST Working Group. This method is used to quantify particles dislodged through the application of mechanical energy under dry conditions as a means of simulating particle shedding from the surface of the garment during use. Garments being tested are tumbled in a rotating drum to release particles from the fabric in a controlled manner, while a discrete-particle counter is used to sample the air within the drum.

Ordering information for IEST-RP-CC003.4 and other IEST publications is available at www.iest.org.

IEST is an international not-for-profit technical society of engineers, scientists, and educators that serves its members and the industries they represent (simulating, testing, controlling, and teaching the environments of earth and space) through education and the development of recommended practices and standards. IEST is an ANSI-accredited standards-developing organization; Secretariat of ISO/TC 209 Cleanrooms and associated controlled environments; Administrator of the ANSI-accredited US TAG to ISO/TC 209; and a founding member of the ANSI-accredited US TAG to ISO/TC 229 Nanotechnologies.

December 28, 2011 — The transition from 32nm to 22nm silicon will have a major impact on the semiconductor design community. The most obvious is the increase in process variation. This affects timing, but more importantly, it affects power. Because of this, we are seeing a dramatic increase in the 22nm process design rules. More and more design teams will decide to leave the IC layout portion of the design to the experts.

The effects of 22nm on the EDA vendors will be a combination of opportunity and shrinking IC layout seat count. Although the new design rules moving toward structured silicon reduce the need for optical proximity correction (OPC) tools, the move to double-patterning lithography raises new challenges for OPC tools, resulting in overall market growth. The variation problems will also drive the demand for design-for-yield (DFY) tools. The new variation challenges require that IC place-and-route tools actively ensure the robustness of the final layout, therefore, growing the IC layout market for those tools that keep up with the 22nm challenge.

This shift in responsibility won

December 28, 2011 — The Global Semiconductor Alliance (GSA) released its Global Semiconductor Funding, IPO and M&A Update for November 2011, showing that initial public offerings surged in the month, with 3 semiconductor companies entering the stock market.

November saw three semiconductor companies price initial public offerings (IPO): Cirtek Holdings Philippines Corporation (PSE:CHIPS), Intermolecular Inc. (NASDAQ:IMI), and InvenSense Inc. (NYSE:INVN).

Seven semiconductor companies raised $22.2 million in November, the same amount as October 2011. November

December 27, 2011 — Intel Corp.’s (NASDAQ:INTC) Atom chips saw plunging sales as the netbook market was swallowed by smartphones, media tablets, and like devices, but the company expanded its microprocessor leadership in Q3 2011, shows IHS iSuppli.

In Q3, Intel accounted for 83.7% of global microprocessor revenue, up 1.2 percentage points from Q2, according to IHS iSuppli Computer Systems research. Advanced Micro Devices Inc. (NYSE:AMD) is 73.5 percentage points behind Intel, holding the number 2 position. AMD