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The Facilities 450mm Consortium (F450C), a partnership of nanoelectronics facility companies guiding the effort to design and build the next-generation 450mm computer chip fabrication facilities, today announced Busch Vacuum Pumps and Systems as the eleventh member company to join the consortium. Busch Vacuum Pumps and Systems brings over 40 years of experience in the semiconductor manufacturing industry with particular focus on energy efficient, harsh-duty vacuums pumps.

“Busch’s expertise in vacuum pumps will be a great asset to the consortium as we discuss solutions for 450mm equipment transition,” said Adrian Maynes, F450C program director.

Busch Vacuum Pumps and Systems is one of the largest manufacturers of vacuum pumps in the world today, which includes a product portfolio specifically for semiconductor and related applications. Vacuum systems are a necessary component to the semiconductor manufacturing process as they remove byproduct materials following the implantation, deposition or etch processes. Busch’s next-generation vacuum pumps offer higher capacity with reduced utilities and limited downtime to support the unique demands of 450mm process platforms.

“The F450C is comprised of the top leaders in our industry, so we are honored to bring our proficiency in vacuum systems to the table,” said Charles Kane, president of Busch USA. “We have had our 450mm roadmap in place for some time, and we can now share our plans with the group to help further its 450mm vision and mission.”

The F450C is a partnership at SUNY’s College of Nanoscale Science and Engineering (CNSE) that is leading the global effort to design and build next-generation 450mm computer chip fabrication facilities. The collaboration includes 11 of the world’s leading nanoelectronics facility companies, including Air Liquide, Busch Vacuum Pumps and Systems, CH2M HILL, CS Clean Systems, Ceres Technologies, Edwards, Haws Corporation, Mega Fluid Systems, M+W Group, Ovivo, and Swagelok. Members of F450C are working closely with the Global 450mm Consortium (G450C), to identify viable solutions required for 450mm high-volume facility construction, with initial focus areas to include reducing tool installation cost and duration and improving facility sustainability.

Dow Electronic Materials, a business unit of The Dow Chemical Company, today introduced the IKONIC 4000 series of chemical mechanical planarization (CMP) polishing pads. This series of pads are initially targeting ceria-based applications.

“The pads are highly tunable and can be customized to address process specific requirements,” said Colin Cameron, director of marketing CMPT Dow Electronic Materials. “Dow’s volume manufacturing methods and commitment to process control further enhance performance by ensuring consistency and reliability in our customer’s processes.”

The new IKONIC 4000 series balances the historic trade-off associated with cutting edge planarization requirements and low defectivity. The novel chemistries deliver removal rate stability over pad life, making them ideal for the challenges associated with ceria based polishing applications. The IKONIC 4000 series delivers step-out defectivity performance representing a 70 percent improvement when compared with the industry-standard IC1000 polishing pad.

Developed in collaboration with Dow’s customers, the IKONIC 4000 series is available in multiple formulations featuring a range of hardness and porosity. This allows for customization to address specific customer requirements. The pads are also optimized for easier conditioning and to maintain consistent texture throughout the pad’s lifetime.

BOBBY ISAACS and ANYA CORNELL, Texas Instruments, Dallas, Tex.

Results can depend on the properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique.

Semiconductor chip geometries continue to shrink, causing once unimportant parameters in the manufacturing process to become more critical. With the shrinkage in transistor size and requirements for improved precision in devices, ion implantation has become an increasingly more delicate and accurate operation. Implantation angle has become extremely important as transistors have decreased in size and voltage specifications. Adjustment and pocket implants, channeling implants, and high accuracy sidewall and HALO implants have become requirements for high performance, with little to no tolerance for incorrect implantation placement.

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FIGURE 1. Illustration of wafer slicing angle and associated offset.

Older generations of ion implanters have been designed with only cursory regard to the extreme precision now required for implant placement. Because of this, semiconductor manufacturers must regularly monitor the implantation angle of these tools as part of normal production operations. In this monitoring, multiple potential issues exist that could cause a misinterpretation of the proper implantation angle, resulting in faulty tool calibration or production of out of tolerance product. This article will describe several variables to be considered when defining the angle of implant for a tool, and offer recommended conditions to achieve reliable and repeatable performance on two older implant tool sets.

The standard production test to determine if the angle of implant is accurate involves implanting 5 to 7 wafers tilted around a theoretical channeling angle, annealing the wafers to activate the implant, and charting the sheet resistance vs. implanted angle to find the channel. This procedure is commonly called a V-curve test. The as-measured channeling angle (found by identifying the minimum sheet resistance of the charted curve for the wafers, or the bottom of the “V”) should be equal to the theoretical channeling angle if the tool set-up is accurate. Unfortunately, the number of steps required by this procedure introduces errors that could lead to a false result. The properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique can all significantly affect the outcome.

Experimental
One of the most commonly overlooked variables that can introduce significant error into measurement of the angle of implant is the wafer which is used for the testing. One relevant silicon property of the wafers, the surface orientation angle offset (angle tolerance of the on-axis cut), has a significant effect. All wafers have a base surface orientation angle offset, as required by the process of slicing the wafers from the ingot (FIGURE 1).

This offset can directly translate into an offset in the V-curve measurement, depending on the angular rotation of the slice. It has been shown in previous work[3] that channeling is minimized at implant angles higher than 0.5°. In this work, the effect of the orientation angle offset on channeling was similarly studied. Implants were performed with 200mm, , N-type (phosphorus-doped) CZ wafers of resistivity 3-5 Ω-cm, surface orientation angle of 0.0+/-1°(on-axis ), Oi spec of <=32 ppma (ASTM-79), and LLS of <20 @0.20µm. The wafer type was chosen for use with Boron implant (P-type dopant) and the orientation was picked for its good channeling properties. Using the above specification, wafers were chosen at various extremes of the angle window (close to 0° and close to 1°) in order to characterize the effect of wafer angle variation. Other silicon properties shown in the spec above, such as surface defects, oxygen concentration, and resistivity are in the standard range for a typical test wafer. These parameters have a lesser effect on the implant angle measurement and were not explored in this study.

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FIGURE 2(L). Comparison of Varian E500 V-curves generated using Thermawave vs TRS-100. FIGURE 3(R). Effect of wafer orientation angle offset on V-curve of Axcelis Optima MD.

The two implant tool types used were an Axcelis Optima MD implanter and a Varian E500 implanter. Implant conditions were chosen as follows based on experimentation and comparison of common processes among multiple manufacturing facilities utilizing several tool types: Boron11 at 100 keV energy, 1.0e14 ion/sq dose, 35° tilt, and 0° twist. Boron11 was chosen as the dopant for its small mass and channeling properties, as discussed in Downey, et.al.[2] Energy of 100 keV is high enough to prevent outgassing of the dopant during the anneal process, and 1.0e14 ion/sq dose was chosen to place the resultant resistance as measured on a standard Tencor RS-100 into a stable range for the measurement equipment.[1] For all tests, the ion beam was optimally tuned to minimize beam instability or non-linearity. The potential process variables influencing beam steering on the tool were not explored during this experimentation, but it should be commented that an improperly tuned ion beam will also significantly affect the result. A tilt angle of 35° was chosen as the optimal channeling condition. Although multiple potential channeling angles exist for [100] N-type silicon wafers, the angle of 35.26o has shown the most sensitive, clear channel for implant angle testing[1], and it is also recommended by Varian Semiconductor[4]. A twist angle of 0° was applied for best resolution of the channel in all but one of the tests, which utilized a rotation angle of 90° to characterize the effect of the wafer substrate angle offset.

The anneal process needed to be selected in such a way as to eliminate any variation or sensitivity due to temperature of anneal, anneal time, or even annealer tool type. An anneal temperature of 1060oC for 30 seconds was selected from earlier work[1] as the condition at which small temperature variations can be tolerated. Two types of annealer tools were used – an Axcelis Summit furnace annealer, and an AG Associates 8800 lamp annealer – to determine if the V-curve could be shifted through anneal by varying the tool type.

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FIGURE 4. Effect of wafer orientation angle offset and wafer rotation on V-curve of Varian E500

Measurement of sheet resistance is well documented for ion implant processing. For this experimentation, Thermawave and Tencor RS-100 measurement tools were researched to identify possible areas of concern in the measurement of V-curve wafers. The advantage to Thermawave processing is the elimination of the need for anneal after implant, removing this source of potential variation. Also, a previous experiment with a different implant has shown that the Tencor RS-100 produces a sharper V-curve than the Thermawave (see sample V-curve in FIGURE 2). Therefore, the Tencor RS-100 tool was chosen for the present work. Testing on the Tencor RS-100 was performed using both 9-point and 49-point radial measurement patterns.

Results and discussion
By far the strongest effect was observed from the silicon wafer orientation angle offset. In particular, at angles above 0.5o, the effect was so pronounced that it shifted the V-curve. See below graph of two sets of wafers processed with identical implant and anneal conditions. The only difference was the orientation angle offset (0.04° vs 0.68°), as shown in FIGURE 3.

In an effort to further characterize the effect of a larger orientation angle offset of the wafers, testing was performed by rotating the wafers 90o during the implant to measure the change in the resultant V-curve. Using wafers with very small surface orientation offset angles (0.04o), the change in the measured V-curve could not be easily seen. However, using wafers with a surface orientation offset angle above 0.5o (0.68o), the change in the measured rotated V-curve became much more visible (FIGURE 4). Repeatability of the tests using high surface orientation angles was also noted to be inconsistent, with significant variance in results from test to test.

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FIGURE 5. Effect of anneal tool and temperature on V-Curve of Varian E500.

Based on the results presented above, it is our recommendation that high-angle offset wafers (above 0.5°) should not be used for implant angle qualifications. It is also recommended that the surface orientation angle of the test wafers be scrutinized if the V-curve produced shows abnormal variance from the expected outcome. To reduce variability from other wafer parameters, we also recommend a tight resistivity specification (ex: 3-5 ohm-cm) for the silicon ingot, and advocate the use of wafers not only from the same ingot, but from the same area of the ingot, to ensure similar properties.

Minor effects were observed from other variables studied. An experiment comparing two anneal temperatures confirmed earlier findings1 of 1060C being the optimal temperature to produce a sharper V-curve (FIGURE 5). The type of anneal tool was also a factor. Although the process was matched as closely as possible through matching of the thermal budget, a difference could be seen between the annealer types (Fig. 5, left). Based on the clarity of the V-curve inflection on the lamp annealer, this tool was used as the benchmark for anneals during other experiments.

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FIGURE 6. Effect of measurement map resolution on V-Curve of Axcelis Optima MD.

As for the Sheet Resistance measurement, very little to no effect was observed from varying the measurement pattern and number of measured points. A 9-point measurement showed the same accuracy as a 49-point measurement, making the additional points unnecessary (FIGURE 6).

Conclusion
As a result of this testing, multiple recommendations can be made to ensure accurate and repeatable measurement of the implant angle of a tool. These areas can result in significant variation of results if not accounted for during testing. The silicon quality of the wafers is one of the most overlooked variables in performance of implant angle measurement. The surface orientation angle offset can significantly change the measured implant angle, especially in ranges above 0.5° (from on-axis cut). Wafers with angle cut tolerance greater than 0.5° produce inconsistent results, severe enough to shift the sheet resistance values or even the entire V-curve, and are therefore not recommended for implant angle testing.

The parameters used in implantation also contribute significantly to the resolution and accuracy of a V-curve test. Although multiple potential channeling angles exist for [100] N-type silicon wafers, a 35° angle is recommended as the most sensitive, clear channel for implant angle testing.[1,4] The implanted species, energy, and dose all contribute to the stability and repeatability of the measurements. Once implanted, the anneal of the wafer must be tuned to a temperature and thermal budget that minimizes variation, as this will also cause slight changes in results. Finally, measurement techniques can change the outcome of a V-curve test through differences in the measurement tool used.

Once the angle of implant of a given tool is characterized, regular verification (qualification) is highly recommended, especially for events which involve components handling wafer orientation. To save on wafer cost, a test may be performed using 1 or 3 wafers once the baseline sheet resistance of the channeling angle is obtained, and charted through standard SPC techniques. If a failure is observed, escalation of the testing can then include a full 5 or 7 wafer V-curve test to determine if the angle of implant has shifted. Standard troubleshooting for common sheet resistance failure events should be included in disposition of a failure, since hardware issues in the form of leaks, contamination and other failure modes can influence the sheet resistance measurement obtained during angle testing.

Acknowledgments
The authors would like to thank TI silicon material technologist Thomas McKenna for valuable insight into starting material properties, as well as Jeff Bell of SUMCO-USA for providing substrate orientation angle data.

1. Rathmell, M.A. (2006). Implant Angle Monitoring – A Comparison of Channeling Features. Ion Implantation Technology Conference Proceedings, Marseille, France, June 11-16.

2. Downey, D.F., Arevalo, E.A., Eddy, R.J. (2000). The Significance of Controlling “Off-Axis” (from 1-0-0) Oriented Si Wafers During High Angle Implants. Ion Implantation Technology Conference Proceedings, Alpbach, Austria, September 17-22.

3.Guo, B.N., Variam, N., Jeong, U., Mehta, S., Posselt, M., & Lebedev, A. (2002). Experimental and Simulation Studies of the Channeling Phenomena for High Energy Implantation. Ion Implantation Technology Conference Proceedings, Taos, New Mexico, USA, September 22-27.

4.Canning, Stephen, (7/17/2006). BKM – System related Checks for Process Control, PSB2621A, Varian Semiconductor VSEA Product Support Bulletins, Pg. 6.

BOBBY ISAACS is an Ion Implant Fabrication Engineer for Texas Instruments’ DMOS5 manufacturing site in Dallas, TX ([email protected]). ANYA CORNELL is an Ion Implant and Silicon Processing Engineer for Texas Instruments’ MFAB manufacturing site in Portland, Maine.([email protected]).

Brooks Instrument, a provider of advanced flow, pressure, vacuum and level solutions, has expanded its GF 40/80 Series portfolio of thermal mass flow controllers. Broader capabilities, including increased flow rates up to 50 slpm and a “normally open” valve for non-hazardous gas applications, are ideal upgrades for users of Aera (Hitachi), Celerity, Tylan, Mykrolis, Millipore and Unit mass flow controllers, as well as other competitive devices.

The GF 40/80 Series leads the market in long-term zero stability at less than 0.5% per year. This specification means the device will return more reliable accuracy data for a longer period of time, giving users greater confidence in the numbers reported. The GF 40/80 Series is also available with Brooks’ patented MultiFlo, a powerful technology that enables users to re-program the gas and/or range in minutes without the trouble and cost of removing the mass flow controller from service. Brooks has expanded the flow rates for the GF 40/80 Series from 30 slpm to 50 slpm, making these devices an excellent choice for applications that require a higher flow rate with the flexibility of a MultiFlo-capable mass flow controller.

Newly expanded RS485 communication protocols increase the flexibility and application range of the GF 40/80 Series. These versions of the RS485 protocols are ideal for users of Aera (Hitachi), Celerity, Tylan, Mykrolis, Millipore and Unit mass flow controllers, which are now part of the Brooks product line following its acquisition of Celerity Instrumentation in 2009. These end users can now upgrade to a device that offers better accuracy and repeatability while keeping the same communication protocols.

The GF 40/80 Series also integrates the EtherCAT communication protocol, which is a high-performance, ethernet-based fieldbus system designed for process control applications requiring short data update times with low communication “jitter.” Adopted by leading-edge technology companies, EtherCAT makes it easier to network instrumentation for advanced process control and diagnostics capabilities.

The GF 40 is now equipped with a “normally open” valve for non-hazardous gas applications that require a fully open valve in the event of a process interruption. Normally open valves are desirable in applications where it is preferable for the valve to remain open even if a facility loses power, so that the mass flow controller continues to provide maximum purge gas flow from the system.

The GF 80 also features a new Teflon valve seat. The valve seat is non-reactive, which allows the GF 80 to be used in applications for corrosive and reactive gases.

mass flow controllers

July 6, 2011 — Avantor Performance Materials will launch the first in its new J.T.Baker SLCT Series of selective etch surface treatment chemistries, SLCT 128 sigma etchant, at SEMICON West 2011.

J.T.Baker SLCT 128 sigma etchant simultaneously cleans and selectively etches the wafer substrate in poly-gate architectures, creating a cavity for strain engineered gate structures. No pre-implant operations are required to tailor the initial etching. Highly controlled etch is paired with post-etch residue removal and pre-cleaning. The resultant clear, well-defined faceted sigma shape for epitaxy suits advanced nodes, and users may cut out an additional rinse after the process. Plasma pre-etching can be eliminated or reduced in some operations.

The self-cleaning etch chemistry can be used in front end of line (FEOL) wafer fab on strained silicon channels where silicon germanium (SiGe) and silicon nitride (SiN) induce strain on the silicon lattice under the gate region; FinFET structures where the semiconductor material is vertical rather than horizontal; and other advanced wafer processes.

The etchant was created through a joint development agreement between Avantor and SACHEM Inc., which covers specialty surface preparation and removal chemistries for thin-film wafer stacks. Avantor applied photoresist/residue removal technologies, while SACHEM engineered bulk etchants and surface prep aspects. Under the agreements, the companies established a global applications team supported by Avantor’s advanced wafer processing equipment.

Combining the companies’ core strengths in selective etch products enables better semiconductor manufacturing, said John Bubel, director of marketing, electronic materials, at Avantor, adding that the partnership smartly boosts investment in research and development. Tom Mooney, president of SACHEM Asia, added that the partnership is targeting emerging sub-22nm nodes, cutting down on process materials consumption and steps.

Avantor and SACHEM are developing other selective etch and targeted layer removal solutions with leading semiconductor manufacturers in Asia and the Americas.

Avantor plans to expand the SLCT Series with additional selective etch products in the near future, targeting selectivity to metal oxides and integration stacks common in advanced memory chip manufacturing.

To learn more about SLCT 128 sigma etchant and other selective etch products in development, visit Avantor booth 1607 at SEMICON West, July 12-14 at the Moscone Center in San Francisco, CA.

Avantor Performance Materials (formerly Mallinckrodt Baker, Inc.) manufactures and markets high-performance chemistries and materials. Avantor makes products used in the manufacturing of semiconductors, photovoltaic cells and flat panel displays (FPD). For additional information, visit www.avantormaterials.com

SACHEM Inc. delivers highly pure, precise and innovative chemical solutions designed to solve the most demanding and challenging applications. Learn more at www.sacheminc.com

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April 28, 2011 — ASM International N.V. (NASDAQ: ASMI and Euronext Amsterdam: ASM) received multiple system orders for its plasma enhanced atomic layer deposition (PEALD) reactor from a leading memory customer in Asia. Second, the company qualified a new PEALD oxide application with a memory manufacturer for the 2X nm node.

“Our innovative PEALD technology is seeing strong market validation with high-volume business from multiple top tier memory customers,” said Tominori Yoshida, general manager of ASM’s Plasma Products business unit. “Our increasing range of production-ready PEALD applications position us to support memory manufacturers now and as they move towards the challenging 1X nm node.”

The PEALD systems were ordered by a leading memory customer for high-volume manufacturing and will be installed in multiple facilities in Asia. The reactors will be used to deposit dielectrics for advanced lithography double patterning applications at the 3X nm technology node and below. This order represents the second major manufacturer to adopt ASM’s PEALD system for use in double patterning in high volume manufacturing.

ASM also qualified a new oxide application for an advanced PEALD SiO layer that targets manufacturing at the 2X nm node and below. The new application is expected to enter volume production later this year with a different Asia-based manufacturer.

ASM’s PEALD reactors are optimized to deposit dielectrics including SiO, SiN and SiCN. The process delivers conformal thin films at low temperatures, for double patterning lithography technologies where thin dielectrics are deposited over temperature-sensitive photoresists for critical dimension control and pitch reduction.

Each of the systems ordered includes multiple PEALD reactors implemented on ASM’s XP platform. The XP is a production-proven standard platform that can be configured with plasma enhanced chemical vapor deposition (PECVD), thermal ALD or PEALD reactors.

Also see: Below 22nm, spacers get unconventional: Interview with ASM

ASM International N.V. and its subsidiaries design and manufacture equipment and materials used to produce semiconductor devices, wafer processing (Front-end segment) as well as assembly and packaging (Back-end segment). ASM International’s common stock trades on NASDAQ (symbol ASMI) and the Euronext Amsterdam Stock Exchange (symbol ASM). For more information, visit ASMI’s website at www.asm.com

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Executive OverviewCertain inherent process characteristics such as precision, cleanliness, control and high productivity have been the hallmark of the entire implant industry for some time. Coupled with new capability, implant has become less of a commodity product and more enabling. In fact, the makers of the industry’s next-generation devices are looking to implant to improve established doping applications and facilitate new precision materials modification applications to provide device performance and yield improvements required for 22nm.

James L. Kawski, Varian Semiconductor Equipment Associates, Gloucester, MA USA

Recently, implant has re-emerged as an enabler improving device performance and process variability that would otherwise unacceptably degrade as technology moves to 22nm.

It is becoming more and more apparent that subsequent node transitions will expose new device performance and process limitations driven by scale and physics. Also, tool performance specifications that for several nodes have been taken for granted, will start to become obsolete. In particular, CMOS transistor yield is adversely affected by scaling due to increasing leakage current from multiple sources. The formation of highly activated ultra shallow junctions (USJ) that are both stable and abrupt is a significant challenge [1]. To circumvent this dynamic, the industry has developed damage engineering strategies through cryogenic implant technology and co-implants.

Other limitations are emerging that are impacting other process areas in the fab. Using implant as a precision material modification (PMM) tool, in contrast to its traditional role as a semiconductor dopant tool, provides enabling technology and new applications to drive total available market (TAM) growth. For example, in the formation of ultra-sensitive gate regions, previously acceptable amounts of photoresist line edge roughness (LER) have become a source of threshold voltage variability that will increase leakage current and add to yield loss.

Cryogenic ion implant

A variety of complex device problems present themselves at the threshold of the 22nm technology node, particularly for boron-doped PMOS transistors. Dopant activation and defect creation at the sub-surface source/drain junction and surface regions become significant limiting issues. Through techniques referred to as damage engineering, implant is able to neutralize these effects and enable transition to 22nm.

Boron source/drain doping for PMOS transistors are run on high current ion implanters with beam powers that would normally elevate wafer temperatures that would cause photoresist masks to deform. Historically, simple backside liquid cooling schemes using commercially available chillers would be adequate to keep wafer temperatures from exceeding 70°C.

To facilitate low leakage, high quality sub-surface junctions, high dopant activation and low surface defectivity in the implanted region must be uniformly amorphous.

After milli-second flash or laser annealing, a low-defect, low-resistivity source/drain is desired. With device features at 22nm, junction depths must be under 10nm to minimize short channel effects (SCE). At these junction depths, natural dynamic annealing occurs during the implant process creating interstitial vacancy clusters at room temperature and above. By cooling the wafer during implant it has been demonstrated that self interstitials present at the end-of-range of the implant are reduced. This results in a significant reduction in dopant diffusion and deactivation. It has also been widely reported that lower temperatures down to -100ºC are the most effective [2]. With the expansion of cryogenic cooling into medium current applications such as HALO, maintaining wafer temperature during implant down to -100ºC will be absolutely essential.

Implementation of cryogenic wafer temperatures during implant at high vacuum present a rather significant engineering problem. Varian Semiconductor Equipment Associates (Varian) PTC II hardware has achieved the required temperature range while maintaining ultra-low particle performance and high productivity. Considering the added time necessary to cool and return the wafer to room temperature, Varian’s VIISta platform with batch load lock capability optimized this implementation for maximum productivity.

Molecular dopants

Another proven technique to enhance device performance and yield is through molecular dopants. For years BF2 has been used in the industry with excellent results. Recently the use of carborane (C2B10H12 – “CBH”) has proven an effective and stable option to introduce carbon into the lattice during PMOS source/drain doping.

CBH provides multiple benefits including reduction of end-of-range (EOR) defects, improving dopant activation and reducing lateral diffusion. A reduction of junction leakage (through diode leakage studies) of 50% has been reported [2]. The deactivation and eventual reactivation of boron in annealed silicon has been shown to benefit greatly from the use of cryogenic implant. Significant improvement in sheet resistivity when CBH is implanted at -100ºC compared to room temperature as illustrated in Fig. 1.

Figure 1. The best Rs/Xj performance has been shown @ -100°C implant temperature. The colder the better for Rs/Xj control.

Varian’s experience with Synopsis’ Technology Computer Aided Design (TCAD) Software has shown that increased surface activation of boron is due to ultra-shallow carbon associated with CBH [3].

Figure 2. Drive current and leakage current of PMOSFET with CBH.

Studies have shown that ultra shallow carborane implantation into pMOS S/D extensions provided enhanced surface activation and reduced sub-surface junction leakage [4]. When comparing the use of a pre-amorphization implant using Ge with and without CBH, the results were striking (Fig. 2). Drive currents of pMOS at -1.1V supply voltage increased by 20% with the use of CBH. Reduction of parasitic resistance and increased activation at the surface was responsible. Also, a demonstrated reduction in leakage current has been shown, which can be attributed to lower junction defectivity.

Tighter angle control

Prior to 32nm half-pitch, post-implant anneals would effectively smear out dopant profile variations resulting from “across wafer” or “across device” angle variations. Beam angle is affected by three prime components: 1) Global steering angle caused by beam tuning repeatability issues, 2) Local steering angle controlled by beam optics design, and 3) Within-device angle spread due to space charge effects [5]. It has been shown that for 32nm devices, as little as 1º of beam steering angle variation during extension implants can lead to a 3% reduction in Idsat [6].

To meet these angle accuracy demands, sophisticated beam angle measurement and adjustment technology has been developed that provides both vertical and horizontal control [7]. Current available technology has proven capability to control beam angle deviation down to 0.1% resulting in marked improvements to NMOS and PMOS Idsat.

Uniformity

It is generally accepted that uniformity and precision go hand in hand. Ultimately, control of non-uniformity will result from reducing variability in the implanter at various points in the beam-line. The effort to control variability will result in a cumulative set of added controls that ultimately increase an implanter’s flexibility for other applications. So it is with the current state of ion implant. Uniformity can be defined wafer-to-wafer, die-to-die and transistor-to-transistor. Micro-uniformity is of increasing importance as transistors get smaller and die get larger.

Precision dopant placement is affected by both ion beam dynamics and wafer handling capability. Controlling ion beams is particularly challenging since tool makers have to deal with space charge where the main challenge is transporting beams of like charged ions that naturally diverge. After years of development, ribbon beams have become a controllable means of beam transport. This development occurred at the beginning of the decade facilitating the move to single-wafer platforms. Also, wafer handling systems using highly flexible rotational platens that can reposition wafers without removal from the beam path provide exciting new capability with no loss in throughput. For example, implant can compensate for variability in other processes such as photolithography, chemical mechanical planarization, and spike anneal. Scanning an implant at different rotation angles creates a cross-wafer doping distribution that is intentionally non-uniform in opposition to the incoming non-uniformity from other process steps. This has been successfully implemented, particularly for improving threshold voltage variability on CMOS transistors, on medium current tools.

For the future, it is expected that enhanced uniformity control and beam angle control will contribute to new device integration efforts. As an example, device makers are looking to these technologies for development of 3D structures.

Energy contamination-free implant

Sub-2 keV implants are necessary to obtain the required ultrashallow junction (USJ) to control SCE for sub-45nm devices. These low energy beams lose more beam current due to space charge effects adversely affecting productivity. Instead of “drifting” these low energy beams, implanter makers have resorted to accelerating the beam, then decelerating it just before the wafer to maintain beam current and increase productivity. This deceleration creates neutralized ions that do not fully decelerate thereby entering the wafer at a higher energy. This energy contamination creates a tail on the profile that will increase leakage at the sub-surface junction. Recent improvements to high current beam lines have enabled full energy purity capability for deceleration technology applied to recipes from 500eV to 2keV.

Figure 3. Low-energy boron SIMS plot: The latest generation of high current implanters provide full energy purity at maximum throughput.

Since dopant activation is critical, device makers can now utilize phosphorous for NMOS source drain implants. Phosphorous has a higher activation level over arsenic. Historically, heavier arsenic was the dopant of choice because implanters ran more productively at higher energies and it diffused less during activation. Now device makers can run phosphorous at or below 2keV, achieving high activation while maintaining high productivity. Adding carbon co-implants to the NMOS source/drain region retards phosphorus diffusion during activation and keeps the junctions shallow. With this new implant technology, device makers can now achieve very high productivity free of energy contamination.

Improving lithography through materials modification

Implanting dopant atoms changes the conductivity of silicon. The use of implant with other materials results in physical or chemical changes to the target. Utilizing PMM with lithographic applications has resulted in several growth opportunities for implant. Reduction of line edge roughness (LER) or line width roughness (LWR) is one widely investigated application.

Figure 4. Comparison of implanted photoresist samples to a reference sample showing CD and LWR changes.

LER does not decrease as line-widths do. Consequently, it becomes a larger percentage of overall variability. Short wavelength LER and LWR is due to residual resist molecules left after development while long wavelength LER is due to interference patterns created by patterning light sources. LER for lithography typically uses heavy ions such as argon, neon or silicon which result in sputtering processes at the wafer when applied. Reduction or elimination of resist roughness through implant is enhanced by exploiting the angular dependence of sputter rates. In one study, silicon and argon were evaluated by implanting at a fixed dose of 5E15 ions/cm2 with a fixed tilt angle of 60 degrees [8]. In this analysis, both critical dimension and LWR were measured (Fig. 4). The ion implanted resist shows a change in CD as well as a reduction in LWR. At the same energy, argon still exhibits a greater CD loss and LWR reduction. As has been shown, non-reactive ion beam species has won out in comparative studies with other techniques providing anywhere from a 25% to 500% improvement [9].

Conclusion

Through a combination of established implant technology and newly developed hardware, ion implant is providing enabling applications for 22nm device integration. Cryogenic ion implant, where the wafer is held at temperatures down to -100C during implant, has proven to reduce device leakage and increase dopant activation. When used in conjunction with molecular dopants, such as carborane, where carbon can be introduced into PMOS source/drains, as much as a 50% reduction in junction leakage has been reported. Improvements in beam angle control have proven to increase device speed directly through improvements in Idsat. Tradeoffs between high productivity and low energy contamination have been prominent in the past. New hardware designs have attained the elusive goal of full energy purity and high productivity for the lowest energy implants. Finally, the use of implant for precision material modification has shown significant promise to extend other process capabilities namely in lithography through reduction of line edge roughness.

Acknowledgments

The author would like to thank Chris Campbell, Benjamin Colombeau, Fareen Khaja, Niranjan Khasgivale, Patrick Martin, Curt Norris, Tom Parrill and Dennis Rodier for their support.

References

  1. F. Khaja, B. Colombeau, T. Thanigaivelan, D. Ramappa, T. Henry, “Benefits of Damage Engineering for PMOS Junction Stability,” 2010 Inter. Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
  2. C.I. Li, P. Kuo, H.H. Lai, K. Ma, R. Liu, H.H. Wu, et al., “Enabling Solutions for 28nm CMOS Advanced Junction Formation,” 2010 Inter. Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
  3. C.I. Li, T.M. Shen, H.H. Lai, P. Kuo, R. Liu, H.Y. Wang, et al., ” Integration Benefits of Carborane Molecular Implant for State-of-the-Art 28nm Logic PFET Device Manufacturing,” IEEE Electronic Device Letters, to be published.
  4. B. Colombeau, T. Thanigaivelan, E. Arevalo, T. Toh, R. Miura, H. Ito, “Ultra-Shallow Carborane Molecular Implant for 22nm Node p-MOSFET Performance Boost,” Inter. Workshop on Junction Tech., 2009, pp. 27-30.
  5. A. Renau, “Device Performance and Yield – A New Focus for Ion Implantation,” Inter. Workshop on Junction Tech, 2010, pp 1-6.
  6. H.J. Gossman, T. Romig, et al., “Precision Requirements for Advanced HP Logic Implantation,” Solid State Technology, July 2007.
  7. J.C. Olsen, et al., 17th Int. Conf on Ion Implantation Tech, Monterey, USA, pp. 129-132, 2008.
  8. P. Martin, L. Godet, A. Cheung, G. de Cock, C. Hatem, “Ion Implant Enabled 2X Lithography,” 2010 International Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
  9. C.R.M. Struck, R. Raju, M.J. Neumann, D.N. Ruzic, “Reducing LER Using a Grazing Incidence Ion Beam,” Proc. of SPIE Advanced Lithography 2009 Vol. 7273-49.

Biography

James L. Kawski received his BS in electrical engineering from The Rochester Institute of Technology and is manager of market research and communications at Varian Semiconductor Equipment Associates, 35 Dory Road, Gloucester Massachusetts, 01930; ph.: 978-282-2000; email [email protected].

Solid State Technology | Volume 54 | Issue 3 | March 2011

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Executive Overview

Atomic layer deposition (ALD) will be used in multiple areas of the 22nm logic process flow despite initial concerns about the technology’s viability for high-volume manufacturing. Each application space creates a unique need for manufacturing equipment configuration and technology variations – from single-wafer ALD systems for extremely tight process control, batch ALD systems for low COO operation, to mini-batch systems for a meld of COO and process control for multi-layer applications. Selection of the appropriate manufacturing toolset is as critical to eventual technology adoption as the process itself, and final implementation will require the correct toolsets to ensure that the ALD films can be deposited in a cost efficient manner.

M. Verghese, ASM, Phoenix, AZ USA;  J. W. Maes, ASM, Leuven, Belgium; N. Kobayashi, ASM, Tokyo, Japan

Since its invention in the 1970s, atomic layer deposition (ALD) has been used in a variety of applications ranging from electroluminescence display manufacturing to industrial coatings [1]. Over the last decade, the semiconductor industry has slowly been adopting ALD reactors for critical layers where the benefits of ALD enable scaling and improved performance. With the upcoming transition to 22nm, process flows are being adapted to allow ever more ALD layers. As a variant of chemical vapor deposition (CVD), ALD techniques capitalize on surface saturation reactions to deposit extremely smooth, dense, and highly conformal films through a process that is relatively insensitive to fluctuations in process temperature and reactant flux. The ALD process relies on sequential introduction of the reactants into the reaction space, separated by inert gas purges, such that repetition of the ALD cycles results in a monolayer by monolayer growth of the deposited film. Thickness of the film can then be precisely controlled by adjusting the number of ALD cycles.

Process considerations for single-wafer tools

DRAM manufacturers were the first to use ALD to ensure conformal deposition of high-k dielectrics in high aspect ratio capacitor structures. Aggressive scaling of device dimensions and the subsequent requirement of low thermal budgets to control dopant diffusion continue to push the entire semiconductor industry to displace conventional CVD, plasma enhanced CVD (PECVD), and sputtering techniques with novel ALD processes in critical areas such as transistor gate stack formation and spacer defined double patterning. The low throughputs that are typically associated with ALD techniques have been a barrier to its adoption in mainstream production flows. However, these concerns are being addressed by intelligent equipment design to optimize the ALD process and hardware for individual application spaces. At the 22nm node, the logic industry will use ALD in several key process steps – both in front end transistor formation and in back end metallization and interconnect. Each application has highly specific requirements and calls for different hardware configurations for the optimal production solution.

Single-wafer ALD chambers are ideal when the application demands extremely thin films with precise thickness and uniformity control. Single-wafer systems can also most easily handle difficult precursor chemistries such as low vapor pressure, decomposition prone liquids and solids since ALD cycle times are typically short (in the order of a few seconds) and the source delivery systems can be placed in close proximity to the reaction chamber. Purge efficiency can be optimized relatively easily in single-wafer systems and as a result, these chambers are ideal for pure ALD deposition.

Figure 1. Need for complete ALD high-k/metal gate solution in 22nm logic transistors.

Single-wafer ALD systems also have high precursor utilization efficiencies and hence, are a good fit for processes that use expensive precursor materials. For example, high-k dielectrics and metal gates for transistor gate oxide and electrodes require deposition of films as thin as 10Å while maintaining within wafer uniformities of <1%, 1σ. Hafnium-based high-k gate oxides typically use hafnium chloride, a solid precursor, for its excellent electrical performance when compared to metal organic chemistries [2]. Single-wafer systems tend to be the best choice for gate oxide deposition as they are very capable of delivering this highly condensable precursor. Furthermore, replacement gate devices require multiple, conformal metal films <50Å thick to ensure that space remains for a gate contact fill (Fig. 1). Single-wafer plasma-enhanced ALD (PEALD) is also used for the deposition of silicon oxide, silicon nitride, and silicon carbon nitride gate spacers. PEALD enables low-temperature deposition (<400°C), excellent conformality, and lower wet etch rates than films deposited by plasma enhanced CVD (PECVD). Film stress can also be varied from compressive to tensile by varying plasma processing conditions [3]. Techniques such as PVD and CVD are unable to attain the step coverage, thickness control, and cross-wafer uniformities required for such an application; single-wafer ALD has been gradually replacing these techniques in high performance logic gate structures since the 45nm node [4]. By the 22nm node, all primary gate stack materials will be deposited by ALD processes. The advent of three-dimensional architectures such as FinFETs, and the film conformality requirements that come therewith, will ensure that ALD will be the deposition technique of choice for the next several generations of advanced logic gate stack structures.

Batch tools for thicker films/high-aspect ratios

When film thicknesses are less than one hundred angstroms thick, ALD process times are typically no longer than a few minutes. Single-wafer tools then give acceptable throughput performance and short turn-around times. However, for some applications, the process times are inevitably longer. This can occur when thicker layers are required or when films have to be deposited in high-aspect ratio structures. Substrates with high-aspect ratio structures have a larger surface area than planar wafers and usually require a higher precursor dose and subsequently need longer pulses and purge times to enable effective gas transport into and out of the structures. Also, some ALD chemistries can have lower growth rates than others and some processes may require relatively long pulses to ensure complete surface reactions to achieve the desired film quality.

The throughput and cost-of-ownership (COO) performance of batch ALD approaches with ~100 wafer loads in one reactor can be substantially better than that of single-wafer systems. Pulse and purge times have to be longer in batch reactors because the volume of the reactor is larger and the gas transport depends more on diffusion (rather than forced convection) than in single-wafer systems. However, the total increase in cycle time is smaller than a factor of 100, more on the order of 10-50. Process optimization in a batch system is more complex than in a single-wafer system but for ALD chemistries that result in self-limiting ALD surface reactions, relatively good uniformities and step coverage can still be achieved. The precursor flow and total dose that is delivered to the batch reactor is typically much larger than in single-wafer applications, especially when high aspect ratio device structures are involved. However, techniques such as direct liquid injection (DLI) can be used to mitigate precursor dose delivery issues as long as the vapor pressure of the precursor is sufficiently high. Low vapor pressure precursors (which also can be solid powders) are more troublesome in batch equipment due to risk of condensation and decomposition associated with the high residence time in the reactors.

ALD titanium nitride using titanium chloride and ammonia meet all the criteria required to make batch processing an attractive option. Titanium nitride films are used in several applications in logic devices: electrodes for replacement gates, electrodes for embedded DRAM devices, barrier films in tungsten contacts, and through- silicon-via (TSV) structures. Required film thicknesses are in the range of 20−150Å.

Figure 2. Step coverage of batch pulsed CVD TiN film in 32:1 trenches.

The process can be run in two modes: a strict ALD mode where completely separated titanium chloride and ammonia pulses are used (resulting in a growth rate of ~0.3Å/cycle), but also in a second mode in which one of the two pulses is actually a CVD pulse. In the pulsed CVD mode, a higher (3-5x) growth rate can be achieved. Batch reactors are able to run ALD-like processes such as pulsed CVD, with good results. The resulting film resistivity is a function of deposition temperature. In the ALD mode, one can use about 100°C lower deposition temperature to achieve the same resistivity as films deposited by the pulsed CVD mode [5]. Figure 2 shows an example of the deposition of a thicker layer of titanium nitride in a high aspect ratio structure. A highly conformal film is achieved, with step coverage of better than 95%, using the ALD-like pulsed CVD process mode in a batch reactor. Batch reactors can run at a throughput of greater than 30wph per reactor for 10nm films. These results demonstrate that batch-type ALD reactors are an attractive tool choice for some of the new ALD applications in future logic devices.

Mini-batch or multi-wafer ALD systems

When deposition of thicker films using complex precursors is required at reasonable throughputs and with short turn around times, a mini-batch or multi-single-wafer ALD system is the most appropriate. Mini-batch and multi-single-wafer ALD reactors meld the flexibility of single-wafer systems with the productivity of batch reactors. Typically, a mini-batch reactor processes four to five wafers together in one reactor and a multi-single-wafer system processes four to five wafers in individual reactors packaged in one module. These types of reactors can result in improved COO when compared to single-wafer systems as they occupy less floor space and rely on fewer, shared sub-systems. For example, gas panels, RF systems, and pumps can be combined for use on a mini-batch system whereas single-wafer tools would require multiple individual sub-systems. In addition, creative design of mini-batch systems can allow the use of direct plasma to enable plasma-enhanced ALD processes.

Spacer-defined double-patterning (SDDP) will likely be introduced to manufacture highly scaled lines and spacers for 22nm logic devices. In this technology, a conformal, ALD silicon oxide (SiO2) film is deposited directly on photoresist at extremely low temperatures. This is followed by an anisotropic etch-back process that results in the formation of SiO2 spacers that act as hard masks with smaller pitches. For this application, a mini-batch (multi-single-wafer) system is useful – ensuring high throughput in a system that can utilize direct plasma to enable deposition at near room temperatures. PEALD SiO2 using a mini-batch system results in conformal deposition at low-temperatures (<100°C) with within-wafer and wafer-to-wafer uniformity < 1%, three sigma. Throughputs can be achieved at >45wph per reactor at 20nm film thickness with high equipment utilization due to in situ remote plasma cleaning capability.

One cycle of PEALD SiO2 consists of 3 steps: chemisorption of an aminosilane precursor on the substrate, purging the precursor by inert gas flow, and plasma-assisted surface reaction of chemisorbed precursor with reactant gas. The RF-based plasma pulse is <400ms in length. Growth per cycle (GPC) of PEALD SiO2 increases with decreasing deposition temperature [6]. This GPC temperature dependence indicates the ALD reaction is limited by the desorption rate of the physisorbed precursor, which increases with increasing deposition temperature. Because this is an ALD process, film thickness is proportional to cycle number and thickness can be precisely controlled. These PEALD films have been confirmed to not cause plasma damage to the underlying substrate/films as the RF power during the deposition process is much smaller (<50W) than that of conventional PECVD.

Figure 3. PEALD SiO2 deposition on resist at 50ºC.

As shown in Fig. 3a, 300Å of a conformal SiO2 film can be deposited directly on resist at 50°C without any damage. Furthermore, in situ treatments can be used to widen the space between lines and/or reform the resist shape. Figure 3b shows an example of in situ treatment before SiO2 deposition. In this case, the resist is slimmed isotropically by ~65Å. Within wafer uniformity of the treatment process is typically <2%, 3σ. This is a good example showing the process flexibility gained by using a mini-batch system, while sustaining the high throughputs required for manufacturing.

Conclusion

Overcoming the initial barriers to adoption has required the creation of several toolset configurations to address the unique issues in specific applications. Single-wafer, batch and mini-batch ALD solutions are available, each with thermal and plasma enhanced capabilities, and selection of the appropriate manufacturing toolset is as critical to eventual technology adoption as the process itself. In very cost sensitive markets such as memories, cost-of-ownership (COO) will be a main driver for equipment selection. In foundry or other logic applications, equipment choice is more a mix between COO, turn-around time and process performance considerations and choices of equipment type have to be made with careful regard to the specific application.

References

1. C. Goodman, et al., “Atomic Layer Epitaxy,” Jour. of Appl. Physics, R65-R81, 1986.

2. D. Triyoso, et al., “Physical and Electrical Characteristics of Atomic-Layer-Deposited Hafnium Oxide Formed Using Hafnium Tetrachloride and Tetrakis(ethylmethylaminohafnium),” Jour. of Appl. Physics, Vol. 97, 124107, 2005.

3. H. P. W. Hey et. al., “Ion Bombardment: A Determining Factor in Plasma CVD,” Solid State Technology, pp. 139-144, April, 1990.

4 . L. Niinistö, et. al., “Advanced Electronic and Optoelectronic Materials by Atomic Layer Deposition: An Overview with Special Emphasis on Recent Progress in Processing of High-k Dielectrics and Other Oxide Materials,” Physica Status Solidi (a), 201, p. 1443–1452, 2004

5. E. Granneman, et al., Batch ALD: Characteristics, Comparison with Single-wafer ALD, and Examples, Surface and Coatings Technology, Vol. 201, p. 8899 – 8907, 2007.

6 . A. Kobayashi, et al., Temperature Dependence of GPC with PEALD-SiO,” Proc. 10th Inter. Conf. on Atomic Layer Deposition, p. 31, 2010.

Biographies

Mohith Verghese earned a BS in chemical engineering from the U. of Texas at Austin and a MS in chemical engineering from the U. of Arizona. He is technical product manager of ALD technologies at ASM America, Phoenix, AZ, USA; ph: +1-602-470-2736, email:  [email protected]

Jan Willem Maes received his PhD in applied physics from Delft U. of Technology and works at ASM Belgium on ALD and EPI process application development projects.

Nobuyoshi Kobayashi earned a BS, a MS, and a PhD in solid state physics from the U. of Tokyo. He is director of PECVD and PEALD technologies at ASM Japan, Tama in Tokyo.

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