Category Archives: Resource Guide

Today, SEMI announced that 19 new fabs and lines are forecasted to begin construction in 2016 and 2017, according to the latest update of the SEMI World Fab Forecast report. While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Fab equipment spending ─ including new, secondary, and in-house ─ was down 2 percent in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to US$36 billion in 2016, 1.5 percent over 2015, and to $40.7 billion in 2017, up 13 percent. Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60 percent or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year. The SEMI World Fab Forecast report, published May 31, 2016, provides more details about the construction boom.

new fab lines

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition to announced and planned new fabs and lines, SEMI’s World Fab Forecast provides information about existing fabs and lines with associated construction spending, e.g. when a cleanroom is converted to a larger wafer size or a different product type.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

For insight into semiconductor manufacturing in 2016 and 2017 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

ClassOne Technology, manufacturer of budget-friendly wet processing equipment, is reporting significant savings in the plating of gold in ≤200mm applications using its Solstice systems. The savings come from elimination of gold waste, faster and simpler processing, and innovative Solstice-enabled techniques that can substantially reduce gold usage.

“Many users have been spending millions of dollars on gold each year,” said Byron Exarcos, President of ClassOne Group. “It’s a major issue, especially in emerging markets such as lasers, LEDs, RF and MEMS which often require gold layers as thick as 3 to 35 microns. “That’s why they’re becoming keenly interested in Solstice to cut their gold spending.”

“One fundamental advantage of Solstice electroplating is its elimination of gold waste,” explained Kevin Witt, President of ClassOne Technology. “Previously used CVD and PVD methods deposited gold not just on the wafer but also on the entire chamber interior. That ‘oversprayed’ gold was difficult to remove and inefficient to reclaim — which led to a considerable net loss of gold. By contrast, Solstice deposits only on the wafer, so there’s no gold waste, and no need for cleaning or gold reclamation efforts.”

Witt pointed out that Solstice economies also come from its higher gold deposition speed. Plating at 150 to 300nm/min, it is roughly ten times faster than CVD and PVD methods. In addition, Solstice starts processing immediately, not requiring an hour or more for pump-down as vacuum-based tools do. All of this translates to additional savings, from higher throughput and more cost-efficient production.

Innovative Solstice layering technique can cut gold usage dramatically

The unique 8-chamber design of the Solstice S8 enables it to readily replace a solid gold layer with a multi-metal stack — and reduce gold usage very substantially.

For example, a feature that previously required a 5µm layer of solid gold can now be replaced with a “sandwich” of 0.25µm Au, 1µm Ni, 2.5µm Cu, another 1µm Ni, topped with 0.25µm Au — to achieve equivalent functionality while reducing gold usage by a factor of ten! And Solstice’s multi-chamber design enables it to deposit all five layers in a single cycle; so no additional process steps or time are required to gain very significant cost savings.

ClassOne noted that over a year, total gold savings can grow quite large. For example, in the case cited above, if the solid gold 5µm layer covers 50% of a 150mm wafer area, and if the fab is running 1500 wafers per week through a metal lift-off process and gold costs $1200 per troy ounce — even if all oversprayed gold were recovered, the user’s annual gold expenditure would be roughly $2,150,000. However, if the special Solstice multi-metal layering technique were used, the total metal cost (for Au, Ni and Cu combined) would be reduced to approximately $108,000. This would yield an annual savings of over $2,042,000, which would more than pay back the cost of a Solstice.

The Solstice S8 provides eight modular chamber positions that can be used for plating a wide range of metals as well as performing additional processes. Solstice tools are available in three different models for production and development, and they serve many cost-sensitive emerging markets that use 200mm and smaller wafers. The systems are priced at less than half of what similarly configured plating systems from the larger manufacturers would cost — which is why Solstice has been described as “Advanced Plating for the Rest of Us.”

On May 19th, NXP Semiconductors N.V. announced Busch Semiconductor Vacuum Group LLC as the Best Supplier for Front-end equipment (semiconductor equipment) at NXP’s first Supplier Day Awards ceremony in Austin, Texas. The inaugural award ceremony’s theme was ‘Partnering for Growth’. Eighty key suppliers in attendance represented all areas of the industry from materials and equipment to sub-con and indirect services.

This award is an example of how Busch and its employees focus their activities and efforts into the customer, and the recognition centers on the Busch Family’s seven keys of success business driving philosophy, including “continuous improvement and drive.”

This is evident to NXP as their President and CEO, Rick Clemmer, acknowledged, “We know that partnering with the right suppliers is a crucial element that allows us to better execute on our growth strategy.” Busch is honored and proud to be recognized by one of their partners in the semiconductor industry, NXP Semiconductors.

Ultratech, Inc., a supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high­brightness LEDs (HB­ LEDs), as well as atomic layer deposition (ALD) systems, announced the formation of a research collaboration with Professor Thomas J. Webster, Ph.D. at Northeastern University, to study the use of nano-materials produced via ALD for medical applications. The initial research has focused on inhibiting bacterial growth and inflammation and promoting cell and tissue growth.

Dr. Thomas Webster, Chair and Professor of Chemical Engineering at Northeastern, said, “We are very excited to embark on this collaboration with Ultratech-CNT. While we are in the early stages of this study, the initial results of our work suggest that the materials and processes we are developing could have long-range impact in this field.”

Ultratech-CNT Senior Research Scientist Ritwik Bhatia, Ph.D., who has been working closely with Professor Webster, explained, “This type of work is a marked departure from the traditional applications and uses for ALD and dramatically opens up a new field where material science and life sciences intersect. I am extremely pleased to be part of this research program and excited by the potential benefits for healthy surgical outcomes that this research represents.”

Arthur W. Zafiropoulo, Ultratech’s Chairman and Chief Executive Officer, said, “At Ultratech, we have long maintained and understood that material science would play a key role in moving many emerging technological fields forward. We also feel that it can serve a much larger role, namely in improving the quality of life. In linking the expertise of Prof. Webster and his research group with Ultratech-CNT’s ALD group, we believe we are taking steps to solidly and efficiently pursue our scientific and commercial goals.”

Worldwide silicon wafer area shipments increased during the first quarter 2016 when compared to fourth quarter 2015 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,538 million square inches during the most recent quarter, a 1.3 percent increase from the 2,504 million square inches shipped during the previous quarter. However, new quarterly total area shipments are 3.8 percent lower than first quarter 2015 shipments.

“After two quarters of negative silicon shipment volume growth, the increase in silicon volume shipments in the most recent quarter is encouraging,” said Dr. Volker Braetsch, chairman SEMI SMG and senior vice president of Siltronic AG. “It remains to be seen if silicon shipment volumes will exceed the record amount shipped last year.”

Quarterly Silicon* Area Shipment Trends

Millions of Square Inches

1Q-2015

4Q-2015

1Q-2016
Total

2,637

2,504

2,538

Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

By Debra Vogler, SEMI

The semiconductor industry is nothing if not persistent — it’s been working away at developing extreme ultraviolet lithography (EUVL) for many years. Though its production insertion target has slipped over the years, some say that the industry is getting closer to its introduction at the 5nm node. But it’s also true that some may be hedging their bets.

Whatever camp you fall into, the discussion is sure to be lively as a team of experts tackles the status of advanced lithography options that can get the industry from node 10 to node 5 (session “Lithography: Charting a Path, or Paths, between Nodes 10 and 5”, part of the Advanced Manufacturing Forum) at SEMICON West 2016 (July 12, 10:30am-12:30pm). Confirmed speakers for this event include Robert Aitken (ARM), Stephen Renwick (Nikon Research Corporation of America), Ben Rathsack (TEL), Mike Lercel (ASML), Mark Slezak (JSR Micro, Inc.), and Harry Levinson (GLOBALFOUNDRIES). The session will be moderated by Lithoguru’s Chris Mack. SEMI interviewed some of the session speakers to get a preview of the issues most likely to be addressed.

Equipment status

Mike Lercel, director of product marketing at ASML, told SEMI that his company is very confident that EUVL will be ready for next-generation nodes, having demonstrated progress on the NXE:3350B, which is intended for volume production: achieving 1,368 wafers per day at the ASML factory, and excellent imaging and overlay performance at >80W. He further noted that the company’s logic customers will take EUV into production in 2018-2019, so it needs to ship in volume a year before — likewise for DRAM. “We believe that EUV is cost-competitive around 1,500 good wafers per day, but the crossover point may be lower depending on the customer and the application.”

Having already achieved the productivity milestone of 1,368 wafers per day makes EUVL cost-competitive or break-even for many applications, said Lercel, primarily because multiple patterning is becoming too difficult and EUV is needed to reduce this complexity. “Additionally, we’ve exposed more than 300,000 wafers on multiple NXE:3300 scanners at customer sites and that has accelerated our rates of learning. A 125W EUV source setting has been qualified and is ready for field rollout, and we demonstrated 200W source power at ASML.” He also noted that the company has a robust EUVL product roadmap, including a high-NA EUV scanner, which will take it into the next decade and beyond. “As long as the industry continues to scale and we are not close to reaching devices’ physical limits, there will be a need for EUV.”

Lercel acknowledged that EUVL productivity must continue to be improved and throughput is closely connected to source power and tool reliability. “We’ve derived new understandings from plasma modeling and computational lithography that have enabled us to significantly increase our conversion efficiency,” said Lercel. “This was a key contributing factor in our latest 200W achievement and builds confidence in our ability to reach 250W by the end of the year, which is the source power required for 1,500 wafers per day.”

Materials and infrastructure for EUVL

There are still a number of challenges remaining for the infrastructure needed to support EUVL. Among them are actinic inspections for blanks and resists. “Deposition tools and post-pellicle mask inspection must catch up to support EUVL,” said Lercel, who told SEMI that notable progress has already been made on E-beam mask inspection high-volume manufacturing (HVM) tools and on an actinic blank inspection tool development program led by the EUVL Infrastructure Development Center (EIDEC).

In other developments reported by Lercel, Zeiss is working on an AIMS tool for defect disposition; and at imec’s EUV Resist Manufacturing & Qualification Center (EUV RMQC), the industry-wide manufacturing infrastructure and quality control capabilities needed to take EUVL into HVM are being finalized. Other R&D efforts are continuing to improve EUV blank quality process and yield — defects are now reaching single digits said Lercel. ASML is also in the process of commercializing a pellicle. Significant gaps still exist with respect to a blank multi-layer deposition tool that needs to have improved defect results. “Multiple deposition techniques are being evaluated to define the HVM tool approach,” said Lercel. “And post-pellicle mask inspection (APMI) is not on timeline for insertion,” so the industry needs other options.

Regarding EUVL resists, Mark Slezak, executive vice-president, at JSR Micro, Inc., told SEMI that short-term, the materials industry is continuing to evolve and improve chemically amplified systems that are allowing technical requirements to be met at 7nm (see Figure 1 for examples of recent performance data). “Longer term, the industry is focused on new alternative approaches to chemically amplified systems with a variety of techniques, including molecular resists, nano-particles, and advanced sensitizers,” said Slezak, who will also present at SEMICON West 2016. “Additionally, in the case of both 193i and EUV, the material industry is working on post-development solutions, such as chemical shrink, pattern collapse mitigation, and combinations with DSA (directed self-assembly) that enable further imaging extensions.”

Figure 1: Examples of recent progress in patterning materials. Source: ASML, PSI, and imec

Figure 1: Examples of recent progress in patterning materials.
Source: ASML, PSI, and imec

As a company, JSR Micro is preparing to provide scaled-up EUV materials in a HVM setting, including advanced quality control, as early as the end of 2016, Slezak told SEMI. “However, we see that the most likely insertion point for significant volumes is in the 2018 time period.”

Overall outlook

Chris Mack summed up the industry’s current dilemma with respect to EUVL and getting from node 10 to node 5. “The whole idea of continuing on the Moore’s Law progression is to reduce the cost of a transistor by shrinking it,” Mack told SEMI. “We’ve seen a flattening of the cost/transistor trends over time lately, and I think there are some serious questions as to whether or not any specific new technology node from 10nm on will actually result in a lower cost/transistor — and if it doesn’t, there won’t be much motivation for designs to migrate to these nodes.”

Mack further observed that the cost of lithography already accounts for more than 50% of the cost of making a chip, and possibly even as high as 70% depending on the design. “As those costs escalate with each node, we worry that the cost savings won’t be enough to compensate for the higher design costs.” Citing conventional wisdom, Mack noted that the rule-of-thumb with respect to the break-even point for deciding to use EUVL is that it has to be able to cost-effectively replace three 193nm immersion steps (or masks). While there are a lot of assumptions that go into the cost-of-ownership models, Mack explained that if throughput levels can get to around 60-90wph, that would make one EUV layer cost-competitive with three 193nm immersion exposures. “I think most people agree that EUV would then be worthwhile to do. The hope is to be able to do that at the 5nm node.”

Aside from the actual technical challenges that remain to be solved before EUVL can be inserted into HVM, the major hurdle is time. “People are planning the 7nm logic node right now,” said Mack, “and no one is willing to commit to EUV for 7nm because it’s not ready.” He further explained that TSMC has said publicly it plans to exercise EUV in parallel with 193i manufacturing for the 7nm node and then implement EUV in manufacturing at the 5nm node. That would place it at around the 2020 time frame. “If EUV hits its schedule between now and 2018/2019, then we may see TSMC commit to using EUV at 5nm.” Conversely, if the EUV schedule slips and is still too risky to implement, then when 2019 comes around, it could very well be that EUVL will be pushed out even further. “Because foundries have to accept design rules about two years before manufacturing begins, and because the design rules for multiple-patterning 193 immersion are very different from single-patterning EUV, TSMC and other foundries will have to make their call about two years from now.”

For DRAM, Mack says there is still a desire for EUV to be successful, but the window is rapidly disappearing. “We might see more chip stacking as a solution going forward for DRAM,” said Mack, but “then we could see 193nm immersion SADP (single immersion double-patterning) for 20nm DRAM.” Below 20nm DRAM, If EUV isn’t ready, Mack says that chip stacking would be the solution, which leaves EUV for logic, primarily at 5nm.

“Here’s where an interesting phenomenon happens,” Mack told SEMI. “The classic view of Moore’s Law — a doubling of the number of components on a chip every two years — has been carrying on for over 50 years. Current trends are redefining the meaning of Moore’s Law (see Figure 2).”

The industry is seeing a slow-down in, i.e., 3-year cycles instead of 2-year cycles. “If that trend continues and EUV is late, that would give some breathing room for EUV to catch up. So it might be ready in time for the 5nm node.”

Figure 2: Moore’s Law trend. Courtesy: Chris Mack

Figure 2: Moore’s Law trend. Courtesy: Chris Mack

These speakers and more will present at SEMICON West 2016 (July 12-14) in San Francisco, Calif. The new SEMICON West offers eight forums: Extended Supply Chain, Advanced Manufacturing Chain Forum, Advanced Packaging Forum, Test Forum, Sustainable Manufacturing Forum, Silicon Innovation Forum, Flexible Hybrid Electronics Forum, and World of IoT Forum. Register before June 3 and save $50.

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $26.1 billion for the month of March 2016, a slight increase of 0.3 percent compared to the previous month’s total of $26.0 billion. Sales from the first quarter of 2016 were $78.3 billion, down 5.5 percent compared to the previous quarter and 5.8 lower than the first quarter of 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales increased in March for the first time in five months, but soft demand, market cyclicality, and macroeconomic conditions continue to impede more robust growth,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Q1 sales lagged behind last quarter across nearly all regional markets, with the Americas showing the sharpest decline.”

Regionally, month-to-month sales increased in Japan (4.8 percent), Asia Pacific/All Other (2.3 percent), and Europe (0.1 percent), but fell in China (-1.1 percent) and the Americas (-2.8 percent). Compared to the same month last year, sales in March increased in Japan (1.8 percent) and China (1.3 percent), but decreased in Asia Pacific/All Other (-6.4 percent), Europe (-9.8 percent), and the Americas (-15.8 percent).

“Eighty-three percent of U.S. semiconductor industry sales are into markets outside the U.S., so access to overseas markets is imperative to the long-term strength of our industry,” Neuffer said. “The Trans-Pacific Partnership (TPP) is a landmark trade agreement that would tear down myriad barriers to trade with countries in the Asia-Pacific. The TPP is good for the semiconductor industry, the tech sector, the American economy, and the global economy. Congress should approve it.”

March 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.03

4.89

-2.8%

Europe

2.66

2.67

0.1%

Japan

2.47

2.59

4.8%

China

8.02

7.93

-1.1%

Asia Pacific/All Other

7.83

8.01

2.3%

Total

26.02

26.09

0.3%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.81

4.89

-15.8%

Europe

2.96

2.67

-9.8%

Japan

2.55

2.59

1.8%

China

7.83

7.93

1.3%

Asia Pacific/All Other

8.57

8.01

-6.4%

Total

27.70

26.09

-5.8%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

5.75

4.89

-15.0%

Europe

2.77

2.67

-3.6%

Japan

2.57

2.59

0.8%

China

8.45

7.93

-6.1%

Asia Pacific/All Other

8.08

8.01

-0.8%

Total

27.62

26.09

-5.5%
Year-to-year percent change in world semiconductor revenues over the past 20 years.

Year-to-year percent change in world semiconductor revenues over the past 20 years.

North America-based manufacturers of semiconductor equipment posted $1.38 billion in orders worldwide in March 2016 (three-month average basis) and a book-to-bill ratio of 1.15, according to the March Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.15 means that $115 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in March 2016 was $1.38 billion. The bookings figure is 9.4 percent higher than the final February 2016 level of $1.26 billion, and is 0.9 percent lower than the March 2015 order level of $1.39 billion.

The three-month average of worldwide billings in March 2016 was $1.20 billion. The billings figure is 0.5 percent lower than the final February 2016 level of $1.20 billion, and is 5.3 percent lower than the March 2015 billings level of $1.27 billion.

“Order activity remains steady and is on par with both the previous quarter and one year ago,” said Denny McGuirk, president and CEO of SEMI. “3D NAND and advanced logic are the key drivers for investments.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
October 2015

$1,358.6

$1,325.6

0.98
November 2015

$1,288.3

$1,236.6

0.96
December 2015

$1,349.9

$1,343.5

1.00
January 2016

$1,221.2

$1,310.9

1.07
February 2016 (final)

$1,204.4

$1,262.0

1.05
March 2016 (prelim)

$1,198.5

$1,380.5

1.15

Source: SEMI (www.semi.org), April 2016

Celebrating its 70th anniversary, Brooks Instrument will be exhibiting at SEMICON West 2016 with new mass flow controllers (MFC) equipped with the high-speed EtherCAT interface, along with a broad range of other mass flow meters, controllers, vaporizers and capacitance manometers for semiconductor manufacturing.

The show runs July 12-14 at the Moscone Center in San Francisco. Brooks Instrument will be located in the South Hall at booth 1323.

A world leader in advanced flow, pressure, vacuum and vapor delivery solutions, Brooks Instrument will showcase key components in its MFC portfolio designed to meet critical gas chemistry control challenges and improve process yields for sub-20nm nodes. This includes the company’s newly enhanced GF100 Series MFCs with high-speed EtherCAT connectivity, as well as the GF135 advanced diagnostic MFC. Information on other pressure-based flow control technologies will also be available.

With its 70-year history in leading technology development, Brooks Instrument is focused on improving the precision and performance of mass flow, pressure and vacuum technologies to help enable advanced semiconductor manufacturing. Key items at SEMICON West include:

GF100 Series MFC with High-Speed EtherCAT Connectivity: Brooks Instrument has enhanced its industry-leading GF100 Series MFCs with high-speed EtherCAT interfaces for both high-flow and low-flow applications.

Responding to rapidly evolving requirements for next-generation tools and fabs, the GF100 Series features several additions to help boost process yields and productivity:

  • Embedded diagnostics to leverage real-time EtherCAT data acquisition capabilities for advanced fault detection and classification;
  • An ultra-stable flow sensor (less than 0.15 percent of S.P. drift per year) enables tighter low set point accuracy and reduces maintenance requirements;
  • Improved valve shutdown reduces valve leak-by, minimizing potential first wafer effects;
  • Enhancements to the GF100 advanced pressure transient insensitivity to less than one percent of S.P. with five PSI per second pressure perturbations, which reduces crosstalk sensitivity for consistent mass flow delivery.

GF135 Advanced Self-Diagnostic PTI MFC: The GF135 is the first “smart” pressure transient insensitive (PTI) MFC that can perform self-diagnostics such as integral rate-of-decay flow measurement without stopping the flow of process gas. This provides a competitive advantage, allowing semiconductor manufacturers to verify process gas accuracy, check valve leak-by, and monitor sensor stability in real time without removing the flow controller from the gas line – saving thousands of dollars in lost productivity.

With this unique real-time error detection technology, process and equipment engineers can reduce wafer scrap and lost production time from unacceptable flow deviations and unnecessary preventative maintenance checks. The Brooks Instrument GF135 PTI MFC also offers industry leading actual process gas accuracy and fast flow settling time for ascending and descending set points, helping to improve productivity and chamber-to-chamber matching.

Interactive Demonstration: The Brooks Instrument booth will include an interactive mass flow control demonstration where attendees can watch real-time gas flow error detection and advanced diagnostics on the GF135 MFC. Applications engineers will also be available to answer questions about the latest technologies to enhance process control, improve chamber matching and support process yield programs for semiconductor manufacturing. In addition, attendees are encouraged to visit the company in booth 1323 to share in its 70th anniversary celebration.

Samco, a Japan-based semiconductor process equipment developer and manufacturer, is employing around 20 more people at its locations in North America, China, Taiwan and Singapore, as well as its subsidiary Samco-UCP in Liechtenstein, in order to better provide services and support to overseas customers.

“Increasing the number of Samco employees abroad is part of the company’s larger strategy to optimize our current sales structure while actively growing our customer base across the globe,” says Osamu Tsuji, Samco’s President, Chairman and CEO.

Samco offers systems and services that revolve around three major technologies, namely thin film deposition with PECVD, MOCVD and ALD systems; microfabrication with ICP etching, RIE and DRIE systems; and surface treatment with plasma cleaning and UV ozone cleaning systems.

“We’ve seen an increase in laser diode, MEMS and power device-related inquiries from abroad,” says Tsuji. “Systems for research and development at universities and research institutions, which is an area Samco specializes in, are also in high demand.”

This includes India, where the growing economy is expected to accelerate in the future. The Indian Institute of Technology Bombay recently installed one of Samco’s DRIE systems and collaborated with Samco to host the company’s first thin-film technology workshop in the country.

Samco is currently considering offering internships to students at IIT Bombay and has started gathering a team that will focus on cultivating the Indian market, Tsuji adds.

Future goals include doubling its on-site staff by July 2018, discussing the possibility of new locations in the future, and ensuring its overseas sales encompass at least 50% of the company’s total net sales within the next two or three years.

“Semiconductor equipment manufacturers’ overseas sales generally account for around 70 or 80 percent of their total net sales,” Tsuji says. “Samco has great potential for growth in the future. With these markets, we’ll actively expand and reach our goal of at least 10 billion yen in total net sales.”