Category Archives: Semicon

For the first time ever, SEMICON Southeast Asia (SEMICON SEA), the region’s premier gathering of the industry connecting people, products, technologies and solutions across the electronics manufacturing supply chain, will be held in Kuala Lumpur. Taking place 8 to 10 May 2018, the conference will debut in the newly constructed Malaysia International Trade and Exhibition Centre (MITEC). With more than 85 percent of the exhibition space already sold, SEMICON SEA 2018 will represent companies from Southeast Asia, China, Taiwan, Europe and the U.S.  More than 300 companies will exhibit and as many as 8,000 visitors from 15 countries are expected to participate in SEMICON SEA. Organised by SEMI, SEMICON SEA 2018 theme will be “Think Smart Make Smart.”

The Southeast Asia region is a world-class electronics manufacturing hub with end-to-end R&D capabilities, and SEMICON SEA 2018 is the comprehensive platform for the electronics industry in the region. The event will feature three themed pavilions, five country pavilions, keynote presentations, and forums that will address critical trending topics within the semiconductor eco-system. The show will connect decision makers from the industry, demonstrate the most advanced products, and provide the most up-to-date market and technology trends.

Ng Kai Fai, president of SEMI Southeast Asia says, “The growth of SEMICON Southeast Asia is attributed to the rapid expansion and robust growth of the Electrical & Electronics (E&E) sector across Southeast Asia, with companies emerging as world leaders in mobile, automotive, medical and Internet of Things (IoT) supply chains. As one of the high-growth markets in the region, Malaysia contributes 44 percent of the total manufacturing output and 26 percent of the total Gross Domestic Product of the region and is forecasted to generate approximately US$ 382 billion in exports in 2018.”

Over the past three years, SEMICON SEA has become the annual gathering of the full regional supply chain. SEMICON SEA 2018 will feature a supplier search programme to encourage cross-border business matching as well as a technology start-up platform which will bring together Southeast Asia technology entrepreneurial resources. In conjunction with SEMICON SEA 2018, this event will also include the SEMICON University Programme which aims to encourage and promote STEM (Science, Technology, Engineering, and Mathematics) interest amongst young talent and will also include a job fair.

ASM International introduced the Intrepid® ESTM 300mm epitaxy (epi) tool for advanced-node CMOS logic and memory high-volume production applications. Intrepid ES introduces innovative closed loop reactor control technology that enables optimal within wafer and wafer-to-wafer process performance, critical for today’s advanced transistors and memories. Furthermore, Intrepid ES reduces the cost per wafer significantly for a 7nm epi process compared with prior node processes. The new tool has been qualified for production at a leading-edge foundry customer, and is targeting production applications in other industry segments as well. To date, over 40 reactors have been delivered.

“Over the past several years, multiple customers have been very clear that there is a need to address several technical and cost challenges in the epi market,” said Chuck del Prado, President and Chief Executive Officer of ASM International. “Intrepid ES is the result of a focused development program to address major challenges in this market, including film non-uniformity, process repeatability, tool uptime and high cost per wafer. This early success of the Intrepid ES clearly demonstrates that we are on track in addressing our customers’ emerging epi requirements.”

The new Intrepid ES tool is based on a combination of reactor and platform design improvements. It demonstrates improved film performance and enhanced reactor stability. Fundamental to its technology is an isothermal reactor environment in which the wafer is processed. This provides consistent and repeatable temperature control across the wafer and wafer-to-wafer.

By Ed Korczynski

Veeco Instruments (Veeco) recently announced that Veeco CNT—formerly known as Ultratech/Cambridge Nanotech—shipped its 500th Atomic Layer Deposition (ALD) system to the North Carolina State University. The Veeco CNT Fiji G2 ALD system will enable the University to perform research for next-generation electronic devices including wearables and sensors. Veeco announced the overall acquisition of Ultratech on May 26 of this year. Executive technologists from Veeco discussed the evolution of ALD technology with Solid State Technology in an exclusive interview just prior to SEMICON West 2017.

Professor Roy Gordon from Harvard University been famous for decades as an innovator in the science of thin-film depositions, and people from his group were part of the founding of Cambridge Nanotech in 2003. Continuity from the original team has been maintained throughout the acquisitions, such that Veeco inherited a lot of process know-how along with the hardware technologies. “Cambridge Nanotech has had a broad history of working with ALD technology,” said Ganesh Sandaren, VP of Veeco CNT Applied Technology, “and that’s been a big advantage for us in working with some major researchers who really appreciate what we’re providing.”

The Figure shows that the company’s ALD chambers have evolved over time from simple single-wafer thermal ALD, to single-wafer plasma-enhance ALD (PEALD), to a large chamber targeting batch processing of up to ten 370 mm x 470 mm (Gen2.5) flat-panels for display applications, and a “large area” chamber capable of 1m x 1.2m substrates for photovoltaic and FPD applications. The large area chamber allows customers to do things like put down an encapsulating layer or an active layer such as buffer materials on CIGS-based solar cells.

Evolution of Atomic-Layer Deposition (ALD) technology starts with single-wafer thermal chambers, adds plasma energy, and then goes to batch processing for manufacturing. (Source: Veeco CNT).

Evolution of Atomic-Layer Deposition (ALD) technology starts with single-wafer thermal chambers, adds plasma energy, and then goes to batch processing for manufacturing. (Source: Veeco CNT).

“There a tendency to think that ALD only belongs in the high-k dielectric application for semiconductor devices, but there are many ongoing applications outside of IC fabs,” reminded Gerry Blumenstock, VP and GM of MBE business unit and Veeco CNT. “Customers who want to do heterogeneous materials develop can now have MBE and ALD in a single tool connected by a vacuum cluster configuration. We have customers today that do not want to break vacuum between processes.” Veeco’s MBE tools are mostly used for R&D, but are also reportedly used for HVM of laser chips.

To date, Cambridge Nanotech tools are generally used by R&D labs, but Veeco is open to the possibility of creating tools for High-Volume Manufacturing (HVM) if customers call for them. “Now that this is part of Veeco, we have the service infrastructure to be able to support end-users in high-volume manufacturing like any of the major OEMs,” said Blumenstock. “It’s an interesting future possibility, but in the next six months to a year we’re focusing on improving our offering to the R&D community. Still, we’re staying close to HVM because if a real opportunity arose there’s no reason we couldn’t get into it.”

In IC fab R&D today, some of the most challenging depositions are of Self-Assembled Monolayers (SAM) that are needed as part of the process-flow to enable Direct Self-Assembly (DSA) of patterns to extend optical lithography to the finest possible device features. SAM are typically created using ALD-type processes, and can also be used to enable selective ALD of more than a monolayer. Veeco-CNT is actively working on SAM in R&D with multiple customers now, and claim that major IC device manufacturers have purchased tools.

At the leading edge of materials R&D, researchers are always experimenting with new chemical precursors. “Having a precursor that has good vapor-pressure, and is reactive yet somewhat stable is what is needed,” reminded Sundaram. “People will generally chose a liquid over a solid precursor because of higher vapor pressure. There are many classes of precursors, and many are halogens but they have disadvantages in some reactions. So we see continue to move to metal-organic precursors, which tend to provide good vapor-pressures and not form undesirable byproducts.”

By Pete Singer

Semiconductor manufacturers use a variety of high global warming potential (GWP) gases to process wafers and to rapidly clean chemical vapor deposition (CVD) tool chambers. Processes use high GWP fluorinated compounds including perfluorocarbons (e.g., CF4, C2F6 and C3F8), hydrofluorocarbons (CHF3, CH3F and CH2F2), nitrogen trifluoride (NF3) and sulfur hexafluoride (SF6). Semiconductor manufacturing processes also use fluorinated heat transfer fluids and nitrous oxide (N2O).

Of these, the semiconductor industry naturally tends to focus its attention on CF4 since it is one of the worst offenders, with an atmospheric half-life of 50,000 years. “CF4 the hardest to get rid of and it’s one of the worst global warming gases,” said Kate Wilson, VP Marketing, Subfab Solutions – Semiconductor Division of Edwards. “We tend to use that as an indicator of how much of the other global warming gases, as well, are being emitted by the industry. If we’re dealing with that (CF4) well, we tend to be managing the rest of the gases pretty effectively.”

According to the Environmental Protection Agency (EPA), estimating fluorinated GHG emissions from semiconductor manufacture is complicated and has required a significant and coordinated effort by the industry and governments. It was historically assumed that the majority of these chemicals were consumed or transformed in the manufacturing process. It is now known that under normal operating conditions, anywhere between 10 to 80 percent of the fluorinated GHGs pass through the manufacturing tool chambers unreacted and are released into the air.

In addition, fluorinated GHG emissions vary depending on a number of factors, including gas used, type/brand of equipment used, company-specific process parameters, number of fluorinated GHG-using steps in a production process, generation of fluorinated GHG by-product chemicals, and whether appropriate abatement equipment has been installed. Companies’ product types, manufacturing processes and emissions also vary widely across semiconductor fabs.

The good news is that many companies in the semiconductor manufacturing industry have successfully identified, evaluated and implemented a variety of technologies that protect the climate and improved production efficiencies. Solutions have been investigated and successfully implemented in the following key technological areas:

  • Process improvements/source reduction
  • Alternative chemicals
  • Capture and beneficial reuse
  • Destruction technologies (known as abatement)

In 2011 the industry set new targets for 2020, which it summarizes as:

  • The implementation of best practices for new semiconductor fabs. The industry expects that the implementation of best practices will result in a normalized emission rate (NER) in 2020 of 0.22 kgCO2e/cm2, which is a 30 percent NER reduction from the 2010 aggregated baseline.
  • The addition of “Rest of World” fabs (fabs located outside the World Semiconductor Council (WSC) regions that are operated by a company from a WSC association) in reporting of emissions and the implementation of best practices for new fabs.
  • NER based measurement in kilograms of carbon equivalents per area of silicon wafers processed (kgCO2e/cm2), which will be the single WSC goal at the global level.

“We’re finding as we get down to the lower levels and different things come up as the highest priority in the fab where we’re moving into more and more lower usage processes, which are requiring abatement now in order to get those levels down to meet the targets of 2020 in the industry,” Wilson explained.

The main area for potential improvement now is etch, especially in older 200mm fabs where etch processes may not have been fitted with PFC abatement devices. This is particularly true for etch processes making extensive use of CF4. “The area where we still have the most gaps is clearly etch,” Wilson said. In CVD processes, most of the benefit was done by material shifts rather than actual abatement, although we clearly do need to abate the other gases in those processes. For the etch side, there are still quite a few customers that really only do the toxic emission abatement rather than the global warming gas emission abatement. But we do see, across almost all of our customer base, people have either fairly recently moved to fully abating all the PFC type gases or will be shortly.”

Wilson said some other gases have been coming up more recently in terms of things like N2O, which people are putting more focus on now as it’s becoming a larger part of the fab footprint of global warming materials.

For PFC abatement, Edwards offers the Atlas range of products, which destroys PFCs by burning them. This is followed by a wet scrub of the byproducts. This works quite well, but Wilson cautions that in can be tricky for some processes, such as chamber cleans with NF3. “If the burn is not correct and you get too hot, there’s actually the potential to create PFC’s. And so, it is quite critical to have well-controlled burn technology to make sure that you don’t actually cause issues where we didn’t have them before.”

Wilson said another area where they have seen some issues with PFCs being created is with processing of carbon-doped materials, such as low-k dielectrics. “When they do the chamber clean, they’re cleaning off predominately silicon dioxide but there’s carbon in there so that can create PFCs and CF4 as well so there’s a requirement to look at abatement in those areas,” she said.

Another piece of good news is that no company in the supply chain is waiting for legislation to be enacted before they act themselves. “Right from consumers to the consumer manufacturers, the car manufacturers, consumer electric manufacturers, our direct customers, the equipment manufacturers plus the major players within semiconductor and flat panel display, it seems that at every level there’s a commitment that this is the right thing to do,” Wilson said. “At every level people are pushing to get the requirements more stringent and it’s almost not about legislation anymore, it’s about everybody actually thinks it’s a good idea and they want to do it.”

Across all process areas in the fab effective abatement technologies reduce the GHG emissions significantly. The reductions per process area are shown in the diagram.

Across all process areas in the fab effective abatement technologies reduce the GHG emissions significantly. The reductions per process area are shown in the diagram.

By Lynnette Reese

On Wednesday, Intel Corporation’s Katherine Winter, Vice President of the Automated Driving Group, delivered a keynote that many would think is off-topic from the usual at SemiCon West: ”Big Data in Autonomous Driving.” She revealed that autonomous driving will shift the semiconductor industries’ focus to processing terra flops of data at blinding speeds with low latency. Winter stated, “A lot of the testing that’s going on today is to find what is the right level of MIPS to have the safest possible drive.” Winter addressed the need for computing power by the semiconductor industry to meet the challenges that autonomous driving for the passenger economy will pose. Intel, in working with Strategy Analytics, finds that the Passenger Economy may be worth $7 trillion by 2050. The largest factor holding this new business space back may very well be consumer acceptance.

The burden on semiconductor processors and supporting ICs will be driven part by data. Massive amounts of data will be driven by multiple sensors, “so that you, if you are riding in it, you trust that the vehicle knows what it’s doing…you want to know that it can handle snow and ice.” The sensors complement each other. “As we go through more and more testing, and there’s more of those vehicles out there, we are learning about the combinations, how much redundancy, things like that, that you actually need in the vehicle.” Emerging pedestrians, variable weather conditions, and myriad navigation issues from differing state regulations to undocumented construction and potholes also contribute to the need for data from differing variables aimed at every possibility.

Such enormous amounts of data come not only as technical data from sensors on the car and from infrastructure, but from crowd-sourced data as well as personal data for drivers and passengers. Crowd-sourced data might include reporting new obstacles or construction to be incorporated into the AV’s navigating knowledge. The autonomous learning cycle continues as cars upload data to the cloud, which shares and uses the data to train other vehicles on the new information. Personal data gathered from within the car includes information about the passengers which will be critical to the new passenger economy as AVs become the foundation for new markets for services formed for passengers within the vehicle. New applications like robo-taxis, managing fleets of delivery trucks, and crowd-sourcing data for navigation and finding parking are within reach.

Challenges translate to the semiconductor industry as we try and solve associated problems. How do we store and share the data? What do we do with the data, and what data is saved? Areas of focus in this developing economy will be the speed of critical information and processing workload. Security is also a critical part of the AV vision. Both privacy and overall resistance to cyberattacks are of genuine concern. “How do we keep it secure? How do we make sure that there’s not a way for cyberattacks once those vehicles are out there?” posed Winter. In short, how do we trust autonomous vehicles in every way?

As we get to thousands and millions of autonomous vehicles, we will also need to understand how many we want to manage at one time. At scale, we can share safety data, create standards, and even promote an industry platform. Winter acknowledged that the semiconductor industry is not new to challenges, but indicated that the landscape will change, “We think we know what the sensors are, we think we know that kind of data is generated, but we can’t imagine what we are going to know in two years based on the speed of acceleration that we have seen so far developing in this space.”

The “Passenger Economy,” a term coined by Intel CEO Brian Krzanich, is estimated at $7 trillion by 2050. (Source: Strategy Analytics).

The “Passenger Economy,” a term coined by Intel CEO Brian Krzanich, is estimated at $7 trillion by 2050. (Source: Strategy Analytics).

8:30 am –12:30 pm
Get Smart: SEMI/Gartner, Bulls & Bears Industry Outlook
Yerba Buena Theater

10:30 am – 12:30 pm
SMART Automotive
Meet the Expert Theater, Moscone West

10:30 am – 12:30 pm
The Economics of Choosing a Lithography Strategy
Moscone West, TechXPOT West

10:30 am –12:35 pm
5G Communications and the Next-generation Cloud
Moscone North, TechXPOT North

2:00 pm – 4:00 pm
The Economics of Density Scaling
Moscone West, TechXPOT West

2:00 pm – 4:00 pm
Exploring Electronics Requirements & Solutions for Medical Technology
Moscone North, TechXPOT North

By Ed Korczynski 

Global industry R&D hub IMEC defines the “IMEC 7nm-Node” (I7N) for finFETs to have 56nm Contacted Gate Pitch (CGP) with 40nm Metal Pitch (MP), and such critical mask layers can be patterned with a single exposure of 0.33 N.A. EUVL as provided by the ASML NXE:3400B tool. To reach IMEC 3nm-Node (I3N) patterning targets of ~40 CGP and ~24 MP, either double exposure of 0.33 N.A. EUVL would be needed or else single-exposure of 0.55 N.A. EUVL as promised by the next-generation ASML tool. All variations of EUVL require novel photoresists and anti-reflective coatings (ARC) to be able to achieve the desired patterning.

The Figure shows that IMEC has led tremendous progress on the photoresists, with best resolution in a single 0.33 N.A. EUVL exposure of 13nm half-pitch (HP) line arrays. The most important parameter for the photoresist is the sensitivity target of 20 mJ/cm2, but at that dosage the best materials seen today have unacceptably high line-width roughness of >5nm three-sigma.

“If you’re talking about lines of 16nm width, for 3-sigma you want to be less than 3nm line-width-roughness,” explained Steegen during the 2017 IMEC Technology Forum. “Smoothing techniques are post-develop technologies that basically reduce line-width-roughness. We are working with many partners, and all are making progress in reducing line-width roughness though post-develop techniques.”

Top-down SEM images of the best achieved EUVL resolutions using 0.33 N.A. stepper and Chemically-Amplified Resist (CAR) or metal-oxide Non-Chemically-Amplified Resist (NCAR) formulations, along with post-development “smoothing” technologies to improve the Line-Width Roughness (LWR) to meet target specifications. (Source: IMEC)

Top-down SEM images of the best achieved EUVL resolutions using 0.33 N.A. stepper and Chemically-Amplified Resist (CAR) or metal-oxide Non-Chemically-Amplified Resist (NCAR) formulations, along with post-development “smoothing” technologies to improve the Line-Width Roughness (LWR) to meet target specifications. (Source: IMEC)

The Figure also shows that IMEC has been working with vacuum deposition companies on atomic-layer deposition (ALD) or chemical-vapor deposition (CVD) processes to ideally take off 2 nm of sidewall roughness. Plasma energy may be capacitively- or inductively-coupled to a vacuum chamber to allow for either PEALD or PECVD processing. Such precise atomic-scale processing may be composed of “dep/etch” sequences of one/few atomic layer depositions followed by light plasma etching such that the nominal line-width would not necessarily change. However, this approach necessitates that the wafer leave the lithography track and move to a separate vacuum-tool.

To save on cost and time, LWR smoothing may be accomplished to some extent today in the litho track by specialized spin-on materials. Companies that supply lithography resolution extension (EXT) materials such as spin-on hard masks (SOHM) and anti-reflective coatings (ARC) have looked at ways spin-on materials can improve the LWR of post-developed resist lines. This can be combined with “shrink” materials that add controlled thicknesses to sidewalls of holes, or with “trim” materials that subtract controlled thicknesses from the sidewalls of lines. Generally, some manner of complex chemical engineering is used to create a film that either forms or breaks bonds when thermally driven by a bake step, and after image transfer to underlying SOHM layers the shrink/trim material is typically stripped in a solvent such as propylene glycol methyl ether acetate (PGMEA).

EUVL photoresists may be based on metal-oxide nano-particles, instead of on extensions to the Chemically-Amplified Resist (CAR) formulations that have been mainstays of ArF/ArFi lithography for decades. Inpria Corp.—the 10-year-old-start-up supported by industry—has ultimately developed a tin-oxide family of blends that are shown as the Non-Chemically-Amplified Resist (NCAR) in the Figure. NCAR metal-oxide resists show similar LWR at similar exposure doses to CARs. However, the metal-oxides in the NCAR can often replace SOHM materials, saving cost and complexity in the resist stack.

IMEC’s work on EUVL with ASML steppers leads to the belief that the source power will increase to allow throughput to rise from today’s ~100 wph to ~120 wph by the end of this year. However, those throughputs assume 20mJ/cm2 resist-speed, and masks may require 30 mJ/cm2 target exposures even with post-develop smoothing steps.

[DISCLOSURE: Ed Korczynski is also Sr. Technology Analyst with TECHCET Group, and author of the “Critical Materials Report: Photoresists and Extensions and Ancillaries 2017”.]

SEMI announced the recipients of the 2017 SEMI Awards for the Americas today. The awards honor: a team from Micron Technology (Micron) for the development of the hybrid memory cube and their leadership in co-founding the Hybrid Memory Cube Consortium, and Bryan Black from Advanced Micro Devices for integration of the “Fiji” 3D-IC graphics processor product. The awards were presented at SEMICON West 2017 today.

SEMI Awards recognize technology developments that have had a major impact on our industry and the world.  The 2017 award recipients share the distinction of having pioneered processes and integration breakthroughs that enabled the first high-volume production of 3D memory and the integration of 3D memory into the first high-volume production of 3D Systems-in-Package (SiP) products.

Use of the third dimension in 3D memory devices provides density and performance that are beyond the range of traditional 2D scaling.  Although efforts to use the third dimension have been ongoing for decades, the use of through-silicon-vias (TSVs) was critical to creating the technology foundation on which current devices are based. The work of Warren Farnworth and Salman Akram at Micron was essential to enabling the development of the “hybrid memory cube.” By 2011, Micron had developed the technology to the point where its technical potential was clear, but Scott Graham recognized that it would be a “niche product” ─ unless a community of device manufacturers, developers, and adopters followed a common interface specification. Micron made a bold move, teaming up with a major competitor (Samsung), to co-found the Hybrid Memory Cube Consortium. The Consortium now has 100+ members working to innovate and expand the capabilities of the next generation of memory-based solutions. For developing the Hybrid Memory Cube technology and their leadership in the establishment of the Hybrid Memory Cube Consortium, SEMI is proud to present Warren Farnworth, Salman Akram, and Scott Graham of Micron with the 2017 SEMI Award. Tom Eby, VP of Micron’s Compute and Networking Business Unit, accepted the award for Micron.

Advanced Micro Devices (AMD) also recognized the importance of collaboration in 3D SiP devices. A decade ago, AMD realized that advanced graphics processing would require major innovation in multi-die integration and increases in processor-memory bandwidth. To meet this challenge, AMD began a 10-year development process with its memory partner, SK-Hynix, and the system integrator, ASE. Their process drove advances in multi-die memory stacking and software standards as well as addressing the crucial challenges of thermal management and “intelligent reliability” for components operating at the edge of their design envelope. In 2015, AMD introduced the “Fiji” graphics processor which was made possible by an aggressive prototyping sequence that produced over 15 distinct product designs and involved over 20 contributing companies. More importantly, the AMD-led project produced a number of industry firsts:  the use of die-stacked memory in a graphics processor, the use of a high-volume interposer package in a graphics product, the integration of 22 discrete die into a package shipping millions of parts, and collaboration across the supply chain. These innovations would not be possible without the leadership of AMD. SEMI is honored to present Bryan Black, a senior AMD Fellow at AMD Austin, with the 2017 SEMI Award for the integration of the “Fiji” 3D-IC graphics processor.

“Every year SEMI honors key technological contributions and industry leadership through the SEMI Award. This year’s recipients were each instrumental in delivering technologies that will influence product design and system architecture for many years to come. Congratulations to both Bryan from AMD and the Micron team for their significant accomplishments,” said David Anderson, president, SEMI Americas.

“Both of the 2017 Awards recognize the enabling of high-volume manufacturing through collaboration with key vendors in the supply chain at AMD and by establishing a collaboration with competitors as well as the supply chain at Micron. These breakthroughs through collaboration set an example for acceleration of innovation in the future,” said Bill Bottoms, chairman of the SEMI Awards Advisory Committee.

The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The award is the highest honor conferred by SEMI Americas. It is open to individuals or teams from industry or academia whose specific accomplishments have broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/semiaward.

SEMI honored four industry leaders for their outstanding accomplishments in developing Standards for the electronics and related industries. The SEMI Standards awards were announced at the SEMI International Standards reception held during SEMICON West 2017.

The SEMI International Standards Excellence Award, inspired by Karel Urbanek, is the most prestigious award in the SEMI International Standards Program. The 2017 recipient is Bert Planting (ASML) who has been active in SEMI Standards for more than a decade, without interruption, in numerous international safety standardization projects, including:

  • S10 (Safety Guideline for Risk Assessment and Risk Evaluation Process) since 2005
  • S27 (Safety Guideline for the Contents of Environmental, Safety, and Health (ESH) Evaluation Reports) since 2010
  • S2 (Environmental, Health, and Safety Guideline for Semiconductor Manufacturing Equipment)
  • S25 (Safety Guideline for Hydrogen Peroxide Storage and Handling Systems) since 2012

Planting has co-chaired the North American (NA) chapter of the EHS Technical Committee since 2013, and also currently leads the S10 Revision Task Force and the S2 Interlock Reliability Task Force. As leader of the S10 Revision Task Force, he significantly improved S10’s usefulness and practicality. Under his strong direction, the risk assessment methodology of S10 (and by reference, S2) is now more objective, easier to implement, and better harmonized with major international Standards for safety risk assessment. As co-chair of the European EHS Technical Committee from 2005–2013, he successfully led a major S10 revision as well as development of a new Safety Guideline.

The North American SEMI International Standards Merit Award recognizes major contributions to the SEMI International Standards Program.  Award winners typically take on a very complex problem at the task force level, gain industry support, and drive the project to completion. This year two people received the award:

  • Yanli “Joyce” Chen (UCT) reactivated the Pressure Measurements Task Force during the SEMICON West 2014 Standards Meetings. This task force was chartered to develop a series of standardized performance definitions and test methods related to pressure measurement devices used in the semiconductor industry. Previous attempts to develop a standard test method for pressure transducers in gas delivery systems were not successful, but Chen reenergized the Task Force, putting tremendous effort into test apparatus development, test procedure optimization, data collection, and test results analysis, and conducting an extensive pressure transducer side-by-side evaluation project. This provided a solid base for the development of the new Standard, and SEMI F113, Test Method for Pressure Transducers Used in Gas Delivery Systems was approved and published. Chen has also been instrumental in updating several test methods for mass flow controllers and other components with benefits to the entire semiconductor industry.
  • John Visty (Salus Engineering International) has been the leader of the S2 Chemical Exposure Task Force since 2008; he is also the Task Force leader for the S2 Non-ionization and the S6 (Exhaust Ventilation) Revision. Leading these Task Forces resulted in revisions of SEMI S2, the most recognizable SEMI standard. The industrial hygiene section (regarding chemical exposure) in SEMI S2 was in need of clarification to ensure consistent technical interpretation by equipment suppliers, end-users and third-party evaluators.  Visty drove development through multiple ballot attempts, incorporating feedback from unfavorable ballots to reach industry consensus. In March 2017, revisions to SEMI S2 related to chemical exposure were approved and incorporated into SEMI S2. This clarification benefits the semiconductor industry by providing consistent chemical conformance criteria.

The North American SEMI International Standards Leadership Award recognizes outstanding leadership in guiding the SEMI International Standards Program. Brian Rubow (Cimetrix) has been an important contributor to SEMI Standards for many years and has demonstrated ongoing and increasing leadership.  Rubow became leader of the North American Diagnostic Data Acquisition (DDA) Task Force in 2008, leader of the NA GEM300 Task Force in 2010, co-chair of the NA Chapter of the Information and Control Committee in 2013, and vice-chair of the NA Regional Standards Committee in 2014. He continues to serve in all four of these positions. Among other accomplishments, Rubow drove the development of two important advances to bring semiconductor factory automation into the world of modern networks:

  • SEMI E172, SECS Equipment Data Dictionary (SEDD), which allows factory automation systems to adapt to the individual capabilities of each equipment type
  • SEMI E173, SECS Message Notation (SMN), which allows the content of factory messages to be specified in modern XML notation.

Rubow’s technical knowledge of factory connectivity solutions and outstanding leadership skills make a major contribution to the SEMI International Standards program.

For more information about SEMI International Standards, visit www.semi.org/en/Standards.

Solid State Technology and SEMI today announced the recipient of the 2017 “Best of West” Award — Microtronic Inc.— for its EAGLEview 5. The award recognizes important product and technology developments in the electronics manufacturing supply chain. Held in conjunction with SEMICON West, the largest and most influential electronics manufacturing exposition in North America, the Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

Microtronic’s EAGLEview 5 Macro Defect Management Platform is the new, yield-enhancing, breakthrough macro defect inspection platform that was developed ─ and deployed in production ─ through collaboration with several leading device manufacturers who wanted to standardize and unify wafer defect management throughout their fab. Innovations include: dramatically improved defect detection; level-specific sorting; and integration with manual microscopes. (Process Control, Metrology and Test Category; North Hall Booth #5467)

EAGLEview 5