(November 2, 2010) — SEMI announced that Teradyne Inc. (NYSE:TER) has granted a worldwide royalty-free license of Standard Test Data Format (STDF), and any intellectual property rights, to SEMI to use, distribute, modify and support STDF. Under the supervision of SEMI International Standards, the license of STDF will ensure standards development and new products using STDF and future extensions will be unencumbered by IP ownership conflicts.

Advances in technology make it imperative to collect and diagnose detailed structural semiconductor test data during high-volume manufacturing to improve yield, test quality and overall test efficiency. However, multiple datalog formats and lack of industry standards prevent efficient use of test data across multiple test platforms and IC designs. This license represents an important milestone in the semiconductor test industry by enabling a more efficient, industry-wide application of STDF and future STDF extensions in the maintenance and development of test programs and other semiconductor test products. The demand for comprehensive datalog standards is greater than ever as IDMs, foundries, and outsourced test and assembly firms are looking to lower costs, improve test quality and speed implementation of test strategies across multiple test platforms and EDA vendors.

"This action will encourage increased participation in standards development activities from a broader section of the industry and enable broader adoption of STDF around the world," said Jonathan Davis, president of the Semiconductor Business Unit at SEMI. "This is an important milestone in industry collaboration for the semiconductor test industry. With Teradyne’s support, important and valuable international standards can now progress utilizing the well-regarded STDF solution."

The Collaborative Alliance for Semiconductor Test (CAST), a SEMI special interest group, formed a working group on SDTF in 2008 as a successor to a previously independent standards group. Through the group’s efforts, a new, standard extension for logging memory fails in STDF has been developed. The format is currently in ballot by SEMI International Standards for international adoption as an industry standard. The SEMI CAST working group on STDF, comprised of members from the ATE, EDA, OSAT and the IC industry, is currently evaluating continued development and enhancements of STDF.

"We are pleased to help enable this important milestone in the semiconductor test industry by designating SEMI as the primary body to oversee the enhancement and further adoption of STDF," said Greg Smith, Broadband and Computing Business Unit manager, of Teradyne. "SEMI and CAST working groups have a unique environment that allows all the participants in the Semiconductor Test ecosystem to further the efficiency of the entire manufacturing process. This action will better serve Teradyne, our customers and the entire semiconductor industry by allowing us to focus on innovation and customer service, and not unproductive duplication of effort."

Teradyne (NYSE:TER) supplies automatic test equipment used to test complex electronics used in the consumer electronics, automotive, computing, telecommunications, and aerospace and defense industries. For more information, visit www.teradyne.com.

SEMI is the global industry association serving the manufacturing supply chains for the microelectronic, display and photovoltaic industries. For more information, visit www.semi.org.

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(November 1, 2010) — Achronix Semiconductor Corp. announced strategic access to Intel Corporation’s 22nm process technology, and plans to develop the most advanced field programmable gate arrays (FPGAs).

The Achronix Speedster22i FPGA family targets cost-effective production for high performance devices over 2.5M LUTs in size, equivalent to an ASIC of over 20 million gates. Taking advantage of the performance and power savings of Intel’s 22nm process technology, Speedster22i will also extend the boundaries of FPGA speed and power efficiency, enabling as much as 300% higher performance, 50% lower power, and 40% lower cost than any other FPGA in any other process technology.

Achronix Speedster22i will be suitable for applications in the telecommunication, networking, industrial and consumer markets and will enable emerging applications such as 100G, 400G Ethernet networking and LTE mobile communications. Additionally, Speedster22i can be commercially manufactured in the US, suiting military and aerospace applications requiring "on shore" silicon.

"Intel’s manufacturing strengths and lead in process technology offers leadership cost, performance and power efficiency benefits, giving Intel and our manufacturing customers such as Achronix an opportunity to design products with superior capabilities,” said Sunit Rikhi, vice president, Technology and Manufacturing Group, Intel.

“Intel has the best process technology in the world and we are privileged to have formed this strategic relationship, which enables simultaneous improvements in speed, power, density and cost,” said John Lofton Holt, CEO of Achronix. “The combination of the advanced 22nm process from Intel and the advanced FPGA technology from Achronix enables Speedster22i to eclipse other FPGA solutions expected to hit the market in the next few years.”

Achronix Semiconductor is a privately held fabless corporation that builds field programmable gate arrays (FPGAs) capable of up to 1.5 GHz peak performance. Find out more at http://www.achronix.com.

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(October 26, 2010) — Semico presented an ASIC market update during a Xilinx-hosted event this week. Semico noted a low growth forecast for the traditional ASIC market, and programmable logic growth being driven by increasing requirement for bandwidth for portable connectivity. Presenter Richard Wawrzyniak’s discussion is summarized below.

ASIC design started to recover in 2010, growing again, but at lower levels than historic rates. Total ASIC market revenues for 2010 will be $13.1 billion, says Semico, reaching $18.2 billion in 2015, a 6.8% CAGR. Total programmable logic growth in 2010 is expected to be ~47.4%.

ASIC design starts declined 7.7% in 2009, recovering with 7.4% growth in 2010. Semico notes that designs are getting "long in the tooth," and SoCs are buoyed by derivative designs. Pent up demand for fresh silicon and new architectures will probably be unleashed in 2011. By 2015, the total SoC market will reach $87.7 billion, an 8.8% CAGR.

The SIP market recovered in 2010 and sees long term growth through 2015. CPU cores are the largest revenue segment with 14.1% CAGR. Logic is the second largest category, but with only a 5,9% CAGR. Analog IP has the highest CAGR at 20.9%. SIP subsystems are emerging as a new driver for IP, SoC and ASIC Design starts markets. New silicon functionality will become possible.

For more information, contact Richard Wawrzyniak, Semico, at [email protected]

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(October 25, 2010) — Mentor Graphics Corporation (NASDAQ: MENT) has announced its next-generation FloTHERM 3D computational fluid dynamics (CFD) software for electronics cooling applications. Called FloTHERM 9, the software provides bottleneck (Bn) and shortcut (Sc) fields so that engineers can identify where heat flow congestion occurs in the electronic design and why. It also identifies thermal shortcuts to resolve the design problem. Erich Bürgel, GM, Mechanical Analysis Division at Mentor Graphics, describes the process in a podcast interview.

Podcast: Download or Play Now

Together, the Bn (Figure 1) and the Sc (Figure 2) fields elevate the use of simulation from an observation tool that identifies heat management problems, to a thermal design problem-solving tool that suggests potential solutions to the designer. The Bn field shows where in a design the heat path is being congested as it attempts to flow from high junction temperature points to ambient. Design changes to these bottlenecks can help solve the heat flow problem. The Sc field highlights possible solutions where the addition of a simple element to the design will provide a new effective heat flow path to further cool the system. The end result is faster and more efficient resolution of heat management problems, Bürgel told ElectroIQ.

Two additional enhancements have been made in the new FloTHERM v.9 product: XML model and geometry data importing to enable FloTHERM integration into existing data flows, and a direct interface to the Mentor Graphics Expedition PCB design platform. The direct interface enables users to import native Expedition PCB data, and delete or edit additional objects (heatsinks, thermal vias, board cutouts, EM cans) for more accurate thermal model design development.

Commenting on the new product, “The value of FloTHERM 9 is in the time and the cost it saved us when developing an IC for a new generation of Energy Star-compliant mobile phone chargers,” stated Nigel Heather, VP, Engineering at CamSemi. “The baseline simulation using the bottleneck feature quickly highlighted a potential thermal issue, and further iterations confirmed our solution.” He added that, to achieve the same result by building prototype boards, would have taken a long time and drawn resources away from other critical work.

For more information, visit www.mentor.com 

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(October 21, 2010 – Nikkei) — Tokyo Electron Ltd. (TOELF – 8035) plans to invest around 5 billion yen in China to build a new manufacturing plant for equipment used to produce LCD panels. Tokyo Electron has, to this point, manufactured its LCD panel fab equipment in Japan. The Nikkei (10/20) reports that competition from South Korean and Taiwanese rivals has intensified for Tokyo Electron.

"South Korea is working hard to enhance its chip equipment industry as a national policy. If the South Korean currency, the won, remains weak, it is possible that the country will emerge as a new, formidable rival for us. But Japanese makers still have technological advantages over their foreign rivals in such cutting-edge areas as miniaturization," said Tetsuro Higashi, chairman of Tokyo Electron Ltd. (8035), speaking with The Nikkei Veritas (10/17).

Tokyo Electron is expected to forge a preliminary agreement with the government of Kunshan in Jiangsu Province as early as Wednesday. Under the proposed arrangement, Tokyo Electron will set up a 100% production unit and will secure a roughly 400,000 sq. meter property in Kunshan for the plant.

The plant could begin operating as early as the second half of 2011. It will initially focus on manufacturing parts used in LCD panel-making equipment. At the same time, engineers will be dispatched from Japan to shift manufacturing technology for the equipment itself. Tokyo Electron plans to launch such production sometime in 2012-2013. Higashi, speaking with The Nikkei Veritas, noted that LCD fab equipment and chip-making equipment have different requirements, saying "we need to cut costs to maintain price competitiveness. We are seriously considering steps like increasing overseas purchases of parts. But we have no plans for overseas production of equipment because we are working on such core elements of competitiveness as product quality and (maintaining our) technological advantage in Japan. We once built manufacturing plants overseas in response to the globalization of our clients’ operations, but we have integrated production into our Japanese operations to ensure product quality."

Tokyo Electron’s plant in Yamanashi Prefecture, which currently manufactures the units, will retain some output.

The company’s plan to construct the plant in China comes as the government there spearheads efforts to build production lines for large LCD panels. A number of Taiwanese, South Korean and Japanese panel manufacturers are expected to make a foray into China starting next year, notes The Nikkei.

Tokyo Electron hopes to increase its sales to 1 trillion yen and become the No. 1 player soon by globalizing its operations and developing next-generation technology, said Higashi.

Higashi was interviewed by Nikkei staff writer Takehiko Hama.

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(October 19, 2010 – BUSINESS WIRE) — Fusion-io, developer of a new flash-based, server-class memory tier (ioMemory), announced the Fusion-io Technology Alliance Program, an initiative that will bring collaborative solutions to the enterprise. In collaboration with Technology Alliance Program members, Fusion-io will develop new "Fusion Powered" technologies, including flash-optimized software, a new generation of storage appliances and virtualization solutions.

Under this program, authorized Technology Alliance Program members will work with Fusion-io to design, build and implement solutions that leverage Fusion’s innovative ioMemory technology. Members will also have access to Fusion-io sales, marketing and technical services to help to help partnering companies gain greater exposure to new markets, increase revenue opportunities and ensure technical compatibility.

"Customers that are implementing Fusion-io as a server-class memory tier across DataCore-powered storage area networks are experiencing unprecedented levels of I/O performance through tiered caching," said Carlos M. Carreras, VP of alliances and business development, DataCore Software, a Fusion-io Technology Alliance Program participant. "Fusion’s solid-state solutions combined with DataCore storage virtualization software achieve new levels of performance, high availability and energy efficiency when the two technologies are deployed together. We are pleased to be working with them to substantially increase enterprise options for virtualization."

"We look forward to working with Fusion-io to provide high performance, easily scalable data management solutions," said Steven Mih, VP of business development for Fusion-io Technology Alliance Program participant Membase. "Our Membase Server combined with Fusion’s ioMemory technology offers an excellent solution for significantly reducing data management costs."

"Enterprises around the world are seeking simplified and consolidated solutions that reduce infrastructure and overhead," said Tyler Smith, VP of alliances for Fusion-io. "One-stop solutions, like those provided through Fusion’s new Technology Alliance Program, reduce strains on resources, remove risks inherent with managing several partners and reduce expenditures. Working together, we believe we can offer greater value to our customers who are looking to solve the ever increasing data-intensive nature of the contemporary enterprise."

To learn more about collaborating through the Fusion-io Technology Alliance Program, go to http://www.fusionio.com/partners/technology-alliance-program.

Fusion-io provides system, application & database acceleration. For more on Fusion-io, go to www.fusionio.com.

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by Laura Peters, contributing editor

October 18, 2010 – Researchers from the IBM Alliance have developed a new germanium ion implantation process that implants Ge into the shallow silicon channel region prior to high-k/metal gate (HKMG) stack depositions. The process allows superior low threshold voltage (V_t) modulation relative to aluminum or titanium caps for low-V_t pFETs. At the 16nm node, such an approach could eliminate an aluminum cap and solve the low-V_t problem. Ion implantation also overcomes the integration challenges associated with epitaxial SiGe channel formation, which requires hardmask integration and precise silicon recess and SiGe thickness control. The group that developed the process, from Toshiba America Electronic Components, IBM’s Semiconductor Research and Development Center, and STMicroelectronics in Albany, NY, will present their findings at International Electron Devices Meeting (IEDM) in San Francisco, CA (Dec. 6-8).

To achieve low-V_t modulation, the researchers compared aluminum to germanium channel ion implantation processes. The Ge implant was followed by a recrystallization anneal, interfacial layer formation, then HKMG deposition. undesirable hump in the C-V curve could be eliminated, the group determined, by using a cryogenic process in which wafer temperature was reduced during implantation. The Ge implant proved superior to the aluminum process because it lowered threshold voltage by as much as 500mV with no increase in equivalent oxide thickness (EOT, see figure below). Conversely, large degradations of EOT occurred with the aluminum ion implantation. Other electrical results were favorable including an improved gate leakage current density/EOT curve (J_g-EOT), low gate-induced drain leakage (GIDL) current, and slightly improved NBTI characteristics over the control.

Threshold voltage shift vs. EOT. The germanium channel ion implantation induced ~500 mV threshold voltage shift with no increase in inversion thickness. The aluminum ion implant provides large Vt shift but also large EOT degradation. (Source: IBM Alliance)

To better optimize the process, the researchers sought to determine the physical cause of the threshold voltage modulation. Backside SIMS revealed high Ge concentration near the gate stack/silicon interfaces, and the threshold voltage shift correlates well with the germanium peak concentration. Through a process of elimination and chemical analysis, they determined that pile-up of Ge atoms at the interfacial layer/channel interface determines the pFET threshold voltage shift. This physical cause of V_t modulation is completely different than that of a conventional epitaxial SiGe channel, where energy-band modulation is the key factor.

(October 11, 2010) — China is projected to lead in patent activity by 2011, according to a detailed intellectual property (IP) analysis published by the IP Solutions business of Thomson Reuters. China’s patents focus has continued to be digital computing, a trend started in the 1990s/2000s outsourcing boom to China, but increasingly these are Chinese companies, not multinational parent companies, filing, says Thomson Reuters.

The study, "Patented in China II: The Present and Future State of Innovation in China," tracks global patent activity as a barometer for innovation across dozens of metrics to provide a view into China’s innovation economy. 

This second edition of the Thomson Reuters study suggests that patent filings in China will outpace the US and Japan in 2011, one year earlier than was forecast when the first edition of the study was published in 2008. The projected growth in Chinese patent activity is based on analysis of the total volume of first-patent filings in China, Europe, Japan, Korea and the U.S. China experienced an annual growth rate of 26.1% in total patent volume from 2003-2009, as compared to its closest rival, the U.S., with a 5.5% growth rate, but larger base number of patents. Also read: Ranking the nations on nanotech

Beyond projected patent growth, the study also examines the composition of patents from China relative to its peer group globally, domestic vs. foreign patent applications, patent technology areas, government/policy implications, and patent quality vs. quantity.

While innovation by domestic entities is driving China’s patent boom, China is also expanding its IP protection overseas. From 2007-2008, the growth rate of China’s overseas patent fillings in Europe, Japan and the U.S. were 33.5%, 15.9% and 14.1%, respectively.

Government innovation incentives, R&D tax deductions, Chinese premier Wen Jiabao’s commitment to make China an innovation-centered economy, and unique patent types (such as utility models) contribute to China’s acceleration to the top innovator spot.

As the Chinese economic landscape changes, a major shift is occurring in patent filings: agri-centered innovation related to food production is growing much more slowly than high-technology innovation. There was a 4,861% increase in domestic Chinese patent applications in digital computers in the decade from 1998 to 2008, versus a much more modest increase of 552% in natural products and polymers for that same period.

Approximately half of all Chinese patents filed in 2009 were utility models, which are less-rigorous, more-affordable forms of patents that provide 10 years of protection (versus 20 years for invention patents). The use of utility model patents in China has grown at a rate of 18% per annum since 2001. Utility models are also a potentially valuable strategy for foreign filings in China. Also read: IP trolls: Fiction or reality? Friendly or devious?

Despite the growing use of utility model patents, Chinese patent quality is slowly improving based on the Thomson Reuters analysis. By tracking the ratio of patent applications to granted patents among full invention patents in China, the analysis finds that patent quality is trending up.

The data in this report was compiled using the Thomson Reuters Derwent World Patents Index (DWPISM) database, a trusted source of global patent information with expertly indexed records, enhanced titles and comprehensive abstracts, enabling deeper insight into patent research.

To view the full report, "Patented in China II: The Present and Future State of Innovation in China," go to:
http://ip.thomsonreuters.com/chinapatents2010/index.html.

Thomson Reuters is a leading source of intelligent information for businesses and professionals. For more information, go to www.thomsonreuters.com.

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(October 11, 2010 – BUSINESS WIRE) — 3M, through its New Ventures business, invested in Printechnologics, a German printed electronics specialist, aimed at joint efforts for providing innovative solutions for electronic circuitry on paper or foil. Terms of the transaction were not disclosed.

Printechnologics developed custom alterations to conventional printing methods with extremely high scalability and cost advantages to address mass markets. The technologies can facilitate a broad range of solutions across b2b and b2c channels. This opens significant global market potential with printed circuit structures on paper.

Possible applications include anti-fraud solutions that could save billions of dollars, such as smart packaging to prevent counterfeiting or anti-fraud solutions in the gaming market in connection with 3M multi-touch displays, said Voyl Divljakovic, VP and GM, 3M Electronic Solutions Division. Listen to a podcast interview with 3M’s Art Lathrop about 3D film here.

“In the future, most paper products will include electronic data carriers enabling them to store data and communicate with the environment. We start connecting print products with online content," said Sascha Voigt, co-founder of Printechnologics.

Jan Thiele, co-founder of Printechnologics, added: "Printechnologics offers one of the most cost efficient printing solutions for electronics on paper. The results are environment-friendly, low-cost data structures that open up visionary possibilities in countless application areas. We are proud to work with an outstanding partner like 3M to explore new application fields outside of our current core business."

Printechnologics develops electronic systems produced entirely by a printing press. For more information, visit www.printechnologics.com.

3M produces thousands of innovative products for dozens of diverse markets. For more information, visit www.3m.com

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(October 8, 2010 – Reuters) — Advanced Micro Devices (AMD) is not for sale, however the chip maker will listen to interesting proposals, chief executive Dirk Meyer said when asked about Oracle’s recent interest in the sector.

"AMD is not for sale, but we are happy to listen to any proposal that is in the interest to our shareholders," Meyer said, reports Reuters.

Larry Ellison, chief executive of Oracle, said last month his firm is keen to make more acquisitions to bolster its technology and a microchip company could be a good fit.

AMD is the second largest supplier, after Intel, of processors based on the x86 architecture that powers most PCs and servers.

AMD started to see new rivalry from chip manufacturers using designs of ARM as computer and cellphone industry borders have begun to blur. "I don’t really view ARM as a threat," Meyer said, adding he saw major growth opportunities in the industry. ARM’s chip designs are relatively simpler and use less power, making them dominant in mobile phones and embedded electronics. ARM’s chip designs are also running tablet computers, such as Apple’s iPad, and its customers are developing processors for servers, although it will be about five years before products are on the market.

AMD shares have taken a beating because of poor demand for computers, but the chip maker wants to reclaim market share lost to Intel in past years with its new line of "Fusion" chips, which it says combines graphics and computing power better in a single chip than rivals.

(Additional reporting by Paul Sandle in London; Editing by Sharon Lindores, Reuters)

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