Category Archives: Uncategorized

Pfeiffer Vacuum has introduced the HiPace 2800 IT turbopump that is designed for ion implantation applications. The sophisticated rotor design of the turbopump results in an optimized pumping speed for light gases. This ensures exceptional process adaption for ion implantation processes, where hydrogen is the most accumulating gas. With 2,750 I/s pumping speed for hydrogen, the new HiPace 2800 IT is the best turbopump in its class.

The intelligent temperature management system prevents process condensation and deposition inside the pumping system. It allows setting the temperature individually to ideally support the process. The special coating of the rotor ensures robustness against all ion implantation process materials. These HiPace turbopumps have a robust hybrid bearing design with a combination of ceramic ball bearings on the fore-vacuum side and permanently magnetic radial bearings on the high vacuum side. Together with the efficient coating, this forms the basis for the long life cycle and maximum up-time of the pumps.

turbopump

 

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Date: August 9, 2016 at 1 PM ET

Free to attend

Length: Approximately one hour

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In this high-pressure environment, leading semiconductor companies are swapping out older manufacturing executions systems (MES) for modern MES. Surprised? True, the perceived risk of changing out MES in a semiconductor facility is high. Yet companies have done it with great success and enormous business benefits.

Fairchild Semiconductor’s positive experiences as it strives for quality, on-time delivery, new product introduction success, improved productivity and quality are indicative. In just one year, Fairchild switched out aging systems for a new MES at a plant in China – and the following month, they got it up at a second plant. Learn what they did to ensure the change happened quickly and without a hitch.

In addition to this case study, you’ll hear from a leading industry analyst who has interviewed dozens of people from semiconductor companies that have succeeded with the move to modern MES.

Join this free 1-hour session from your desk to learn:

  • What’s modern MES? The radically different face of today’s MES
  • Benefits to make the case: How modern MES addresses business challenges
  • How to change: Options for an MES changeover project
  • Succeed with speed: The 1-year MES change at Fairchild
  • Lessons Learned: What Fairchild and others did to ensure success

Speakers:

Harold Caldwell photoHarold Caldwell, Manufacturing Systems IT Director, Fairchild Semiconductor

Harold Caldwell is the IT Director of Global Manufacturing Systems at Fairchild Semiconductor. He has over 30 years of semiconductor manufacturing experience, including solutions for WIP tracking, quality systems, equipment automation, yield analysis, factory planning, and analytics. Harold’s career has focused on enabling increased operational efficiency as well as product quality and yield improvements through effective deployment of information technology.

Julie Fraser Square portrait reducedJulie Fraser, Principal and President, Iyno Advisors

Julie Fraser is Founder and Principal of Iyno Advisors Inc., where she fosters understanding between buyers and sellers of solutions for production, design, supply chain and analytics. She has researched and written hundreds of reports, papers, articles, and blog posts including the MES Fundamentals chapter of McGraw-Hills Semiconductor Manufacturing Handbook, due out in autumn of 2016.

Sponsored by Siemens

Siemens PLM Software, a business unit of the Siemens Digital Factory Division, is a leading global provider of product lifecycle management (PLM) and manufacturing operations management (MOM) software, systems and services. Camstar Semiconductor Suite in the Siemens MOM portfolio is a global-ready, growth-ready enterprise manufacturing execution system (MES) that enables semiconductor companies to keep pace with the huge advances in innovation and customer expectations. For more information, visit: www.siemens.com/mom/camstar.

 

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Date: July 28, 2016 at 10 AM MT

Free to attend

Length: Approximately one hour

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Decreasing the time to detect, contain and mitigate very low levels of Airborne Molecular Contamination (AMC) is critical for high tech manufacturers. Costs associated with AMC-related quality issues and yield losses are well understood, and adequate reduction of AMC is critical for clean manufacturers to stay competitive.

Technical personnel need the flexibility to efficiently collect AMC data with good temporal-spatial resolution anywhere in the clean environment for both sustaining sample plans, as well as to collect site-specific data to converge on AMC sources during troubleshooting events. A brief overview of AMC will be presented along with the latest technology for efficiently identifying AMC sources in the cleanroom.

Speaker: 

RodierDan Rodier, Ph.D., Technology Development Manager, Electronics Division, Particle Measuring Systems

Dr. Dan Rodier has a Ph.D. in analytical chemistry from the University of Colorado and has over 25 years of experience developing and implementing technologies and strategies to measure airborne molecular species and particulate contamination. He has worked with customers across Asia, Europe, and North America to implement monitoring programs in the semiconductor, disk drive, and display industries.

Sponsored by Particle Measuring Systems Inc. 

Particle Measuring Systems Inc. (PMS), a subsidiary of Spectris plc, is a global technology leader in contamination monitoring, the inventor of laser particle counting, and now is the leading provider of solutions for monitoring and controlling many forms of contamination that impact companies that manufacture in ultra-clean environments. Learn more at pmeasuring.com.

This blog originally appeared on SemiMD.com and was featured in the May 2016 issue of Solid State Technology.

By Cédric Mayor, Chief Technical Officer, Presto Engineering, Inc., Caen, France [email protected]

The confrontation between Apple and the FBI over the FBI’s request for assistance in hacking a known terrorist’s iPhone brought the topic of security to the top of the agenda for the tech industry. Recent developments, including the FBI’s withdrawal of its request and Apple’s subsequent demand that the FBI now share information the security vulnerability that permitted a third party to hack the iPhone, have only emphasized the “moving target” nature of security. Whether manufacturing a car, a smartphone, or a smartcard, security is an important aspect to consider and plan into the supply chain. And concerns about security will only increase if the IoT grows as explosively as many industry pundits are now predicting.

One of the defining characteristics of “things” for the IoT is their autonomous connectivity. With the likelihood that there will soon be tens or hundreds of millions of these things connected to networks everywhere, it is imperative to establish a certain level of trust that such objects will not provide a backdoor or counterfeit identity that could jeopardize an entire network and the costly infrastructure of service providers.

Fortunately, the industry has already encountered this problem and developed a workable solution for smartcards with the concept of secured product manufacturing test flows. Admittedly, it has an impact on the requirement for test infrastructure and complexity, but it is a well proven solution. Essentially, it addresses the security and confidentiality requirements of IoT devices for encrypted certificates of authentication or secret token keys by isolating the injection of these secrets at the die or SiP (system in package) level within a secured final test and assembly environment.

The specific concerns that must be addressed in this secure environment include:

-How to ensure that each die in an IoT SiP/McM (multichip module) device can be tested along a route of trust.

-How to provide a seamless test manufacturing flow that efficiently and effectively detects manufacturing quality issues    while injecting secrets from customers, without storing the secret information, needing to decrypt it, or leaving it open to  reverse engineering.

-How the injection of secrets/certificates impacts DFT and diagnosis of the chip.

These sensitive operations require the insertion of secret keys, tokens, certificates and boot loaders into the device during wafer probe or at final test on the package level. The secret vectors must be dynamically allocated and are often reshuffled by the end-customers to disaggregate the supply chain. The test floor must include an encrypted server gateway, and the ability to selectively push the encrypted information into the right device on wafer, which is usually locked at the end of the wafer test and completely isolated when the wafer is sawn. Test and assembly is really the only opportunity to address confidentiality since the heterogeneous nature an IoT devices necessarily involves the sourcing of die from different vendors and requires validation of trust for each component. Test providers that can deliver a secure workflow will be critical contributors to the security of the IoT.

BY PETE SINGER, Editor-in-Chief

The ConFab Conference and Networking Event will be held June 12-15. Presented by Solid State Technology, this executive-level event is designed exclusively for those driving growth and innovation in the semiconductor industry. Here are 10 reasons to register now.

1. The keynotes. Hear from Dr. Thomas Caulfield, senior vice president and general manager of GlobalFoundries’ latest leading- edge 300mm semiconductor wafer manufacturing facility; Sunny Hui, senior vice president of worldwide marketing, Semiconductor Manufacturing International Corp., and Bill McClean, President of IC Insights.

2. The networking. The semiconductor industry has undergone unprecedented consolidation over the last year and the only way to know who’s who in the new landscape it to get out and talk to people. There are plenty of opportunities to get together at breakfast, lunch and for evening receptions.

3. The meetings. We arrange strategic meetings between technology suppliers and manufacturers, including IDMs, foundries and OSATs. Fabless companies, which are increasingly driving manufacturing decisions, are also involved.

4. The big picture. You’ll walk away with a high level overview of the myriad of challenges and opportunities now facing the semiconductor industry.

5. The semiconductor industry needs to change the way it thinks about innovation, both technical innovation and business model innovation, especially when it comes to the Internet of Things (IoT).

6. Fab Management. Today’s fab managers must continually be thinking of ways to improve operational efficiency, optimize asset utilization, boost tool and worker productivity (and safety), increase throughput, maximize yield and reduce defectivity.

7. System Level Integration: New Directions in Packaging. How will these technologies be used in advanced data centers & network systems, in future smart phones, and the growing medical, industrial and lifestyle IoT applications?

8. China. We will examine how the China “wild card” and increased M&A activity designed to bring advanced technology into China is a true game-changer for the worldwide semicon- ductor industry.

9. Great location. The ConFab will take place at the beautiful Encore at The Wynn right in downtown Las Vegas.

10. Collaboration. It’s clear that the need for real collaboration has never been greater. At The ConFab, industry leaders will gather to tackle tough questions, take a look at the new post- consolidation landscape, network in a unique environment and collaborate on the future.

I hope to see you there! Check out www.theconfab.com for more information.

BY DR. PHIL GARROU, Contributing Editor

Samsung Electronics announced that it has begun mass producing the industry’s first 4-gigabyte (GB) DRAM package based on the second-generation High Bandwidth Memory (HBM2) interface, for use in high performance computing (HPC), advanced graphics and network systems, and enterprise servers.

The newly introduced 4GB HBM2 DRAM, uses Samsung’s 20nm process technology and is reportedly more than seven times faster than the current DRAM.

The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit (Gb) core dies on top (FIGURE 1). These are then vertically interconnected by TSV holes and microbumps (FIGURE 2). A single 8Gb HBM2 die contains > 5,000 TSV holes, which is more than 36 times that of a 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.

Screen Shot 2017-04-21 at 12.24.14 PM Screen Shot 2017-04-21 at 12.24.20 PM

Samsung’s new DRAM package features 256 GBps of bandwidth, which is double that of a HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips. Samsung’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds ECC (error-correcting code) functionality to offer high reliability.

Samsung also plans to produce an 8GB HBM2 DRAM package in the next 12 months. This will offer designers a 95 percent space savings vs GDDR5 DRAM.

Samsung announced that production volume of HBM2 DRAM will increase over the remainder of the year.

The second-generation HBM (HBM2) technology is outlined by the JESD235A standard. It uses 128-bit DDR interface, 1024-bit I/O, 1.2 V I/O and core. Just like HBM1, HBM2 supports two, four or eight DRAM devices on a base logic die (2Hi, 4Hi, 8Hi stacks). HBM Gen 2 expands capacity of DRAM devices within a stack to 8 Gb and increases supported data-rates up to 1.6 Gb/s or even to 2 Gb/s per pin.

 

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Date: May 26, 2016 at 1 PM ET

Free to attend

Length: Approximately one hour

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Wafer level packaging (WLP) using fan-out technology is a disruptive technology for achieving low-cost, low-profile package solutions for a wide range of applications, including mobile, MEMs, tablets, and automotive. Fan out technology provides cost-effective, high-density interconnects in a small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.

Speaker: 

Bernie Adams_P2[1]Bernard Adams, Deputy Director, Product Technology Marketing, STATS ChipPAC

Bernard Adams is Deputy Director, Product Technology Marketing at STATS ChipPAC where he is responsible for marketing and business development of the Company’s wafer level packaging technology.  He has been with STATS ChipPAC since 2013 and has a diverse background in sales, strategic marketing, finance and product development experience in flip chip technology, backend packaging and front end semiconductor expertise. Prior to joining STATS ChipPAC, Bernard was with Cleanpart US LLC where he was the Micron-Intel Global Account Manager and the Western Regional Manager, responsible for supporting the top 35 integrated Device Manufacturers with semiconductor engineering and tools services. He has also held sales leadership positions at Quantumclean, Leica Microsystems, Electroglas and Flip Chip Technologies. Bernard has a Bachelor of Science in Electrical Engineering from Purdue University and a Masters of Business Administration in International Finance from the University of Pittsburgh.

Sponsored by Zeta Instruments

Zeta Instruments designs and manufactures Multi-Mode non-contact optical profilers and defect inspection systems for multiple high-technology industries, including: advanced semiconductor packaging, high-brightness LEDs, advanced glass manufacturing, solar, microfluidics and data storage.

Zeta’s growth has been driven by rapid technology progress combined with strong focus on customer requirements.  As a result, Zeta has installed production and R&D related equipment in 23 different countries. The rapid adoption of Zeta’s products is a testament to the company’s differentiated technology and a turn-key solution based approach towards designing the tools.  The advanced Zeta-580 Optical Profiler has been adopted by the leading OSATs for WLCSP and FOWLP related metrology and inspection.

Our locations include our headquarters in San Jose, CA, a regional office in Shanghai, China, and sales and service representatives worldwide. www.zeta-inst.com

 

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Date: May 11, 2016 at 12 PM ET

Free to attend

Length: Approximately one hour

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In 2015, the MEMS market did not grow as much as we initially expected. In the past, the Smart Phone industry was a strong driver of the MEMS industry with ever increasing volume. Today, MEMS are becoming commodity products with very low price. The webcast will review the latest market data and forecasts for the future. The MEMS “commoditization” paradox will be discussed as well as latest technical trends (sensors combos, packaging).

Speakers: 

EM_4_[1]Dr. Eric Mounier, MEMS Senior Analyst, Yole Développement

Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. He previously worked at CEA LETI R&D lab in Grenoble, France in marketing dept. Since 1998 he is a cofounder of Yole Développement, a market research company based in Fr ance. At Yole Développement, the “More than Moore” market research and strategy consulting company, Dr. Eric Mounier is in charge of market analysis for MEMS & Sensors, visible and IR imagers (CIS, microbolometers), semiconductors, printed electronics and photonics (e.g. Silicon photonics). He has contributed to more than 200 marketing & technological analysis and 100 reports. Eric is also an expert at the OMNT (“Observatoire des Micro & Nanotechnologies”) for Optics.

image007Philippe Robert, Manager of the Microsystem Components Laboratory, CEA Leti

Philippe Robert received a M.Sc. degree in optical electronic in 91 from the university of Grenoble, and a Ph.D in electrical engineering in 96, from the National Polytechnic Institute of Grenoble (INPG). From 1996 to 1998, he worked as R&D engineer at SILMAG S.A, to develop new TSV interconnections for hard disk silicon magnetic heads. From 1998 to 2001, he was part of the technical staff of THALES-AVIONICS Sensor Unit, where he was in charge of silicon and quartz inertial sensors developments. In 2001, he joined CEA-LETI where he was involved in several projects on RF-MEMS. He is presently manager of the Microsystem Components Laboratory. He has authored or co-authored about 40 journal papers and conference contributions, and he holds more than 40 patents dealing with MEMS, NEMS and packaging.

Sponsored by Boston Semi Equipment

Boston Semi Equipment (BSE) manufactures test cell automation equipment and provides technical services to semiconductor manufacturers and OSATs worldwide. Our test cell equipment solutions include automated test equipment (ATE), gravity and pick-and-place handlers, wafer probers and customized automation solutions. BSE’s worldwide service professionals and technical support offerings enable our customers to achieve maximum uptime from their semiconductor test operations. Our goal is to lower equipment and operating costs for our customers.

BrewerScienceBLUE

Date: May 10, 2016 at 1 PM ET

Free to attend

Length: Approximately one hour

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In order to adapt to new applications and cut down cost, the semiconductor industry seeks further performance and functionality boosts through package level system integration. While transistor scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight is turned to advanced packages. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC solutions and related SiPs together with upgraded flip chip CSP/BGAs aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality.

This webcast will focus on the status of the advanced packaging industry, the challenges and opportunities that lie ahead. A high level overview will be given on current and future global markets, with a particular reflection on the evolution of the market in China. Furthermore, 3D integration packaging technology developments will be summarized, with focus on the 2.5D/3D, FO WLP and advanced FC substrate platforms.

Speakers:

AndrejIvankovic_YOLE2015_Pro_HDAndrej Ivanovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing, Yole Développement

Andrej Ivankovic is a Technology & Market Analyst, in the Advanced Packaging and Semiconductor Manufacturing team, at Yole Développement. He holds a master’s degree in Electrical Engineering, with specialization in Industrial Electronics from the University of Zagreb, Croatia and a PhD in Mechanical Engineering from KU Leuven, Belgium. He started as an intern at ON Semiconductor performing reliability tests, failure analysis and characterization of power electronics and packages. The following 4 years he worked as a R&D engineer at IMEC Belgium on the development of 3D IC technology, focusing on electrical and thermo-mechanical issues of 3D stacking and packaging. Part of this time he also worked at GLOBALFOUNDRIES as an external researcher. He has regularly presented at international conferences authoring and co-authoring 18 papers and 1 patent.

Mike KellyMike Kelly, Senior Director 3D TSV Development, Amkor Technology

Mr. Kelly joined Amkor in 2005 and has led package developments for EMC shielding, low cost thermal enhancements for PBGAs,  image sensors and most recently 2.5D and SLIM package development. He previously worked for HP and Avago. Mike has worked in electronics interconnect for 24 years, including circuit board assembly,  IC package mechanical and thermal design and projects ranging from polyester flexible circuits to eutectic flip chip, and management of IC IP block design and acquisition and electrical signal integrity teams. Mike holds master’s degrees in Mechanical and Chemical Engineering.

Sponsored by Brewer Science

Brewer Science is a global technology leader in developing and manufacturing innovative materials, processes, and equipment for the fabrication of semiconductors and microelectronic devices. In 1981, Brewer Science revolutionized lithography processes with its invention of Brewer Science® ARC® anti-reflective coatings. Today, Brewer Science continues to expand its technology portfolio to include products that enable advanced lithography, 3-D integration, chemical and mechanical device protection, nanotechnology, and thin wafer handling.

Brewer Science was one of the first companies to recognize the potential of temporary wafer bonding for ultrathin wafer handling. Temporary bonding is key as the semiconductor industry pushes for smaller devices, faster processing, and lower costs. The industry is moving toward thinner and larger-area substrates that can handle higher stress levels and more extreme temperature conditions, such as higher-temperature processing and lower-temperature bonding and debonding. Brewer Science offers advanced material and equipment sets for low-volume R&D environments and works with leading equipment vendors to provide fully automated solutions for higher-volume needs. By listening to customer needs and following industry advancements, Brewer Science has created the highest-quality temporary bonding products possible.

ARC is a registered trademark of Brewer Science, Inc.

Park Logo[4]

Date: Thursday, April 14, 2016 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

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Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and characterization.  As the industry continues to explore new patterning methods, new phenomena further challenge metrology and characterization including pitch walking, stress relaxation in multilayer fins, and new device designs.   New materials continue to be explored for transistor and interconnect applications.  Here, the challenges facing materials characterization highlight the issues that will face in-line metrology when these materials transition to manufacturing.

Speaker:

Alain Diebold 2015Alain Diebold, Interim Dean, College of Nanoscale Sciences

Alain Diebold is Interim Dean at the College of Nanoscale Sciences.  He is also the Director of the SRC NRI INDEX Center.  He is a fellow of the American Vacuum Society and SPIE as well as a senior member of the IEEE. He is an associate editor for IEEE’s Transactions on Semiconductor Manufacturing. Before moving to Albany, Alain was a Senior Fellow at SEMATECH.  Prior to moving to Austin, He was a senior chemist at Allied Signal in Morristown, NJ. Alain received his PhD from Purdue University in 1979.

Sponsored by Park Systems

Park Systems provides the best quality AFM equipment for manufacturing and research in Semiconductor microscopy for failure analysis and defect review. Park Systems has introduced the revolutionary Park 3DM Series, the completely automated AFM system designed for overhang profiles, high-resolution sidewall imaging, and critical angle measurements. With the patented decoupled XY and Z scanning system with tilted Z-scanner, it overcomes the challenges of the normal and flare tip methods in accurate sidewall analysis.   Park NX-Hivac allows failure analysis engineers to improve the sensitivity of their measurements through high vacuum Scanning Spreading Resistance Microscopy (SSRM).  Park Smart ADR is the most advanced defect review solution available, featuring automatic target positioning without the need for labor intensive reference marks that often damage the sample. The Smart ADR process improves productivity by up to 1,000% compared to traditional defect review methods and offers up to 20x longer tip life thanks to Park’s groundbreaking True Non-Contact™ Mode AFM technology.

Park NX-Wafer makes accurate, repeatable, and reproducible sub-Angstrom roughness measurements for the flattest substrates and wafers with minimized tip-to-tip variation.  Park NX-Wafer delivers the industry’s lowest noise floor of less than 0.5 throughout the wafer area, combined with True Non-Contact Mode™ to achieve reliable measurements even for the long-range waviness measurement of scan sizes up to 100m x 100m.

Park Systems, is a world-leading manufacturer of atomic force microscopy (AFM) systems offering a complete range of products for researchers and industry engineers in chemistry, materials, physics, life sciences, semiconductor and data storage industries, used by over a thousand leading institutions and corporations worldwide. Park products are sold and supported worldwide with regional headquarters in the US, Korea, Japan, and Singapore, and distribution partners throughout Europe, Asia, and America. For more information call 408-986-1110 or email  [email protected] or visit the website at www.parkafm.com