7. InGaAs Nanowire FETs on Silicon
Category: Alternatives to Silicon
Paper 31.1 – Gate-All-Around InGaAs Nanowire FETS with Peak Transconductance of 2200 μS/μm at 50nm Lg Using a Replacement Fin RMG Flow; N. Waldron et al, Imec/ASM

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There have been many demonstrations of the potential performance benefits of III-V channels for low-power logic devices, but complete integration of these channels in devices made on standard 300mm silicon wafers would demonstrate their manufacturability and relevance to the industry. That day is getting closer, as a team led by Imec will discuss gate-all-around, high-performance InGaAs nanowire MOSFETs built on 300mm silicon wafers. Their high transconductance (g_m=2200) indicates that despite having a lattice-mismatched substrate, the InGaAs channel material maintains its high carrier velocity.

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6. High-Frequency, Low-Leakage IGZO Transistors for Internet of Things
Category: Alternatives to Silicon
Paper 6.5 – 20-nm-node Trench-Gate-Self-Aligned Crystalline In-Ga-Zn-Oxide FET with High Frequency and Low Off-State Current; Daisuke Matsubayashi et al, Semiconductor Energy Laboratory Co., LTD

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Much work is ongoing to develop low-power devices and circuits for Internet of Things applications. A team from Japan’s Semiconductor Energy Laboratory Co. will describe how they made 20nm gate-all-around MOSFETs with incredibly low off-state currents of <0.1pA, yet with cutoff frequencies exceeding 10GHz. The transistors were made from thin films of indium-gallium-zinc-oxide (IGZO). They were built using a self-aligned process that eliminated overlaps from the gate to the source and drain, rendering the channel immune from short-channel effects that otherwise would degrade performance. Integrated in a DRAM memory cell to demonstrate their performance, their extremely low off-current allowed for data retention of >10 days at 125°C.

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5. Diamond-Shaped Ge Nanowire FETs
Category: Alternatives to Silicon
Paper 15.1 – Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology; Yao-Jen Lee et al, National Nano Device Laboratories/National Chiao Tung University/National Chi Nan University

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Silicon and germanium have crystalline atomic structures which, like other crystals, have different facets. The materials’ electrical properties can vary according to which facet is used to build devices, and some facets are more favorable than others. A team led by Taiwan’s National Nano Device Laboratories will describe how they built gate-all-around (GAA) nanowire MOSFETs with diamond-shaped Ge and GeSi nanowire channels. The purpose of the work was to find a way to more effectively use germanium (Ge) as the channel material in multi-gate device configurations, because high-mobility Ge is seen as potentially necessary for scaling beyond the 10-nm technology node. Using common dry etching and blanket epitaxy techniques, the researchers sculpted Ge and GeSi nanowires into diamond cross-sectional shapes, with four favorable facets (the so-called {111} orientation) exposed. They used these nanowires as suspended channels in a GAA MOSFET configuration. Both nFET and pFET transistors with excellent performance were demonstrated, including pFETs with an I_on/I_off ratio exceeding 10⁸, the highest ever reported for Ge-based pFETs.

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4. III-V Nanowire CMOS on Silicon
Category: Alternatives to Silicon
Paper 15.4 – Gate-All-Around CMOS (InAs n-FET and GaSb p-FET) Based on Vertically-Stacked Nanowires on a Si Platform, Enabled by Extremely-Thin Buffer Layer Technology and Common Gate Stack and Contact Modules; Kian-Hui Goh et al, National University of Singapore/Nanyang Technological University

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High electron-mobility III-V semiconductors have been intensely researched as alternative channel materials for sub-7 nm technology nodes, but one of the main stumbling blocks is how to integrate them monolithically and cost-effectively with traditional CMOS silicon technology. A team led by National University of Singapore will describe the first use of vertically stacked III-V nanowires to do so. The key was an extremely thin (sub-150nm) high-quality GaSb buffer layer on silicon. On top of it, the researchers built multi-gate InAs nFETs and GaSb pFETs from stacked InAs or GaSb nanowires, respectively. The fabrication technique employed multiple common modules such as gate stack and contact processes. Good subthreshold slope of 126 mV/decade and DIBL of 285 mV/V were obtained for the InAs nFET with a 20nm channel length. Meanwhile, the lowest reported subthreshold slope of 188 mV/decade and the highest reported I_on/I_off ratio of 3.5 were demonstrated for the GaSb pFET, which had a channel length of 500nm. The technology may be suitable for future high-performance and low-power logic applications.

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3. Making RRAM with a FinFET and Its Dielectric
Category: Memories
Paper 10.5 – 1Kbit FINFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process; Hsin Wei Pan et al, National Tsing-Hua University/Taiwan Semiconductor Manufacturing Co.

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A research team led by Taiwan’s National Tsing-Hua University will describe a novel way to build a resistive memory (RRAM): use a FinFET transistor for the “select” gate and the FinFET’s HfO₂-based resistive dielectric film for a storage node of the RRAM cell. At the 16nm node, the RRAM cell size is 0.07632μm² without any additional mask or process steps required. It exhibits low-voltage operation, good retention and excellent reliability overall.

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2. New NAND Architecture
Category: Memories
Paper 3.2 – A Novel Double-Density, Single-Gate Vertical Channel (SGVC) 3D NAND Flash That Is Tolerant to Deep Vertical Etching CD Variation and Possesses Robust Read-disturb Immunity; Hang-Ting Lue, Macronix

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The most popular 3D NAND architectures are gate-all-around (GAA) devices arranged in a vertical channel structure. While these exhibit excellent device performance, they are highly sensitive to any variations in their critical dimensions (CD). It is increasingly difficult to maintain precise dimensional control of these structures at the high aspect ratios required, however. Macronix researchers will describe an alternate 3D NAND architecture that mitigates this issue. Their idea is to create a 2D-like structure but in the vertical direction; i.e., to stand it up on its end, in effect. The structure is a single-gate, flat-cell thin film transistor (TFT) with an ultra-thin body that Macronix calls single-gate vertical channel (SGVC). The design is not as sensitive to CD variation and the researchers say it can have potentially more than four times the memory density of GAA vertical channels at the same scaling node.

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1. DRAMs Poised for 20nm and Below
Category: Memories
Paper 26.5 – 20nm DRAM: A New Beginning of Another Revolution; Jemin Park et al, Samsung

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Further advancement in dynamic random access memories (DRAMs) has all but been given up for dead time and time again, as scaling them gets more difficult and as alternative memory technology options proliferate. Now that leading-edge technology is at 20nm and below that day might finally seem to be at hand, but designers keep coming up with new tricks to extend their usefulness. The trend will continue at the IEDM when Samsung researchers describe clever techniques they used to wring substantial performance improvements out of state-of-the-art 20nm DRAMs with no need for expensive and as-yet unproven fabrication techniques like EUV lithography. One key improvement is a honeycomb cell structure that effectively increases cell pitch by 7.5%, leading to a 57% increase in cell capacitance for improved data retention. Another is an air-gap spacer arrangement that achieves a 34% reduction in bitline capacitance for faster operation. The researchers say these techniques will be key enablers for DRAMs for the 20nm node and beyond.

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BY PETE SINGER, Editor-in-Chief

Please join me welcoming our news members of the Advisory Board for our annual conference and networking event, The ConFab. New members include: Pinyen Lin, Director of Etch Engineering, G450C and Deputy Director, TSMC; Robert Cappel, Senior Director Corporate Marketing, KLA-Tencor; William Chen, Fellow and Senior Technical Advisor, ASE; L.T. Guttadauro, Executive Director, Fab Owners Associ- ation; Li Li, Distinguished Engineer, Cisco Systems; Ariel Meyuhas, COO, The MAX Group; Gary Patton, CTO and Head of Worldwide R&D, GLOBALFOUNDRIES and Elton Peace, General Manager North America Regional Operations, Lam Research.

The new members will be joining the existing Advisory Board, comprised of David Bennett, VP Alliances, GLOBALFOUNDRIES; Janice M. Golda, Director, Lithography Capital Equipment Development, Intel Corpo- ration; Devan Iyer, Director Worldwide Semiconductor Packaging Opera- tions, Texas Instruments; Lori Nye, COO/Executive Director Customer Operations, Brewer Science; Ken Rygler, President, Rygler Associates (founder of Toppan Photomasks); Sima Salamati, VP, Fab Operations, imec; Hans Stork, CTO, ON Semiconductor Corporation; Aubrey Tobey, President, ACT International; Geoffrey Yeap, VP of Technology, Qualcomm Inc.; and Abe Yee, Sr. Director, Advanced Technology and Package Development, Nvidia Corporation.

Now in its 12th year, The ConFab will be held June 12-15, 2016 at The Encore at The Wynn in Las Vegas. The conference program will focus on “The Economics of Semiconductor Manufacturing and Design”. Topics will include:

• How IoT is Driving the Semiconductor Industry
• Filling the Fabs of the Future: A Guide to Hot New Applications • MEMS Sensor Fusion and More then Moore
• The Limits of Scaling: Understanding the Challenges of sub-10nm Manufacturing
• Fabless, Foundries and OSATs: Optimizing the Supply Chain • System Integration, Advanced Packaging + 3D Integration
• China’s New Role in the Global Semiconductor Industry
• Legacy Fabs and the Resurgence of 200mm
• The Impact of Continued Consolidation Across the Supply Chain • Wearables and Bioelectronics: The Cusp of a Revolution?
• Tackling Rising R&D Costs in the Semiconductor Industry

The ConFab is an executive-level conference and networking event for business leaders from the semiconductor manufacturing and design industry. The event features a high-level conference program, networking events and business meetings with purchasing decision makers and influencers. More information on The ConFab may be found at www.theconfab.com. Please join us!