Device Architecture

DEVICE ARCHITECTURE ARTICLES



Is the past a prologue for this cycle?

01/08/2009  Every semiconductor downturn raises two key questions: How long will it last, and who will survive? For answers, we must look at the causes of these cyclical events, and hazard some crystal-ball gazing into the current crisis.

Improving R&D ROI in a downturn

01/08/2009  The current economic crisis is forcing semiconductor companies to dramatically reduce capex and opex spending. A prolonged reduction in R&D investment can have long-term negative consequences, including delayed product introductions and reduced competitiveness. Increases in semiconductor R&D expenditures have steadily outpaced revenue growth because of increasing R&D complexity, shorter product life cycles, and reduced ASPs, and this fundamental issue is exacerbated in a downturn.

Vertical integration in materials needed to deliver a more attractive COO model

01/08/2009  In 2009, materials and chemistry will continue to play an important role in semiconductor development. Given the current global economic climate, we expect to see an increased focus on cost of ownership (COO), along with greater collaboration throughout the supply chain as companies look to partner for expertise and spread both cost/risk and potential rewards.

Technology-driven growth still possible in current downturn

01/08/2009  Though we find ourselves in a deep cyclical downturn made worse by chaos in international financial markets, IC manufacturers must continue to make critical investments in new and emerging technologies that will define the competitive landscape when the next upswing materializes. Technological innovation has been the lifeblood of our industry since its inception. We have grown used to surmounting insurmountable barriers with creative solutions to often unanticipated problems.

For long-term stability, embrace a more aggressive outsourcing model

01/08/2009  Looking ahead to 2009, we find ourselves in an economic downturn, the depth and breadth of which is yet unknown. What is known is that it will lead to both consolidation and failures within the equipment space, as is already becoming clear with the smaller players in the market.

Position for leadership with predictive computational manufacturing

01/08/2009  In the quest to develop products with higher functionality at lower cost, the semiconductor value chain is struggling to cope with the increasingly complex technologies and expenditures needed to develop leading-edge CMOS products. Though the nature of these challenges is not new, their intensity is unprecedented.

Steady progress reported on HK+MG for ≤32nm

01/08/2009  Chipmakers are trying many paths toward high-k metal gate dielectric (HK+MG) CMOS for 32nm and beyond, and papers presented at IEDM 2008 in San Francisco, CA, showed steadily improving results even though the routes may vary. Still, getting to uniform manufacturable devices presents some tough challenges.

Reports differ on Samsung capex plans

01/06/2009  Media reports suggest Samsung is chopping its chip investment plans by nearly 50%, but the company says it's not so -- at least, not yet. But if true, it could actually help the firm's DRAM competitors.

Taiwan DRAM bailout redux: Bailout numbers, who wants in, Elpida's role

01/06/2009  Taiwan's National Development Fund reportedly is ready to appropriate about US $6B to underpin its DRAM and flat-panel display industries, but individual companies are still hashing out whether their individual needs will be met. And an outside party is stumping to be the island's DRAM consolidator to challenge Samsung.

NEC touts work toward NVM for SoCs

01/05/2009  NEC Corp. says it has developed and demonstrated an operating nonvolatile magnetic flip-flop, opening the possibility for SoCs that require zero power in a standby state and can be quickly returned to an active state.

IEDM Day 3: SRAMs, image sensors, flash memory

12/17/2008  In his daily blog from IEDM, Chipworks' Dick James looks at a number of interesting papers presented on SRAM, image sensors, and radiation soft errors in flash memories.

Latest 32nm CMOS, memory beyond flash, plus novel devices detailed at 2008 IEDM

12/16/2008  New memory concepts and the latest 32nm CMOS with metal gates and high-k dielectrics were highlights of the 2008 International Electron Devices Meeting (IEDM) in San Francisco, Dec. 15-17. A wide range of innovative device technology, including 3D wafer-level integration and a nanowire battery were also presented.

IEDM Day 2: Brain cells, "stress," nanowire batteries

12/16/2008  In an exclusive daily blog for SST, Chipworks' Dick James reviews presentations on interfacing chips and brain cells, nonvolatile memories, parallel sessions on s/d stress options, and a SRO talk on nanowire batteries.

Gartner: 2008 chip decline, 2009 "considerably worse"

12/16/2008  A month after dropping its outlook for both 2008 and 2009, Gartner has decided its previous "worst-case scenario" for the chip industry isn't nearly bad enough -- it now projects only the fifth decline in the past 25 years for 2008, and says 2009 will be "considerably worse."

ProMOS govt appeal highlights JV shifts

12/16/2008  ProMOS is poised to officially file for assistance from the Taiwanese government, a move that comes with a catch -- the company would have to abandon its partnership with Korean chipmaker Hynix and forge ties with Japan's Elpida.

Bound by bonds: Inside Elpida's ¥50B CB dilemma

12/16/2008  A languishing share price has triggered a clause in Elpida's convertible bonds (CB) whereby it has to redeem ¥50B (US $550M) of them in the next month, raising concerns over how the company will finance future capital investments.

IEDM: IMEC touts 11MP micromirror array

12/16/2008  Dec. 15, 2008 - In a paper discussed at this week's IEDM, researchers from IMEC reveal a monolithically integrated 11-megapixel 10cm2micromirror array, double the pixel density of comparable micromirrors, and a 10312 cycle mechanical lifetime, also a record, they claim.

IEDM Day 1: Dense data on 22nm

12/15/2008  In an exclusive daily blog for SST, Chipworks' Dick James soaks in the first day of IEDM with dense presentations of 22nm CMOS presentations.

IEDM: IMEC optimizes 65nm Ge pFET

12/15/2008  Minimizing the Ge in diffusion into a silicon capping layer is the key to boost electrical performance and reach 1nm EOT (equivalent oxide thickness) devices, according to IMEC researchers presenting at IEDM this week.

Intel decloaking 32nm logic tech at IEDM

12/15/2008  Intel's 32nm logic technology will be described in a paper to be presented at the IEDM conference this week by Sanjay Natarajan, the company's director of 32nm CMOS technology development.




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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