10/08/2008  October 7, 2008: SUSS MicroTec, a supplier of solutions for the 3D, MEMS, advanced packaging and nanotechnology markets, announced that the capabilities of its manual mask aligners are now enhanced with a new nanoimprint toolkit that enables them to pattern large areas with repeatable sub-50nm printing capability.

10/03/2008  October 3, 2008: In providing a product solution to implement patented molecular transfer lithography (MxL) processes, a class of nanopatterning procedures that use water-dissolvable nanostructured polyvinyl alcohol (PVA) templates, TDI announces for sale the exaGlide 10 series.

10/02/2008  EUV lithography is still a long way from manufacturing, not expected for mass production until at least 2012 and the 22nm node. But early work with alpha tools is giving a much better understanding of what the platform's capabilities will be, and where the needs are (optics, resists, sources). And at some point the answers will come only with taking risks and making the investment.

10/01/2008  October 1, 2008: NIL Technology has launched a new line of grating stamps, extending the company's standard stamp product line, targeting a broad range optics and photonics applications.

09/24/2008  A full-day symposium at this year's Diskcon USA explored the lithography implications of sub-ITRS roadmap feature sizes on disk drives, with the challenge that HDD lithography must cost 10× less than NAND flash lithography, the lowest-cost semiconductor process.

09/18/2008  The complexity design and process interactions at the 22nm node are so great that they will require a new level of computational power. Thus, IBM and select partners have devised a "computational scaling" strategy that provides an end-to-end look at technology development, and how to accept designs into technology for manufacturing.

09/08/2008  2 years ago, the EMC3D Consortium, open consortia of equipment and materials manufacturers, established itself and set out to develop a process flow and cost model for 3D integration. Focusing on via-first TSVs as the method of interconnect, the intention was to find a solution to achieving this for $200/wafer cost of ownership (CoO) on a 3-year timeline. It appears, however, that they've beaten their own goal ahead of schedule.

09/03/2008  September 3, 2008: X-FAB Silicon Foundries' 200mm facility in Kuching, Sarawak, Malaysia, now is fully qualified for volume production and second sourcing of the company's 0.35μm high-voltage process technology.

08/22/2008  One of the most common and most ignored types of chips is on almost every desk in this electronic world of ours -- the inkjet printhead. This edition of Chip Forensics examines a three-color printhead device out of Hewlett Packard's low-cost HP 60 Tricolor ink cartridge launched earlier this year.

08/18/2008  IBM and joint development partners (AMD, Freescale, STMicroelectronics, Toshiba, CSNE in Albany, NY) say they have built a working static random-access memory (SRAM) using 22nm process technologies -- but details will have to wait until December's IEDM.

08/18/2008  The chrome material that has blocked the light on binary masks for a generation may finally have outlived its usefulness, with interest now turning to opaque OMOG for 32nm generation and beyond photomask technology, explains Toppan Photomasks' Franklin Kalk, in an exclusive interview with SST.

08/15/2008  August 15, 2008 -- Northwestern University nanoscientist Chad A. Mirkin has mass-produced the 2008 Summer Olympics logo -- 15,000 times in one square centimeter of space. Mirkin and his colleagues printed the logos, as well as an integrated gold circuit, using a new printing technique called Polymer Pen Lithography (PPL), that can write on three different length scales using only one device.

08/06/2008  In a post-SEMICON West interview, Edward Charrier, VP/GM of KLA-Tencor's process control information division, described the latest improvements in Prolith, the company's venerable litho simulation tool.

08/06/2008  August 6, 2008 -- Carl Zeiss SMT made several new product announcements at the recent Microscopy and Microanalysis Meeting and Exhibition in Albuquerque, New Mexico. Among them are a new class of SEM, and an additional Argon ion beam column in its NVison 40 CrossBeam workstation.

08/04/2008  Memory concerns aside, there's still reason to be happy with growth in the semiconductor industry, mainly thanks to emerging markets' hunger for PCs and mobile phones, according to the latest data from the Semiconductor Industry Association (SIA).

07/31/2008  Gartner and VLSI Research analysts tell SST what's the driving interest behind KLA-Tencor's proposed acquisition of Vistec Semiconductor Systems' inspection business, and where areas of overlap might be leveraged to take on other sector competitors.

07/25/2008  Double patterning was the talk of the litho panels during SEMICON West and in pitches by top scanner makers ASML, Canon, and Nikon -- but still none have evolved their tools to offer the required overlay capability, with throughput sufficient to be profitable. Even the closest one of the bunch is billed as the "ultimate" single-patterning tool.

07/24/2008  Execs from ASML and Applied Materials tell SST what's driving the re-emergence of memory as a driver for IC manufacturing, and how this trend is impacting development and adoption of new technologies such as double-patterning and EUV lithography.

07/23/2008  Concerns about the next steps in device scaling -- profitability at 32nm and beyond, challenges of double-patterning, worries about chipmakers' commitment to design-tool functionality -- were aired out in a SEMICON West TechXpot discussion.

07/22/2008  The second-generation SUSS MA300, from SUSS MicroTec is a highly automated mask aligner platform for 300-mm and 200-mm wafers. Specifically designed for 3D packaging, it features a dedicated alignment kit for creating 3D interconnects for applications like chip stacking and 3D image sensor packaging. It also targets wafer bumping and wafer level packaging (WLP) applications, but can be used for other technologies where geometries in the range of 5 and 100 µm must be exposed.