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The ConFab Preview

The agenda is set for The ConFab, to be held May 14-17, 2017 in San Diego at the iconic Hotel del Coronado. While reviewing the abstracts for just the Monday morning session, it struck me how well our speakers will cover the complex opportunities and challenges facing the semiconductor industry.

In the opening keynote, for example, Hans Stork, Senior Vice President and Chief Technical Officer, ON Semiconductor we will discuss the challenge to realize high signal to noise ratio in small (read inexpensive) and efficient form factors, using examples of image sensors and power conversion in automotive applications. “It seems that at last, after many decades of exponential progress in logic and memory technologies, the “real world” devices of power handling and sensor functions are jointly enabling another wave of electronics progress in autonomously operating and interacting Things,” he said.

Next, Subramani Kengeri, Vice President of CMOS Platforms Business Unit, GLOBALFOUNDRIES, will describe how the rapid growth of applications in the consumer, auto and mobile space coupled with the emergence of the Internet of Things (IoT) is driving the need for differentiated design and technology solutions. “While die-cost scaling is slowing down and power density is emerging as a major challenge, fabless semiconductor companies are hungry for innovation using application optimized technology solutions. Specifically, emerging SoC innovations are driving the need for low-power, performance, cost, and time-to-volume that solves the issues of voltage scaling and integration of “user-experience” functions,” he notes.

Islam Salama, a Director with Intel Corporation responsible for packaging substrate Pathfinding of the high-density interconnect across all Intel products, looks at it from a connectivity perspective. “The pervasive nature of computing drives a need for connecting billions of people and tens of billions of devices/things via cloud computing. Such connectivity effect will generate tremendous amounts of data and would require a revolutionary change in the technology infrastructures being used to transmit, store and analyze data,” he said.

Next-generation electronics will require several new packaging solutions, he adds. Smaller form factors, lower power consumption, flexible designs, increased memory performance, and-more than ever, a closely managed silicon package, co-optimization and architectural innovations. Heterogeneous integration through package with technologies such as system in package (SIP), on package integration (OPI) and fan-out (WLFO and PLFO) are poised to change the packaging industry and play a disruptive role in enabling next generation devices.

Heterogeneous Integration is also the focus of a talk by Bill Bottoms, Chairman and CEO, Third Millennium Test Solutions. Bill will report on the collaboration in the making of the HIR Roadmap to address disruptive changes in the global IT network, the explosive growth coming for IoT sensors and the multi-sensor fusion and data analytics that extract “awareness” from the expanding data.

I’m very much looking forward to these and many other talks this year, and the exciting panel discussions and networking events we have planned.

The New Driver for Semiconductor Tech

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Over the past 40 years, the electronics industry has gone through three distinct stage or “waves” of evolution. Last year, in a Solid State Technology webcast presentation, Intel’s Islam Salama described the waves and how the latest wave is driving the semiconductor industry in new and very different ways. Dr. Salama is responsible for packaging substrate pathfinding of high density interconnects across all Intel products. His team focuses on packaging substrate architectures, process and materials technology building blocks, intellectual property management, and manufacturing ecosystem development.

The first wave occurred in the 1990s, driven mainly by personal computers and enterprise servers. The 2000s saw the very wide adoption of smartphones and cellular phones. “This really provided a very solid platform for industry growth, Salama said.

But today, a major shift is under way. “Starting in 2010, we started to see a generational shift in the IT architecture. This shift is really reshaping every aspect of our economy and industry, and defining the opportunities that are available for growing the industry moving forward,” he said. This shift – you guessed it – is driven smart devices, cloud computing and the IoT.

“As we experience pervasive computing behavior, we demand consistency and seamless interface among all our devices as we use them throughout the day,” Salama said. “It becomes a cycle. The more pervasive computing becomes, the more demand there is on the cloud and the data center. In the process, you create new application and you try to come up with new devices that keep up with the applications, and the cycle feeds on itself.”

The IoT will bring an explosion of data.

Big and small data being generated by the IoT and smartphones is seen as the next big disrupter. In Wave 2 (the 2000s), PCs generated 90 MB/day and smartphones 30MB/day. In Wave 3, the numbers jump dramatically. A connected car, for example, will generate 4TB of data/day, a connected plane, 40TB/Day and a connected factory 1 PB/Day (petabyte (PB) is 10¹⁵ bytes of data).

“Such an explosion of data, driven by our behavior as consumers and the emergence of new applications, will really challenge the infrastructure of the entire network as we know it today,” Salama said.

For example, all the sophisticated data analytics that are performed today at the data center need to be pushed downstream. This is particularly true for applications that will become very sensitive to data latency, for example, such as autonomous driving or connected hospitals.

“This is really shaping the future to be concentric around big data, and this is the main reason why data is being viewed today in the industry as the next disruptor and the engine for driving the semiconductor and the information and computing technology moving forward,” Salama said.

No technical barriers seen for 450mm

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Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. Speaking at the SEMI ISS meeting in January, Farrar showed impressive results from, etch, CVD, PVD, CMP, furnaces, electroplating, wet cleans and lithography processes and said the inspection/metrology tools were in place to measure results. “I don’t believe we will find fundamental technology limiters,” he said. “But we will have to keep working to find ways to maximize the efficiency.” Gaining such efficiencies are critical in order to meet the cost-saving goals of the program. “In the end, if this isn’t cheaper, no one is going to do it,” he said.

G450C is a consortium based at the CNSE campus in Albany, NY. It is financed by Intel, TSMC, Samsung, IBM, GLOBALFOUNDRIES, and New York State (CNSE). “Our job is to make it as easy as possible to innovation and be collaborative between the semiconductor makers and our key friends in the industry who enable the 450 work to be done in an economic way,” Farrar said.

At the end of 2013, G450C at 34 tools delivered to its 50,000ft² fab in Albany, with another 7 tools in place at partner’s facilities. “The FOUPS are going, the overhead transport is well underway and some of the cleanroom is actually starting to look like a cleanroom,” Farrar said.

Farrar started with etch results, saying they were “starting to see some pretty good data – 3 sigma at about 2%. Yes, there’s still some work to get to the very edge of the wafer but relatively good progress and good jobs on gas delivery, etc.

He showed good results with both oxide and silicon nitride CVD, with close to 1.5mm edge exclusion. “It’s very representation data from early in the program,” Farrar said, noting that they were starting to pattern some of the more complex oxides.

He said the goal for PVD was to demonstrate better than 5% uniformity. “We know we have step coverage challenges for both the 10 and 7nm nodes. There’s tremendous work going on in the injection rings for gases, high density plasmas from multiple RF sources, but again some progress to me made but pretty good data for right out of the chute,” he said.

CMP results demonstrated repeatability less than 4%. “Very good job done by our suppliers,” Farrar said.

Farrar described data from furnaces as reasonably good. “We still need to do more characterization at what I call the micro level,” he said. “We see some hot spots on the edge, but we’re starting to work on those.”

Also “pretty good data” from electrochemical plating (ECP) of copper. “Well done here,” Farrar said. “The challenge is thermal and pattern loading effects, and gap fill.”

More of the same with wet cleans. “We’re starting to see some pretty good particle data. We’re cleaning wafers relatively well. We are seeing a few things like what I would call micro-metallic contamination that can grow some things so we’re still working on that. But from a particle removal standpoint, pretty good unit process work,” Farrar said.

Farrar acknowledged that lithography remained as one of the biggest challenges in the 450mm transition, but showed good results from directed self assembly across a 450mm wafer, and said the consortium had a very strong partnership with Nikon. “We’re working with them and we’ve seen some tremendous progress at their factory,” he said. “I’m fully confident that we’ll have capability by July to run patterned wafers. Immersion is going to be the workhorse. I think that’s a key enabler to get to 450mm.” He said the industry would have to see how the economics of EUV played out later in time. “I don’t think it’s going to be early in time,” he said.

Farrar seemed to draw hope from the earlier transition from 200mm to 300mm wafers, which started around 1998. “By 2008, we were getting more than 2X the number of wafers per tool out compared to what was going in 2003. There was about a 70% improvement over 5 years,” he said.