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IBM’s Jeff Welser to Keynote The ConFab 2019

AI was a big focus on The ConFab and 2018 and we will continue that theme in 2019 with a keynote talk by IBM’s Jeff Welser.
The ConFab 2019 will return to The Cosmopolitan of Las Vegas on May 14-17. In 2018, AI and other leading technologies were discussed by speakers from IBM, Google, Nvidia, HERE Technologies, Silicon Catalyst, TechInsights, Siemens and Qorvo, among many others.

AI, which represents a market opportunity $2 trillion on top of the existing $1.5-2B information technology industry, is a huge game changer for the semiconductor industry. In addition to AI chips from traditional IC companies such as Intel, IBM and Qualcomm, more than 45 start-ups are working to develop new AI chips, with VC investments of more than $1.5B. Tech giants such as Google, Facebook, Microsoft,
Amazon, Baidu and Alibaba are also developing AI chips.

As Vice President and Lab Director at IBM Research – Almaden, Dr. Welser oversees exploratory and applied research. Home of the relational database and the world’s first hard disk drive, Almaden today continues its legacy of advancing data technology and analytics for Cloud and AI systems and software, and is increasingly focused on advanced computing technologies for AI, neuromorphic devices and quantum computing. After joining IBM Research in 1995, Dr. Welser has worked on a broad range of technologies, including novel silicon devices, high performance
CMOS and SOI device design, and next generation system components. He has directed teams in both development
and research as well as running industrial, academic and government consortiums, including the SRI Nanoelectronics
Research Initiative.

Dr. Welser will describe how making AI semiconductor engines will require a wildly innovative range of new materials, equipment, and design methodologies. To get to the next level in performance/Watt, innovations being researched at the AI chip level – at IBM and elsewhere — include:
low precision computing, analog computing and resistive computing.

Additional industry experts adding to The ConFab 2019 Agenda will be announced soon.

About The ConFab
The ConFab, now in its 15th year, is the premier semiconductor manufacturing and design conference and networking event that brings notable industry leaders together to connect and collaborate. For more information, visit www.theconfab.com. To inquire about participating, if you represent an equipment, material or service supplier, contact Kerry Hoffman, Director of Sales at [email protected]; contact Sally Bixby at [email protected] about attending as a guest.

AI Focus of The ConFab

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Artificial Intelligence will be a focus of The ConFab 2018, to be held May 20-23 at The Cosmopolitan of Las Vegas. We’ll hear from a variety of speakers on why A.I. is so important to the semiconductor industry, not only in terms of the new types of chips that will be required, but how A.I. will bring dramatic improvements to the semiconductor manufacturing process.

“The exciting results of AI have been fueled by the exponential growth in data, the widespread availability of increased compute power, and advances in algorithms,” notes Rama Divakaruni of IBM, our keynote speaker. “Continued progress in AI – now in its infancy – will require major innovation across the computing stack, dramatically affecting logic, memory, storage, and communication.”

Rama will explain how the influence of AI is already apparent at the system-level by trends such as heterogeneous processing with GPUs and accelerators, and memories with very high bandwidth connectivity to the processor. The next stages will involve elements which exploit characteristics that benefit AI workloads, such as reduced precision and in-memory computation. Further in time, analog devices that can combine memory and computation, and thus minimize the latency and energy expenditure of data movement, offer the promise of orders of magnitude power-performance improvements for AI workloads.

John Hu, Director of Advanced Technology, Nvidia Corporation will also address AI in a talk titled “The Era of Deep Learning IC Industry Driven by AI, Autonomous Driving and Virtual Reality.” Hu notes that the “big bang” of AI and autonomous driving has driven the IC industry into a new era of rapid growth and innovation. In his talk, Hu will describe how the next 1000 times of improvement requires a new paradigm shift in the collaboration and co-optimizations across the whole industry; from materials, process technologies, design and chip/system platform. In this era that machine(s) can improve themselves by deep learning, hear how the semiconductor industry also needs to have the capability of deep learning for innovation, to stay ahead in the changing competitive landscape.

“Artificial intelligence has brought human beings to a point in history, for our industry and the world in general, that is more revolutionary than a small, evolutionary step,” says Howard Witham, Vice President of Texas Operations at Qorvo, who will speak on the potential of AI in the semiconductor fab. Howard will describe how AI provides predictive maintenance, auto defect and wafer map classification, outlier detection, automated recipe setups based on device requirements and upstream data, and dynamic interpolation and guard-banding.

Please join us for these and other insightful talks, including one from Google’s John Martinis on quantum computing. Visit www.theconfab.com for more information.

Join Us at The ConFab 2018

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The ConFab 2018, to be held May 20-23 at The Cosmopolitan of Las Vegas, is a conference and networking event designed to inform and connect leading semiconductor executives from all parts of the supply chain. Now in its 14^th year, it is produced by Solid State Technology magazine, the semiconductor industry’s oldest and most respected business publication.

The goal of The ConFab this year is to show how today’s semiconductor manufacturers and their suppliers can they best position themselves to take advantage of the tremendous growth the industry is expecting to see in the near future, propelled by a wide array of new applications, including artificial intelligence, virtual and augmented reality, automotive, 5G, the IoT, cloud computing and healthcare.

Here’s a quick look at the agenda as it stands now.

After a welcome reception on Sunday evening, we’ll kick things off on Monday with a talk by IBM’s Rama Divakaruni on “How A.I. is Driving the New Semiconductor Era.” Although A.I. (and associated deep learning and machine learning) is now in its infancy, it will likely to have a major impact on how semiconductors will be designed and manufactured in the future. A.I. will demand dramatic enhancement in computational performance and efficiency, which in turn will drive fundamental changes in algorithms, systems and chip design. Devices and materials will also change.

Following Rama’s talk, we’ll hear from John M. Martinis, Google who heads up Google’s Quantum A.I. Lab. The lab is particularly interested in applying quantum computing to artificial intelligence and machine learning.

After the keynote talks, we’ll hear from a number of industry visionaries, including John Hu, Director of Advanced Technology for Nvidia, Dan Armbrust, Founder and Director of Silicon Catalyst, and Tom Sonderman, President of Sky Water Technology Foundry. On Monday afternoon, invited industry experts, such as Bill Von Novak of Qualcomm will drill down into the applications most critical to semiconductor industry growth, including automotive, networking, healthcare and the IoT.

On Tuesday, the talks will focus on manufacturing trends and challenges with mainstream semiconductor manufacturing the focus of the morning session and advanced packaging the focus in the afternoon. George Gomba, VP of technology research at GlobalFoundries, will provide an update on EUV lithography, followed by Koukou Suu, of Ulvac, a leading expert on materials for phase change memories. Howard Witham, Vice President of Texas Operations, Qorvo, will provide some insights in using artificial intelligence and automation in semiconductor manufacturing.

The advanced packaging session on Tuesday afternoon is organized and sponsored by IEEE CPMT, notably Li Li, Distinguished Engineer, Cisco and William Chen, Fellow, ASE. The semiconductor industry is increased relying on advanced packaging to deliver far more integrated, complex and advanced solutions for different market segments.

On Wednesday, we’ll hear from leading analysts, including Len Jelinek, Senior Director, Semiconductor Manufacturing at IHS Markit, and Jim Feldhan, President of Semico, on market trends and the expected business climate moving forward.

You can register and keep up-to-date by visiting www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For those interested in attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

The ConFab 2018 Update

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A new wave of growth is sweeping through the semiconductor industry, propelled by a vast array of new applications, including artificial intelligence, virtual and augmented reality, automotive, 5G, the IoT, cloud computing, healthcare and many others. The big question facing today’s semiconductor manufacturers and their suppliers is how can they best position themselves to take advantage of this tremendous growth.

Finding answers to that question is the goal of The ConFab 2018, to be held May 20-23 at The Cosmopolitan of Las Vegas. Now in its 14th year, The ConFab is a conference and networking event designed to inform and connect leading semiconductor executives from all parts of the supply chain. It is produced by Solid State Technology magazine, the semiconductor industry’s oldest and most respected business publication.

Kicking things off will be IBM’s Rama Divakaruni, who will speak on “How AI is Driving the New Semiconductor Era.” This is hugely important to how semiconductors will be designed and manufactured in the future, because AI — now in its infancy — will demand dramatic enhancement in computational performance and efficiency. Fundamental changes will be required in algorithms, systems and chip design. Devices and materials will also need to change.

Rama is well position to address these changes: As an IBM Distinguished Engineer, he is responsible for IBM Advanced Process Technology Research (which includes EUV technologies and advanced unit process and Enablement technologies) as well as the main interface between IBM Semiconductor Research and IBM’s Systems Leadership. He is one of IBMs top inventors with over 225+ issued US patents.

We’re also pleased to announce several other speakers at this point. Joining us will be George Gomba, VP of technology research at GlobalFoundries. George has overall responsibility for GlobalFoundries’ semiconductor technology research programs, including global consortia and strategic supplier management (and, like Rama, has a long history at IBM). The focus of George’s talk will be on EUV lithography.

Dan Armbrust, Founder and Director of Silicon Catalyst, the world’s first incubator focused exclusively on semiconductor solutions startups will also be on the dais. A frequent speaker at The ConFab, Dan has a great background, including President and Chief Executive Officer of SEMATECH, IBM VP, 300mm Semiconductor Operations, and Strategic Client Exec for IBM’s Systems and Technology Group.

Another great speaker is Tom Sonderman, President of SkyWater Technology Foundry. Tom also has a great background including GlobalFoundries’ VP of manufacturing technology, and two decases at AMD, where he had global responsibility for development, integration, support and scalability of automation and manufacturing systems in the company’s wafer fabrication and assembly operations. Prior to joining SkyWater, Prior to joining SkyWater, Tom was the group vice president and general manager for Rudolph Technologies’ Integrated Solutions Group. In this position, he created a Smart Manufacturing ecosystem based on big data platforms, predictive analytics and IoT.

We’re so excited about the other speakers we tentatively have lined up, our plans for several thought-provoking panels and much more, so stay tuned. You register and keep up-to-date by visiting www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For those interested in attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

Can we take cost out of technology scaling?

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There is much talk these days about continued scaling, including some recent posts by my colleague Ed Korczynski, in “Moore’s Law is Dead” Part 1 (What?) and Part 2 (When?). At The ConFab in June, keynote speaker, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, talked about scaling, adding some historical perspective. I previously blogged about the “three fundamental shifts” that Patton believes will lead to a bright future for the semiconductor industry.

“We will keep scaling,” he said. “We have shown a tremendous ability to innovate and keep moving that technology forward.”

In the 1990s, Patton notes that life was actually pretty simple. “You brought in a new lithography tool, you scaled the horizontal dimensions, you scaled the vertical dimensions and you got a new technology out. It was better performance, the same power density, and you could do a lot more on the chip,” he said.

Around 2000, we hit the gate oxide limit. “Gate oxide got to be abount three atomic layers. We could have said at that point ‘game over, scaling has ended.’ But guess what, we innovated. We came up with a pretty fundamental shift in ideas which is let’s change the fundamental properties of silicon. If we can strain the silicon, we can enhance the mobility. We can change the gate oxide. We can enhance the coupling between the gate and the channel. And that’s what we get over that last decade. We said let’s go from SRAM to a very high performance eDRAM (embedded DRAM) so we can put a lot more memory next to the processor because we knew memory was a key gating factor for the processor speed. This enabled the personal computing era and smart consumer electronics,” Patton said.

In 2010, we were at another one of these inflection points. “It’s not surprising that the improvements in 20nm are less than people would like because we really reached the end of the planar device era. Again, we were saying ‘game over, we’re done scaling.’ But no, we continue to innovate. The next decade is really about 3D. 3D devices, finFETs, or 3D chip integration,” he added.

Patton said that design technology co-optimization will be a key piece of getting through the next decade. “That will probably take us to about 2020,” he said. At that point we’re going to “hit the atomic dimension limit and we’re going to have to do it all over again. Here, we’re going to get into nanotechnology. Nanowire devices, silicon nanowires, carbon nanotubes, photonics and multi-chip stacking to bring things together. That will enable wearable computing, everywhere connectivity and cognitive computing.”

Patton said the problem is not physics. “We’re going to have solved the physics problems,” he said. “The problem is financial.” Patton showed a chart (below) that depicted the history of our industry from 1980 to present. “What drove the industry was smaller features, which enabled better performance and better cost per function. It enabled new types of applications, and that enabled larger markets. If you look in this time period, there’s about a six order of magnitude improvement in cost per transistor and that enabled a seven order of magnitude increase in consumption of silicon transistors,” he said.

The challenge we’re facing right now is depicted below, showing the compound growth rate reduction and the cost of a circuit. On the x-axis is linear scaling. “We’ve typically targeted about a 0.7X linear scaling, which means from an area perspective, you get about 50% improvement. Note the line, 50%, doesn’t go through 50% improvement because with each new technology, there is some increase in complexity. It might be more like 30% improvement at the die level. If we’re really good and provide some enhancements in the technology, self-aligned processes, things like that, we may get it to 40%. So 30-40% is about the range we’ve been getting in terms of the cost per die improvement as we scale up.

“The challenge we’re facing now is two fold. Number one, we’re struggling to get that 0.7X linear scaling. It might be about 0.8X. And we’re adding a lot more complexity, especially when you adding double and triple patterning .The focus today in innovation has got to be heavily focused on ‘how do we drive cost?’ Not just how do you scale, because scaling would add a lot of extra cost at this point. How do we drive cost down, how do we keep adding value to the technology. The model is changing. Moore’s Law can still hold, but we have to focus on the cost equation. So there’s really two parts. Technology innovation which is focusing on the patterning, focusing on the materials, the processing, and how do we drive that to take cost out of the technology scaling,” Patton said.

Three fundamental shifts

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At The ConFab last week, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, said there is a bright future in microelectronics (I heartily agree). He said that although there seems to be a fair amount of doom and gloom that scaling is ending and Moore’s Law is over, he is very positive. “There are three huge fundamental shifts that are going to drive our industry forward, will drive revenue growth and will force us to keep innovating to enable new opportunities,” he said.

The first fundamental shift is the explosion of applications in the consumer and mobile space. Patton noted examples such as cars that can drive themselves and can detect people and bicyclists and avoid them, smart phones for as little as $25, wearable devices that not only tell you what you’re doing but how you’re doing, and 4K television. “That is an incredible TV system, but it’s going to demand a lot of bandwidth; twice the bandwidth that’s out there today. If you turn on your 4K system, your neighbors are going to start to notice it when they try to access the internet,” he said.

Patton said that it’s estimated that today there are about 12.5 billion devices connected to the internet. That’s expected to grow to $30 billion by 2020. This represents the second fundamental shift commonly known as Big Data. “All these interconnected devices are shoving tremendous amount of data up into the cloud at the rate of 1.5 Exabytes (10¹⁸) bytes of data per month,” Patton said. “And that’s grown by about an order of magnitude in just the last 13 years. The estimate is that in the next 4 years, it’s going to go up another order of magnitude. It’s accelerating.”

The third fundamental shift is with all this data going up into the cloud, the data is almost all unstructured data, such as video and audio. “It’s related data but disconnected. How do we take that data and do something with it? That brings us to analytics and cognitive computing. We have really just started in this arena.”

So there you have it. Three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

IITC: New Materials for Advanced Interconnects

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On-chip interconnects have not been scaling at the same speed as transistors. When TSMC went from 20nm to 16/14nm, for example, they decided to replace the bulk MOSFET with a FinFET, but they left the interconnect stack as is. In part, interconnect scaling has been slow because companies don’t want to make too many major changes at the same time and introduce risk. Costs, of course, are also an issue. “When you’ve got ten layers of metal and let’s say six layers of those are close to minimum pitch, it gets very expensive once you start doing double patterning,” said Dr. Deepak Chandra Sekar, general co-chair of the upcoming 2014 IITC/AMC joint conference. “With the interconnect layers, people want to save litho costs. That’s one reason they are not scaling as much as they used to.”

But the major reason is that it’s difficult to make interconnects much smaller without introducing significant increases in resistivity. “If you scale down and your resistivity goes up exponentially, it can be a problem,” Sekar said. “Copper resistivity shoots up when you scale it down because of surface scattering, grain boundary scattering and interface roughness.”

The 17th annual International Interconnect Technology Conference (IITC) will be held May 21 – 23, 2014 in conjunction with the 31st Advanced Metallization Conference (AMC) at the Doubletree Hotel in San Jose, California. It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: Where are we now and where do we go from here?” on Tuesday, May 20.

Sekar highlighted a number of papers that will be presented this year. Many of them focus on new materials that could lead to reduced resistivity and enable further interconnect scaling. “There is a lot of excitement about carbon and carbon-copper composites eventually replacing copper,” he said. “At IITC this year, we have a couple of papers, one on graphene showing lower resistivity than copper, and then one on carbon nanotubes showing good resistivity as well. They are still a bit far out in the sense that there’s a lot more process integration work that needs to be done because these are proof of concept demos, but they show that there might be more beyond copper.”

In a paper from AIST, titled “Sub 10nm wide intercalated multi-layer graphene interconnects with low resistivity,” work will be presented that demonstrates 8nm wide 6.4nm thick graphene interconnects with a resistivity of 3.2uohm-cm, which is significantly better than copper with similar dimensions. This milestone for graphene interconnect research is expected to motivate the process integration research that is required to take the technology to the next level.

8nm wide graphene interconnects

Carbon nanotubes (CNTs) have been explored as a material for vertical interconnects for many years since they can handle higher current densities than copper and offer ballistic transport. A paper from imec titled “Electron Mean Free Path for CNT in Vertical Interconnects Approaches Copper,” work will be presented that demonstrates a 5x improvement in electron mean free path for CNTs compared to previous work. The CNT mean free path of 24-74nm approaches copper. Contact resistance is improved significantly compared to previous work as well.

Carbon Nanotube (CNT) vias in integrated structures

Another challenge to scaling of interconnects: reliability. Both time-dependent-dielectric-breakdown (TDDB) and electromigration lifetimes for interconnects drop rapidly when scaled. In work to be presented at IITC/AMC, IBM and Applied Materials will present a multi-layer SiN cap process is developed that shows higher breakdown and lower leakage compared to conventional SiCNH caps. Selective cobalt caps in combination with the multi-layer SiN cap are shown to provide a 10x improvement in electromigration lifetimes. Wrap-around cobalt liners in combination with the cap layer schemes are shown to provide a 1000x improvement in electromigration lifetimes. The paper is titled “Advanced Metal and Dielectric Barrier Cap Films for Cu Low k Interconnects.”

10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi-layer SiN cap, cobalt cap and wrap-around cobalt liners.

Of course, an alternative to making everything smaller by scaling is to go 3D. That will be addressed by a variety of papers, including one from CEA-Leti focused on 3D monolithic integration. While most of today’s through-silicon vias (TSVs) are in the 5µm range, monolithic 3D technologies offer TSVs in the 50nm range, which allows dense connectivity between different layers in a 3D-IC. In the Leti paper, such dense connectivity is shown to provide 55% area reduction and 47% energy-delay product improvement for a 14nm FPGA design. Transistor technologies that allow monolithic 3D integration are experimentally demonstrated. “When you make the TSVs smaller and smaller, you can reduce the length of on-chip wires as well by taking what’s on a single now and stacking them into two layers,” Sekar said. “That might save a lot of power and area. There’s been a lot of talk about monolithic 3D, but these are some of the first few experimental demonstrations showing that it’s possible.”

Monolithic 3D-ICs

No technical barriers seen for 450mm

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Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. Speaking at the SEMI ISS meeting in January, Farrar showed impressive results from, etch, CVD, PVD, CMP, furnaces, electroplating, wet cleans and lithography processes and said the inspection/metrology tools were in place to measure results. “I don’t believe we will find fundamental technology limiters,” he said. “But we will have to keep working to find ways to maximize the efficiency.” Gaining such efficiencies are critical in order to meet the cost-saving goals of the program. “In the end, if this isn’t cheaper, no one is going to do it,” he said.

G450C is a consortium based at the CNSE campus in Albany, NY. It is financed by Intel, TSMC, Samsung, IBM, GLOBALFOUNDRIES, and New York State (CNSE). “Our job is to make it as easy as possible to innovation and be collaborative between the semiconductor makers and our key friends in the industry who enable the 450 work to be done in an economic way,” Farrar said.

At the end of 2013, G450C at 34 tools delivered to its 50,000ft² fab in Albany, with another 7 tools in place at partner’s facilities. “The FOUPS are going, the overhead transport is well underway and some of the cleanroom is actually starting to look like a cleanroom,” Farrar said.

Farrar started with etch results, saying they were “starting to see some pretty good data – 3 sigma at about 2%. Yes, there’s still some work to get to the very edge of the wafer but relatively good progress and good jobs on gas delivery, etc.

He showed good results with both oxide and silicon nitride CVD, with close to 1.5mm edge exclusion. “It’s very representation data from early in the program,” Farrar said, noting that they were starting to pattern some of the more complex oxides.

He said the goal for PVD was to demonstrate better than 5% uniformity. “We know we have step coverage challenges for both the 10 and 7nm nodes. There’s tremendous work going on in the injection rings for gases, high density plasmas from multiple RF sources, but again some progress to me made but pretty good data for right out of the chute,” he said.

CMP results demonstrated repeatability less than 4%. “Very good job done by our suppliers,” Farrar said.

Farrar described data from furnaces as reasonably good. “We still need to do more characterization at what I call the micro level,” he said. “We see some hot spots on the edge, but we’re starting to work on those.”

Also “pretty good data” from electrochemical plating (ECP) of copper. “Well done here,” Farrar said. “The challenge is thermal and pattern loading effects, and gap fill.”

More of the same with wet cleans. “We’re starting to see some pretty good particle data. We’re cleaning wafers relatively well. We are seeing a few things like what I would call micro-metallic contamination that can grow some things so we’re still working on that. But from a particle removal standpoint, pretty good unit process work,” Farrar said.

Farrar acknowledged that lithography remained as one of the biggest challenges in the 450mm transition, but showed good results from directed self assembly across a 450mm wafer, and said the consortium had a very strong partnership with Nikon. “We’re working with them and we’ve seen some tremendous progress at their factory,” he said. “I’m fully confident that we’ll have capability by July to run patterned wafers. Immersion is going to be the workhorse. I think that’s a key enabler to get to 450mm.” He said the industry would have to see how the economics of EUV played out later in time. “I don’t think it’s going to be early in time,” he said.

Farrar seemed to draw hope from the earlier transition from 200mm to 300mm wafers, which started around 1998. “By 2008, we were getting more than 2X the number of wafers per tool out compared to what was going in 2003. There was about a 70% improvement over 5 years,” he said.