Tag Archives: Qualcomm

Join Us at The ConFab 2018

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The ConFab 2018, to be held May 20-23 at The Cosmopolitan of Las Vegas, is a conference and networking event designed to inform and connect leading semiconductor executives from all parts of the supply chain. Now in its 14th year, it is produced by Solid State Technology magazine, the semiconductor industry’s oldest and most respected business publication.

The goal of The ConFab this year is to show how today’s semiconductor manufacturers and their suppliers can they best position themselves to take advantage of the tremendous growth the industry is expecting to see in the near future, propelled by a wide array of new applications, including artificial intelligence, virtual and augmented reality, automotive, 5G, the IoT, cloud computing and healthcare.

Here’s a quick look at the agenda as it stands now.

After a welcome reception on Sunday evening, we’ll kick things off on Monday with a talk by IBM’s Rama Divakaruni on “How A.I. is Driving the New Semiconductor Era.” Although A.I. (and associated deep learning and machine learning) is now in its infancy, it will likely to have a major impact on how semiconductors will be designed and manufactured in the future. A.I. will demand dramatic enhancement in computational performance and efficiency, which in turn will drive fundamental changes in algorithms, systems and chip design.  Devices and materials will also change.

Following Rama’s talk, we’ll hear from John M. Martinis, Google who heads up Google’s Quantum A.I. Lab. The lab is particularly interested in applying quantum computing to artificial intelligence and machine learning.

After the keynote talks, we’ll hear from a number of industry visionaries, including John Hu, Director of Advanced Technology for Nvidia, Dan Armbrust, Founder and Director of Silicon Catalyst, and Tom Sonderman, President of Sky Water Technology Foundry. On Monday afternoon, invited industry experts, such as Bill Von Novak of Qualcomm will drill down into the applications most critical to semiconductor industry growth, including automotive, networking, healthcare and the IoT.

On Tuesday, the talks will focus on manufacturing trends and challenges with mainstream semiconductor manufacturing the focus of the morning session and advanced packaging the focus in the afternoon. George Gomba, VP of technology research at GlobalFoundries, will provide an update on EUV lithography, followed by Koukou Suu, of Ulvac, a leading expert on materials for phase change memories. Howard Witham, Vice President of Texas Operations, Qorvo, will provide some insights in using artificial intelligence and automation in semiconductor manufacturing.

The advanced packaging session on Tuesday afternoon is organized and sponsored by IEEE CPMT, notably Li Li, Distinguished Engineer, Cisco and William Chen, Fellow, ASE. The semiconductor industry is increased relying on advanced packaging to deliver far more integrated, complex and advanced solutions for different market segments.

On Wednesday, we’ll hear from leading analysts, including Len Jelinek, Senior Director, Semiconductor Manufacturing at IHS Markit, and Jim Feldhan, President of Semico, on market trends and the expected business climate moving forward.

You can register and keep up-to-date by visiting www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected].  For those interested in attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

Extreme Stress for Existing Foundry/Fabless Model

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Dr. Roawen Chen, senior vice president of global operations at Qualcomm, will provide the keynote talk at The ConFab 2014 this year. The event will be held June 22-25 at The Encore at The Wynn in Las Vegas.

In his talk, Dr. Chen, will describe how the increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. He says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In this talk of “what’s on our mind?” he will deliberate on a number of headwinds and opportunities.

In his role at Qualcomm, Roawen oversees the worldwide operations and supply chain, silicon and package technology, quality/reliability, and procurement functions for the Qualcomm semiconductor business. He has overall responsibility for driving the global integrated fabless strategy and execution.

Roawen is an experienced leader in all aspects of semiconductor operations and supply chain management with a solid background in leading large-scale fabless operations. In addition to his strong technical depth, he has proven experience in building close supplier and vendor relationships and executing to support customer demand and product development. Prior to Qualcomm, Roawen was Vice President of Manufacturing Operations at Marvell Semiconductor in Santa Clara, California. During his more than 12 years at Marvell, Roawen held a variety of leadership roles, including Vice President and General Manager of the Communications and Computing business unit and Vice President and General Manager of the Connectivity business unit. He has also served in management roles in Marvell’s Foundry Operations and Manufacturing Technology groups.

Prior to Marvell, Roawen held technical positions at TSMC-USA and Intel. He earned a bachelor’s degree in Physics from National Tsing-Hua University in Taiwan, a master’s degree in Materials Science from the University of California, San Diego and a PhD in Electrical Engineering and Computer Science from the University of California, Berkeley.

Qualcomm’s Dr. Roawen Chen to keynote at The ConFab

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I’m delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24th. I’m thrilled to have these two visionaries speak to The ConFab audience.

In his role at Qualcomm, Roawen oversees the worldwide operations and supply chain, silicon and package technology, quality/reliability, and procurement functions for the Qualcomm semiconductor business. He has overall responsibility for driving the global integrated fabless strategy and execution.

Roawen is an experienced leader in all aspects of semiconductor operations and supply chain management with a solid background in leading large-scale fabless operations. In addition to his strong technical depth, he has proven experience in building close supplier and vendor relationships and executing to support customer demand and product development. Prior to Qualcomm, Roawen was Vice President of Manufacturing Operations at Marvell Semiconductor in Santa Clara, California. During his more than 12 years at Marvell, Roawen held a variety of leadership roles, including Vice President and General Manager of the Communications and Computing business unit and Vice President and General Manager of the Connectivity business unit. He has also served in management roles in Marvell’s Foundry Operations and Manufacturing Technology groups.

Prior to Marvell, Roawen held technical positions at TSMC-USA and Intel. He earned a bachelor’s degree in Physics from National Tsing-Hua University in Taiwan, a master’s degree in Materials Science from the University of California, San Diego and a PhD in Electrical Engineering and Computer Science from the University of California, Berkeley.

The ConFab will be held June 22-25 at The Encore at The Wynn in Las Vegas.

High cost per wafer, long design cycles may delay 20nm and beyond

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Handel Jones, founder and CEO of International Business Strategies (IBS), spoke at SEMI’s Industry Strategy Symposium last week, focusing on key trends, factors impacting the growth of the industry and the migration to smaller feature dimensions. He is bullish about 2014 and industry innovation, but cautious about how quickly the industry will move to new technology nodes due to higher costs, and long design cycles. Overall, he said he believed semiconductor market growth this year will be slightly better than 2013, due in part to the strength of the global GDP.

Perhaps most surprisingly, he had a fair amount of uncertainly about 20nm.  “Will 20nm be a high tech technology node and when will that occur?” he said. “We’re tracking design starts and design completions and we see a few 20nm designs but not a lot. Frankly, whether 20nm will be big or not will really depend on two customers: one is Qualcomm and the other is Apple.” Handel said “there is a significant challenge in getting lower cost at 20nm” compared to 28nm due to a lack of increase in the gate density and the potential yield impact. “We think 20nm, if it does go into volume production, it will not be in 2014. Potentially 2015 and maybe 2016,” he said.

Similarly, Handel believes there will be a postponement of 16/14nm. “We expect initial production in late 2016, beginning of 2017. That’s for the SoC business. The FPGA markets will be different,” he said. “There will also be delays in 10nm. Delays mean you can’t really go on the 2 year cycle or even the 3 year. I know people will vehemently disagree with that, but if you look at what’s really happening from a design start point of view and also the end customers, I think you’ll agree with our conclusion,” he said.

“If you look at the reality of the industry, 28nm high-k metal gate went into high volume production toward the end of 2013,” said, adding that they define high volume as 10% of the output. “It took almost 4 years for 28nm high-k metal gate to go into high volume production. Now we’re basically starting 20nm. Even if the fabs are ready what you have is the design cycle time. Preparing libraries and IP can take six months at least. Doing a complex design in 20nm can take you at least a year. Validating the design can take you another half a year. If it’s a modem, and you need approval from the carriers, that’s another half a year. Even if the fab is ready, you start these things and it’s two years,” he said. “We have an industry that is trying to adopt three technologies in three years. It’s impossible,” he said. “It’s not realistic from an infrastructure point of view, even if it the fabs are there, for three technology nodes to ramp in three years.”

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Handel said that application processor (AP)/modem design can cost about $450-500 million in 16/14nm, with a timeframe of around 18 months. “You need 10X revenue so for that design, so if you’re spending $450 million, you need $4.5 billion in revenue. A few companies can get that, but not many,” he added.

“The economics of the industry are forcing changes. You’ve seen them already. The long ramp up time for 28nm HKMG, and 20nm with double patterning is clearly a major challenge from a technology point of view, and a bigger challenge from a cost point of view. FinFETs will be an even bigger challenge. Intel is having delays in their 14nm FinFETs, whether in high volume at 22nm, how will companies that have never done FinFETS before, how will design companies that have never designed in FinFETs before, how will they ramp faster?” he asked.

 Not surprisingly, Handel also had a dim outlook for 10nm. He estimates that 10,000 wafers/month at 10nm will cost more than $2billion. “If you want to install 40,000 wafers/month, it’s going to be an $8 billion bill. If you want to install 100,000 wafers/month, it’s going to be $20 billion. Even before you get to 450mm, it’s going to be significantly more capital intensive,” he said.

Just looking at the location of the headquarters of semiconductor companies, he said the U.S. was still strong, but there was also strong growth from Korea – mostly in the form of Samsung – but also China and Taiwan. “We see a relatively flat Europe and then a continuing decline in Japan. In fact, we don’t see Japan strengthening unless we see some major changes,” he said.

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That also has an impact in terms of the technology requirements. In terms of minimal dimensions, Handel most of the advanced technology designs are in the U.S., with advanced technology defined as being 28, 20 and now starting 16/14nm. “In developing countries, many of the designs are still at 40nm. 28 is a new technology and the next technology after 28 is going from polysilicon up to high-k metal gate,” he said.

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Handel also sees uncertainly in the use of FinFET devices due to higher wafer cost. “We see quite a few new designs. The problem again is the cost per wafer. For 28nm, we have about $2600 and for 20nm we have about $3200 and for 16/14 we have about $4000. You now have this increasing cost per wafer and can you get the higher gate density and can you also get higher parametric yields?” he asked.

Handel said the gate utilization is an issue because of limitations of the design tools and parasitic effects. “The other factor is parametric yields, which are strictly tied into leakage control for the 20nm and of course for the 16nm FinFETs,” he said. “You can break this. Intel has shown that it can be broken and of course that’s an excellent achievement. But, it’s based on very high design costs, potentially $1 billion per design, so you need $10 billion in revenue. It also takes a number of years,” he said. He noted that, in the smartphone market, designs move very fast. “You can’t make that kind of investments in designs.”