Semiconductors

SEMICONDUCTORS ARTICLES



EVG expands HQ, hiring 100

07/27/2011 

EV Group (EVG), wafer bonding and lithography equipment supplier, began a manufacturing capacity expansion at its Austrian headquarters, adding floorspace, equipment, worker comforts, and a state-of-the-art visitor area. EVG will hire about 100 new staff members as part of the expansion.

Green wafer fab chemistries that work

07/27/2011 

ATMI's SVP/CTO, Larry Dubois shares the 3 guidelines ATMI keeps in mind when designing eco materials for semiconductor wafer fab, and gives an update on the materials supplier's LED fab products.

Wall Street view: Top takeaways from SEMICON West

07/26/2011 

A trio of analysts who participated in SEMICON West's Bulls/Bears panel have some top-takeaways list for the industry: why WFE spending is slow, why it's only a short pause, and which will comes first, EUV or 450mm.

TSV zen comes down to wafer processing balance

07/26/2011 

3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.

NAND value threatens DRAM market

07/25/2011 

NAND flash is a serious threat to the DRAM memory industry in PCs, according to Objective Analysis, which reviewed a series of nearly 300 PC benchmarks.

Suss MicroTec 3D IC workshop addresses thin wafer handling and testing

07/25/2011 

At SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.

ASM covers FinFET precursor needs from epitaxy to HKMG ALD

07/22/2011 

ASM International's Bob Hollands discusses the challenges of making FinFET structures using both epitaxial and high-k/metal gate (HKMG) atomic layer deposition (ALD) processes.

First Semiconductor Fab for Central and South America Gains Design Approval

07/21/2011 

A four-month fab design verification project was approved for CEITEC S.A., for what is said to be the first semi conductor manufacturing facility to be built in Central and South America. CEITEC S.A. is a Brazilian company that produces application-specific standard products (ASSPs) for RFID, wireless communication and digital multimedia. The design verification project was overseen by Lotus Technical Services, one of five operational divisions of the LotusWorks based in Sligo, Ireland.


Sokudo litho breakfast: Challenges for the 2Xnm node

07/20/2011 

CEA-Leti's Serge Tedesco and Didier Louis summarize key themes from the Sokudo lithography breakfast forum held last week at SEMICON West.

Litho readiness for next-gen logic, flash, and DRAM

07/19/2011 

Franklin Kalk, Toppan Photomasks, covers the major lithography demands of distinct semiconductor technologies: Logic, Flash, and DRAM. He also gives an update on fabless/foundry options, and Japan's earthquake recovery.

SEMICON West workshop addresses stress management for 3D ICs using TSVs

07/19/2011 

Speakers at a SEMATECH/Fraunhofer-hosted workshop at SEMICON West looked at stress management for 3D ICS using TSVs: the state of reliability testing, failure analysis techniques, and why an engineering paradigm shift is needed.

Translucent demos LED growth via one-step epitaxy with rare earth oxides on Si

07/18/2011 

Translucent demonstrated its Mirrored Si technology on a 100mm-diameter wafer that exhibits high reflectivity using a lattice-matched REO material grown on a Si substrate, capped by a GaN layer that can support further nitride epitaxy for LED structure growth.

How EVG accomplished the 1st 450mm printed wafer; HVM expected 2015-2017

07/18/2011 

SEMATECH announced a 450mm imprinted wafer, accomplished by EV Group (EVG). Markus Wimplinger, EVG, described the timeline for the 450mm effort and how the company decided to make a strategic move.

SigmaTech TSV metrology wins Best of West

07/15/2011 

SigmaTech's UltraMap-TSV system won Best of West at SEMICON West, presented by industry association SEMI and Solid State Technology.

Gigaphoton's EUV debris mitigation tech acheives 93% Sn removal

07/15/2011 

Lithography light source maker Gigaphoton Inc. verified its original technology for mitigating debris with magnetic fields for laser-produced plasma (LPP) light sources, clearing a hurdle for mass-production use.

Replisaurus advanced Cu metallization process nears commercialization at Leti

07/15/2011 

CEA-Leti and Replisaurus Technologies will begin applying Replisaurus' ElectroChemical Pattern Replication (ECPR) metallization process to customer target products, following a near-100% yield master.

SEMATECH survey on 2.5D, 3D IC; gaps in the via-mid ecosystem

07/14/2011 

Sitaram Arkalgud, director of interconnect at SEMATECH, discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. Standards are also covered.

A lithography-rich Day 2 at SEMICON West

07/14/2011 

Intermolecular's George Mirth reports on interesting keynote speeches and comments from the Sokudo Lithography Breakfast at SEMICON West, in talks from ASML, Nikon, Mapper, Xtreme, and imec.

450mm update: Participation rising, patterning defined, “low risk” determined

07/14/2011 

Updates from ISMI's 450mm industry briefing at SEMICON West reveal intensifying participation and development underway for most required capabilities, and evaluations showing "low risk" for factory integration.

Trigate transistors vs FDSOI

07/14/2011 

Dick James, ChipWorks, speaks about Intel's presentations on strain engineering and lithography masks for trigate transistors, and the industry split between FDSOI and trigates.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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