04/05/2011 

TowerJazz is looking to buy Micron Technology's semiconductor fab in Nishiwaki City, Hyogo, Japan. The proposed purchase would nearly double TowerJazz's current internal manufacturing capacity, increasing production by 60,000 wafers per month, and set up a supply agreement between the companies.

04/05/2011 

University of Illinois researchers found that graphene transistors have a nanoscale thermoelectric cooling effect that can be stronger at graphene contacts than resistive heating, lowering the temperature of the transistor.

04/04/2011 

Longtime semiconductor exec Takeshi Hattori continues his reporting on the aftermath of the massive Japanese earthquake and tsunami, with updates on the nuclear crisis, advice on traveling to Japan, and the current status of facilities and production struggles.

04/04/2011 

SiliconBlue Technologies unveiled its mobileFPGA platform device roadmap using TSMC's 40nm low power standard CMOS process. The two distinct families target the two areas where smartphones and other handhelds differentiate.

04/04/2011 

A team of researchers from Harvard University and Zena Technologies, led by Kenneth B. Crozier, demonstrated that individual, vertical silicon nanowires can shine in all colors of the spectrum. The Si nanowires are fabricated via e-beam lithography and inductively coupled plasma reactive ion etching.

04/04/2011 

Thin Film Electronics ASA (Thinfilm) and PARC, a Xerox company, entered the next phase of their co-innovation engagement for printed memory devices. This next phase extends the engagement to prototyping the product for manufacturing readiness.

04/04/2011 

GLOBALFOUNDRIES, semiconductor foundry, signed a strategic long-term partnership on sub-22nm CMOS scaling and GaN-on-Si technology with the nanoelectronics R&D center imec.

04/01/2011 

Advanced solid state non-volatile memory (NVM) chips, which retain data when the power is off, are expected to see phenomenal growth in the next five years, says iRAP Inc. In 2010, the potential market for zero capacitor (ZRAM) was highest, but by 2015, it will be phase change memory (PCM, PC-RAM, PRAM, OUM) at the lead.

04/01/2011  Surface clean engineers must discover new methods to realize contamination and surface termination requirements at each step of the manufacturing process, while simultaneously considering the impact to health, cost and the environment. Joel Barnett, SEMATECH, Austin, TX, USA

04/01/2011  Peter Singer, Editor-in-Chief

04/01/2011  Phil Garrou, Contributing Editor

04/01/2011  The Cleaning studies of silicon wafers in DI water in both conventional wet-bath and a single-wafer cleaning tool clearly show that pumping methods have a strong influence on process performance. R. Prasanna Venkatesh, Jung-Soo Lim, Jin-Goo Part, Hanyany University, Ansan, Korea

03/31/2011 

Renesas Electronics America will sell its semiconductor wafer fabrication facility in Roseville, CA, to TELEFUNKEN Semiconductors International LLC. TELEFUNKEN will use the 200mm, 8" line at the Roseville factory to manufacture its own analog/mixed-signal, HV products, Renesas products, and jobs for strategic foundry partners.

03/31/2011 

Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.

03/30/2011 

Every top-10 wafer-fab equipment supplier in VLSI Research's annual rankings remained on the list in the new 2010 version, but there were some position changes.

03/30/2011 

austriamicrosystems (SIX:AMS) conditionally released its advanced 0.18µm High-Voltage CMOS process technology "H18" to for volume production. It will be manufactured in IBM's 200mm Burlington wafer facility.

03/30/2011 

Mechanical stresses can prevent successful implementation of 3D packaging technologies, says Larry Smith, SEMATECH. He argues for a DFM-like solution to identify and manage stress on thinned and stacked die in 3D ICs. To complicate matters, foundries, OSATs, and memory suppliers could inflict different stresses on the die, and the whole industry is too new at 3D packaging to present concrete answers.

03/30/2011 

Technology, not physics, represents the major hurdle to allow graphene to step out of the lab and pave the way to the future of technology: either alone, or hand-in-hand with silicon. Mirco Cantoro, imec, enumerates graphene’s challenges and potential in microelectronics, high-speed/HF electronics, and flexible/plastic electronics.

03/30/2011 

Defect source analysis (DSA) and spatial signature analysis (SSA) go beyond process control to determine where in the process defects are introduced, which defects are common from one process step to the next, how defects propagate throughout the production line, and defect signatures and causes. John Robinson, KLA-Tencor, offers examples of defects and how these can be missed or mis-identified, wasting wafers and time.

03/30/2011 

Mentor Graphics (MENT) says many of its EDA customers are designing, verifying, manufacturing and testing integrated circuit products using multi-die vertical stacking technology, 3D-IC. The company is deploying a multiple-component Tessent design-for-test product line for integrated multi-die hierarchical scan and built-in self-test  methodologies.