Semiconductors

SEMICONDUCTORS ARTICLES



Gate structure and 3D stacking winners will determine semiconductor industry direction

01/11/2011 

Arthur W. Zafiropoulo, Ultratech, sees the 20/22nm node as a competition for gate-first and gate-last proponents to discover which will lead the semiconductor industry. Device makers that master TSV chip stacking will be the winners over the course of this decade, he says. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

Enabling lithography for the 22nm node

01/11/2011 

Single-exposure patterning schemes are unable to meet 22nm specifications, which leads fabs to use double-patterning like LELE. However, below 22nm, a simple multiplication of double-patterning is exceedingly difficult. Alternative processes like tone reversal, EUV, and resist freezing are under development, says Nick Pugliano, Dow Electronic Materials. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

Materials forecast for 22nm devices

01/11/2011 

Weimin Li, ATMI, looks at changes in the materials side of wafer fab that might occur in 2011, especially for advanced DRAM devices. For every evolutionary change or radical new method, cost and performance considerations are high. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

China WLCSP established R and D subsidiary in CA

01/10/2011 

China WLCSP Co. Ltd., provider of wafer level (WLP) miniaturization technologies for the electronics industry, confirmed its commitment to the US market with the opening of a new R&D center in Sunnyvale, CA.

Materials modification with HfO for next-gen semiconductor devices

01/10/2011 

Scaling semiconductor devices without FDSOI, FinFETsFor the near-term, i.e., extending scaling for one or possibly two more generations below 22nm, Glen Wilk, ASM America, is keen on using materials modification to do the job. He views it as a simple near-term solution from a manufacturing standpoint, given the semiconductor industry's experience with hafnium oxide (HfO), which is already in production.

FDSOI-20nm-Leti-researchers-on-future-transistors

01/10/2011 

At the recent IEDM 2010 conference, Leti's Olivier Faynot, Innovative Devices Laboratory leader, discussed planar fully-depleted SOI (FDSOI) technology with Debra Vogler, senior technical editor.

Addressing defectivity will require new surface-engineering processes at 22nm

01/10/2011 

Gilles Baujon, CEO of Nanoplas, explains how the industry's migration toward the 32nm and 22nm nodes will require development of new process integration schemes, device structures, new materials assemblies -- and thus innovative surface-engineering solutions.

Analysis: Samsung's lower 2011 capex plans

01/07/2011 

Samsung's announced 2011 investment plans, while still at record levels and growing across all its business areas, seem to be falling short of expectations in the semiconductor segment. Barclays analyst CJ Muse combs through the data to see what the implications are.

Ziptronix accuses Omnivision, TSMC of patent infringement

01/07/2011 

Dr. Phil Garrou takes a closer look at an IP dispute lobbed by Ziptronix against Omnivision and TSMC over low-temperature oxide bonding, used in making backside-illumination CMOS image sensors.

CyberOptics Semiconductors vibration monitoring software

01/07/2011 

CyberOptics Semiconductors updated its wafer vibration monitoring softwareCyberOptics Semiconductors updated its wafer vibration monitoring software, offering new capabilities for data analysis and third-party data interfaces. CyberOptics’ AVS 2.0 vibration monitoring software provides engineers with the data needed to predict equipment failures related to vibration during semiconductor fabrication to improve process yield and cycle times.

Low-resistance wiring and 2Xnm void-free fill with CVD ruthenium liner and direct seed copper

01/06/2011 

Direct seed copper for semiconductor fabricationJonathan Rullan et al compare resistance from chemical vapor deposited (CVD) ruthenium liners and direct seed (DS) copper used with advanced Electrofill processes to conventional methods, using different annealing temps and simulated back-end-of-line (BEOL) thermal stress builds. 2X nm trenches were shown to have complete gap fill, eliminating the need for conventional PVD Cu seed.

Powerchip standardizes on SpringSoft Laker custom IC layout for high-density memory chips

01/05/2011 

SpringSoft Inc., a global supplier of specialized IC design software, announced that Powerchip Technology Corporation, a memory solution company based in Taiwan, has selected the Laker Custom Layout Automation System as the standard platform for memory chip design.

IEDM Reflections, last day: Novel process technologies

01/04/2011 

Michael A. Fury of Techcet blogs about the papers he saw at IEDM 2010. The final afternoon continued with 4 parallel sessions and the halls and conference rooms were as crowded as they had been all week. I was compelled to spend nearly all of my time in the novel process technologies session.

Leti-on-More-than-Moore-for-RF-filters

01/03/2011 

Engineered substrates and 3D integration technology based on direct bonding for future More Moore and More than Moore integrated devicesFor the "more than Moore" domain, Leti researchers at IEEE’s IEDM 2010 focused on RF applications in the paper #2.6, "Engineered substrates and 3D integration technology based on direct bonding for future More Moore and More than Moore integrated devices." Laurent Clavelier, head of solar technologies department at Leti, discusses the RF research with Debra Vogler.

ONNN_completes_SANYO_buy

01/03/2011 

ON Semiconductor Corporation (Nasdaq: ONNN) completed its acquisition of SANYO Semiconductor Co., Ltd., a subsidiary of SANYO Electric, and other assets related to SANYO Electric’s semiconductor business.

22nm Challenges Abound for 2011

01/01/2011  Pete Singer Editor-in-Chief

The Forecast for 2011: Back to Reality

01/01/2011  2010 was perhaps the best year ever for the semiconductor industry, a nice rebound from the worst year ever. 2011 will likely be a year when the semiconductor industry returns to "normal", with more moderate, single-digit growth. Cyclicality is expected to continue. Here's what leading industry analysts are saying about the year ahead.

Potential opportunities for nanotechnology in electronics manufacturing

01/01/2011  At this point, the NRI program has not yet identified any single, most-promising candidate for a beyond CMOS nanotechnology, but there may eventually be several, spanning and extending the wide range of applications that CMOS FETs currently continue to address very well. Robert Doering, Texas Instruments, Dallas, Texas, USA

22nm: the node of diminishing returns?

01/01/2011  Steve Lerner, CEO, Alchimer, Massy France

Wafer level packaging of image sensors

01/01/2011  Wafer-level packages that use a glass cover over the package cavity and through-silicon vias to interconnect the die bond pads satisfy the packaging requirements for CMOS image sensors: compact, reliable, low cost, and accommodate both front- and back-illuminated image sensors with no external changes. Giles Humpston, Tessera Inc., San Jose, California, USA




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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