Semiconductors

SEMICONDUCTORS ARTICLES



Wafer-level Probe Operating Environment

12/11/2008  The ProberBench Operating Environment, from SUSS MicroTec Test Systems, is a full-featured software suite designed for efficient, intuitive and safe wafer-level probing. The ProberBench Operating Environment, from SUSS MicroTec Test Systems is a full-featured software suite designed for efficient, intuitive and safe wafer-level probing. Development of the interface and architecture was reportedly based on a three-month user study in the laboratories semiconductor design houses and manufacturers.

SEMI: 500K jobs at risk with EU chip decline

12/11/2008  In a pre-emptive measure to avert an increase in unemployment throughout Europe, SEMI is appealing to EU and national policymakers to invest in Europe's semiconductor industry, citing its importance to the health and global competitiveness of the EU economy.

ASML "double-dips" with updated litho tool

12/10/2008  MLW peers under the hood of ASML's new NXT 1950i with company exec Frank van de Mast to understand the platform's benefits for double-patterned immersion litho, as well as leading-edge single patterning and spacer-layer DPT applications, and even EUV.

High-powered Ultra-violet Laser

12/09/2008  The Q304-HD laser from JDSU is a high-powered ultra-violet (UV) laser based upon the company's Q Series UV laser platform. This laser reportedly provides 50% more power and is designed to increase throughput, or the rate at which it conducts micromachining functions such as hole drilling, wafer cutting or singulation, and solar cell processing.

A measurement method for wafer-level 1/f noise

12/09/2008  In MOSFETs used for analog and RF circuits, 1/f noise is an important figure of merit. This article describes a wafer-level measurement method and setup to evaluate the 1/f noise of MOSFETs, which can be automatically performed on the wafer and can measure <100Hz low-frequency noise components.

Making scanners march in step

12/09/2008  Brion Technologies, an ASML company, has developed a suite of products to optimize the performance of diverse scanners so that challenging chip patterns can be manufactured in parallel, on old and new tools, at high volume.

Analyst: Foundries face "historical lows" in utilization

12/06/2008  Wafer shipments at the world's top two foundries, TSMC and UMC, are set to plunge further than anticipated in 4Q, but the picture for 1Q is even uglier with "historic lows" looming for utilizations, according to an analyst report.

ALD NanoSolutions receives patent, and small business technology transfer grant

12/02/2008  December 2, 2008: The University of Colorado< has been awarded U.S. Patent number 7,426,067 "Atomic layer deposition on micro-mechanical devices," which has been exclusively licensed to ALD NanoSolutions Inc.

Cambridge NanoTech expands management team

12/02/2008  December 2, 2008: Cambridge NanoTech, a leader in atomic layer deposition (ALD) science and equipment for research and industry, has expanded its leadership team with the promotion of Dr. Ganesh Sundaram to vice president of technology and Roger Coutu to vice president of engineering.

Report: Merger imminent for China's Hua Hong NEC, Grace Semi

12/02/2008  Chinese foundries Hua Hong NEC (HHNEC) and Grace Semiconductor Manufacturing Corp. are finalizing merger plans in the next few weeks, according to a report by Digitimes citing a local chip industry group.

Elpida boosting Rexchip JV stake

12/02/2008  Japan's Elpida Memory is increasing its ownership stake in its Rexchip Electronics memory JV with Taiwan's Powerchip Semiconductor to 52% in a bid to make the JV a consolidated subsidiary and take over leadership of investment and "adjust capacity allocation."

SIA: Oct. chip sales meltdown in West

12/02/2008  Dec. 1, 2008 - Worldwide sales of semiconductors that slowed significantly in September kept on slowing in October, particularly in the Americas region, according to the latest data from the Semiconductor Industry Association (SIA).

Applied Materials leads TSV drive for 3D ICs

12/01/2008  December 1, 2008: Applied Materials Inc. says it is leading a major effort to enable the widespread adoption of through-silicon vias (TSVs) for vertically stacking integrated circuits (ICs) to boost chip performance and functionality, working internally and with other equipment suppliers to develop an integrated, high-performance on-wafer process flow to lower costs, reduce risk, and accelerate time-to-market for customers.

Letter to the Editor

12/01/2008  I would like to clarify the comments you attributed to me as a result of our conversation at IMAPS International. I do not believe I said that through silicon vias (TSVs) were a pipedream, nor did I doubt that they would be adopted. What I said was that they would not be adopted at the rate projected. That is why I referenced the flip chip vs. wire bond issue as an historical reference.

A look at the economy

12/01/2008  At the time of this writing, the extent of the financial crisis (both in scope and duration) is still unknown, though most agree that it will get worse before it gets better.

Comfort is key for cleanroom garment compliance

12/01/2008  Merging contamination control technology with garment comfort and ease of use reduces the risks to cleanroom operations.

George Washington University establishes new Institute for Nanotechnology

11/28/2008  November 28, 2008: The George Washington University has announced the establishment of the GW Institute for Nanotechnology.

Elpida touts 50nm DRAM

11/26/2008  Elpida Memory says it has completed development of a 50nm DDR3 SDRAM that's twice as fast as Samsung's version, with what the company says is the lowest power consumption available (1.2V operation).

When photoresist is not enough

11/26/2008  Pattern transfer is becoming trickier at 4x/32nm nodes and beyond, with thinner resist layers and higher aspect ratios/etch requirements for both logic and memory. Enter ashable hardmasks as a possible solution. Novellus VP Tim Archer tells SST about the company's strategy and technology to address this pain point.

Analysis roundup: Stinky economy, souring forecasts

11/25/2008  The extent of the financial crisis is still unknown, of course, and most agree that it will get worse before it gets better. We've been gathering reports from leading market forecasters and analysts and can share what they're telling us -- and it looks like some rough sailing ahead for semiconductors.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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