Semiconductors

SEMICONDUCTORS ARTICLES



SAES Getters and ST partner on next-gen MEMS gyroscopes

05/16/2007  SAES Getters Group and STMicroelectronics have agreed to incorporate SAES' PageWafer technology into ST's multi-axis gyroscopes, with a goal of delivering higher sensitivity and stability for angular-speed measurement.

Analyst: DRAM, NAND fab investments now a JV world

05/15/2007  The new crop of tomorrow's DRAM and NAND flash memory fabs will be twice as big in 2009 as they were just five years earlier, and the costs to equip these behemoths will simply squeeze most chip companies out of the business unless they can hook into one of the growing number of industry alliances. Analyst George Burns with Strategic Marketing Associates reviews the delicate balance that memory firms constantly fight to maintain, who has the "flash religion" and who's likely to abandon ship.

SEMATECH will locate HQ at UAlbany NanoCollege

05/15/2007  International SEMATECH, the consortium of nanoelectronics manufacturers, will expand its existing R&D program at the Center of Excellence in Nanoelectronics and Nanotechnology at the University at Albany in New York. The expansion is the largest in the history of the consortium.

Spansion, TSMC extend MirrorBit flash pact to 40nm

05/15/2007  May 15, 2007 - Spansion Inc. and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) have expanded their existing partnership to extend development of Spansion's MirrorBit flash memory technology down to 40nm and below.

Die Sorter Platform

05/15/2007  pre-pick, post-flip, in-pocket, and post-seal — examine bump size, shape, and array; edge chip; laser mark; position and flatness in pocket; and other parameters.

Next-generation Wafer Bonder

05/15/2007  With a new design platform and attention to uniformity, the ELAN CB8 wafer bonder suits emerging technologies such as MEMS and 3D interconnects, as well as high-volume wafer-bonding applications.

Cadence Improves Co-design Platform

05/15/2007  Cadence Design Systems, Inc., released product and technology enhancements within its Allegro system interconnect design platform for PCB design, including constraint-driven flow and global routing.

Japan News: Capex from top chipmakers down 8% in FY08

05/15/2007  May 14, 2007 - Capital investments from Japan's top seven chipmakers is expected to be about 970 billion (US $8.09 billion) in this current fiscal year started in April, down 8% year-on-year but still the second-highest level on record, according to the Nikkei daily paper, which gives a rundown of individual capex plans from Toshiba Corp., Elpida Memory Inc., Renesas Technology Corp., NEC Electronics Corp., Sony Corp., Fujitsu Ltd., and Matsushita Industrial Co.

STATS ChipPAC readies R&D site in Singapore

05/14/2007  May 14, 2007 - STATS ChipPAC has formally established its new R&D facility in Singapore, to develop next-generation technologies including through-silicon vias (TSV), microbump bonding methods for 3D die, silicon substrate-based system-in-package solutions, and embedded active die technology.

Cypress carving out PSRAMs to Taiwan firm

05/14/2007  May 14, 2007 - Continuing a multistep process to slough off noncore businesses, Cypress Semiconductor is selling its PSRAM product line, including IP, photomasks, and probe card assets, to Taiwan's Elite Semiconductor Memory Technology Inc. (ESMT), who had been rumored to be interested in the business.

KLA-Tencor Cleared to Buy Therma-Wave

05/14/2007  The German Federal Cartel Office (FCO) approved KLA-Tencor's bid to purchase Therma-Wave shares, completing the regulatory approval process for the metrology equipment company's acquisition.

Microsoft, SanDisk Enter Joint Venture

05/14/2007  To develop a next-generation hardware and software solution for USB flash drives, Microsoft and SanDisk Corporation will collaborate and open an entity for licensing compatible hardware designs and intellectual property (IP). Revenues from the joint venture will be shared. Microsoft is discussing licensing software with third-party hardware vendors.

SMIC inks $1.86B US tool purchase commitment

05/11/2007  May 11, 2007 - Chinese flagship foundry Semiconductor Manufacturing International Co. (SMIC) has signed six letters of intent to purchase a total of $1.86 billion worth of semiconductor manufacturing equipment over three-year periods from US vendors.

SUSS Apps Center Opens in Singapore

05/11/2007  SUSS MicroTec AC opened its Applications & Measurement Center for the Asia-Pacific region. The Singapore center hosts test equipment for wafer test and semiconductor characterization.

SEMATECH shifting HQ to Albany

05/10/2007  May 10, 1007 - International SEMATECH is moving its headquarters from Austin, TX, to its operations located at the U. of Albany, and will launch a significant expansion there, matching $300 million in state investments for facility upgrades.

Japan News: Q&A with Samsung insider

05/09/2007  Shizuka Ishikawa, president of Samsung partner Tomen Devices Corp., shares his opinions with the Nikkei Business Daily about ongoing memory price volatility, and whether memory firms are investing too heavily in DRAM.

Flash memory is my copilot; Bowling for dollars and empowerment

05/09/2007  In a fascinating observation, Chipworks' Dick James did a teardown of a 4Gbit iPod's Samsung flash memory chip and found himself face-to-face with the apparent visage of Jesus Christ. ALSO: What could be more fun than an afternoon of social networking and hurling heavy spherical projectiles in support of a noble cause?

SUSS launches next-gen wafer bonding with ELAN CB8 tool

05/09/2007  SUSS MicroTec has launched what it calls "next generation, groundbreaking wafer-bonding technology" in the form of ELAN CB8. The tool is based on an entirely new design platform and promises to enable best-in-class production across a wide range of performance parameters.

IITC PREVIEW: Are 3D interconnects ready for prime time?

05/08/2007  Among the most significant developments in interconnect to look for at the upcoming International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) are those involving 3D chip architectures. Sitaram Arkalgud, director of SEMATECH's interconnect division, discusses the "new religion" of 3D chip architecture with WaferNEWS, and explains why it's the most promising route to eliminating the main stumbling block to higher chip speeds and lower power consumption.

IBM adds airgaps for faster chips

05/08/2007  Airgap structures have long been considered to increase the speed of on-chip IC interconnects, but it's a long way from proof-of-concept to a working process flow in a fab. In an exclusive interview with WaferNEWS, IBM strips away the hype to explain its new manufacturable variation on airgaps using a self-assembling polymer mask layer -- revealing that airgaps in standard low-k dielectric structures add only ~1% to chip cost for each layer.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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