Semiconductors

SEMICONDUCTORS ARTICLES



Analysts: litho market to "soften" in 2008

05/26/2006  May 26, 2006 - Analysis from two firms predicts a soft market for lithography equipment in 2008, after leading-edge chipmakers are through placing initial orders for next-generation lithography tools.

Litho forum poll: We want 193nm immersion ready for 45nm

05/26/2006  May 26, 2006 - Attendees at the SEMATECH-sponsored Litho Forum in Vancouver, BC, May 22-24 discussed the readiness of lithography technologies for the 32nm half-pitch and beyond technology generations, seen beginning in 2012, following the 45nm node generation expected to begin production in 2009.

Taiwan chip assemblers prep for China move

05/25/2006  May 25, 2006 - Taiwan's top chip assembly houses are lining up to get government approval to open facilities in mainland China, following the government's decision to limit restrictions on transfers of some technologies

SEMATECH, Queensland U. working on high-index immersion photoresists

05/25/2006  May 25, 2006 - SEMATECH and the U. of Queensland, Brisbane, Australia, have agreed to codevelop new resists for 193nm immersion lithography, in an effort to extend immersion technology for multiple generations.

Capacity, output inch up in 1Q

05/25/2006  May 25, 2006 - Worldwide IC capacity rose 4% during 1Q06, while output inched up about 2%, and utilization rates slipped below the 90% mark for the first time since last summer, according to new data from Semiconductor International Capacity Statistics (SICAS).

SMIC poised to ride the China wave

05/25/2006  In a one-on-one interview at The ConFab, Charles Huang, SVP of SMIC's Shanghai operation, followed up on his Monday presentation about general strategies foundries can take to produce next-generation semiconductor technology, and outlined his company's plans to exploit the burgeoning demand for ICs in China -- now the world's largest regional IC market.

Toward an open ecosystem for R&D

05/25/2006  During a ConFab panel discussion on "Solutions to the R&D Challenge," Simon Yang, senior VP and CTO of Chartered Semiconductor Manufacturing, called for greater support of an industry-wide "open ecosystem of R&D" to deal with the impending R&D crisis. Several factors are converging to create a perfect storm in R&D, he said -- as scaling approaches physical limits, profit margins for technology and manufacturing companies are shrinking, and R&D operation costs are escalating out of control.

Can lessons from 300mm conversion keep the industry on the productivity roadmap?

05/24/2006  A detailed economic model suggests that industry productivity will lag historical trends early in the next decade, slowing the decline in cost/transistor, unless new initiatives get underway to reverse this trend, reported Scott Kramer, director, International SEMATECH Manufacturing Initiative (ISMI), in a Tuesday afternoon presentation at The ConFab.

Litho costs won't limit Moore's Law, but technology is the key

05/24/2006  Examining the history of lithography over the past two decades suggests that the choices ahead are similar to those that were successfully made in the past, suggested Kazuo Ushida, Nikon Corp., in his presentation on "Cost-effective lithography" at The ConFab. Comparing the array of future litho contenders in 2006 with the options considered in 1999, Ushida concluded that it looks like "deja vu all over again."

Disconnect marks 450mm wafer debate

05/24/2006  A ConFab session on 450mm wafers provided a multifaceted look at a sharp split that has developed in the industry. Peter Silverman, Intel Fellow, stated the need for a 30% cost/cm2 reduction every 10 years to follow Moore's Law," while a SEMATECH exec said that would fall short even with a 450mm transition by the ITRS goal of 2012. And don't expect equipment suppliers to pay for the 450mm tool R&D, warned Applied Materials' Mark Pinto.

Innovation needed to tap huge potential markets

05/23/2006  Enormous potential markets are emerging for semiconductors, said Jai Hakhu, corporate VP, Intel, at The ConFab. However, serving them will require continued innovation, and an intense focus on efficiency by the industry. Chips will have to provide multiple functions at lower price points to capitalize on the opportunities, he stated.

Pushing "Moore" out of lithography

05/23/2006  Peter Jenkins, VP of marketing for ASML, described lithography options and challenges at the 32nm half-pitch for ConFab attendees. Among the challenges: there is no clear consensus on the part of IC manufacturers with respect to the kind of lithography needed at 32nm, although EUV is preferred for 22nm half-pitch.

Economics of sub-45nm chipmaking for equipment suppliers

05/23/2006  Tough challenges facing process tool vendors as the industry moves toward sub-45nm chip features will require imaginative solutions. An analysis relating important application trends to process tool requirements was presented by Masayuki Tomoyasu, director of development and planning for Tokyo Electron, Ltd. (TEL), who then proposed a wide range of potential solutions for toolmakers.

Mitsubishi Electric added to DRAM antitrust list

05/23/2006  May 23, 2006 - Mitsubishi Electric Corp. said that US antitrust investigators have requested details of its previous memory chip sales, as part of a widening investigation into DRAM price fixing at several companies.

ASML: Immersion ramp pushing tool demand in 2Q

05/23/2006  May 23, 2006 - ASML Holding NV says it's seeing stronger than anticipated demand for its lithography equipment in 2Q06, as customers place orders for immersion lithography tools used in an anticipated production ramp-up in 4Q06-1Q07.

UAlbany, Corrnell top nano institute rankings

05/23/2006  May 23, 2006 - Ten US universities from New York to Texas to the midwest have been ranked as tops among universities' efforts in micro- and nanotechnology research, according to a survey conducted by Solid State Technology sister publication Small Times.

May 2006 Exclusive Feature:

Tackling future CMOS challenges outside Moore's Law



05/23/2006  By Bob Haavind, Editorial Director, SST

Is Moore's Law dead -- and if so, does it really matter? That question, posed at a recent SEMI breakfast panel near Boston, brought some surprising answers. Yes, an expert panel agreed, the traditional shrink of Moore's Law ran into physical limits a few years ago, but it really won't make that much difference to progress in electronic systems...




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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