Issue

One of the main concerns with three-dimensional stacked chips is the potential impact of mechanical stresses on CMOS transistors.

Researchers report they are close to achieving the density of (CNTs) needed to manufacture carbon nanotube interconnect vias for production applications.

The first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits "3D-TEST," held in Nov. in Austin, TX, was the latest example of how the 3D topic is being picked up by the test community.

Seeing a gap in the lithography roadmap as an etch opportunity, Applied Materials released its new conductor etch system, the Centris AdvantEdge Mesa Etch, at SEMICON Japan.

At this point, the NRI program has not yet identified any single, most-promising candidate for a beyond CMOS nanotechnology, but there may eventually be several, spanning and extending the wide range of applications that CMOS FETs currently continue to address very well. Robert Doering, Texas Instruments, Dallas, Texas, USA

Wafer-level packages that use a glass cover over the package cavity and through-silicon vias to interconnect the die bond pads satisfy the packaging requirements for CMOS image sensors: compact, reliable, low cost, and accommodate both front- and back-illuminated image sensors with no external changes. Giles Humpston, Tessera Inc., San Jose, California, USA

2010 was perhaps the best year ever for the semiconductor industry, a nice rebound from the worst year ever. 2011 will likely be a year when the semiconductor industry returns to "normal", with more moderate, single-digit growth. Cyclicality is expected to continue. Here's what leading industry analysts are saying about the year ahead.