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Nanoengineering researchers at Rice University and Nanyang Technological University in Singapore have unveiled a potentially scalable method for making one-atom-thick layers of molybdenum diselenide — a highly sought semiconductor that is similar to graphene but has better properties for making certain electronic devices like switchable transistors and light-emitting diodes.

 

The method for making two-dimensional molybdenum diselenide uses a technique known as chemical vapor deposition (CVD) and is described online in a new paper in the American Chemical Society journal ACS Nano. The finding is significant because CVD is widely used by the semiconductor and materials industries to make thin films of silicon, carbon fibers and other materials.

“This new method will allow us to exploit the properties of molybdenum diselenide in a number of applications,” said study leader Pulickel Ajayan, chair of Rice’s Department of Materials Science and NanoEngineering. “Unlike graphene, which can now easily be made in large sheets, many interesting 2-D materials remain difficult to synthesize. Now that we have a stable, efficient way to produce 2-D molybdenum diselenide, we are planning to expand this robust procedure to other 2-D materials.”

In the Rice study, Ajayan and colleagues tested their atomically thin layers of molybdenum diselenide by building a field effect transistor (FET), a commonly used device in the microelectronic industry. Tests of the FET found the electronic properties of the molybdenum diselenide layers were significantly better than those of molybdenum disulfide; the latter is a similar material that has been more extensively studied because it was easier to fabricate. For example, the FET tests found that the electron mobility of Rice’s molybdenum diselenide was higher than that of CVD-grown, molybdenum disulfide.

In solid-state physics, electron mobility refers to how quickly electrons pass through a metal or semiconductor in the presence of an electric field. Materials with high electron mobility are often preferred to reduce power consumption and heating in microelectronic devices.

“Being able to make 2-D materials in a controlled fashion really will make an impact on our understanding and use of their fascinating properties,” said study co-author Emilie Ringe, assistant professor of materials science and nanoengineering and of chemistry at Rice. “Characterizing both the structure and function of a material, as we have done in this paper, is critical to such advances.”

Molybdenum diselenide and molybdenum disulfide each belong to a class of materials known as transition metal dichalcogenides; TMDCs are so named because they consist of two elements, a transition metal like molybdenum or tungsten and a “chalcogen” like sulfur, selenium or tellurium.

TMDCs have attracted intense interest from materials scientists because they have an atomic structure similar to graphene, the pure carbon wonder materials that attracted the 2010 Nobel Prize in physics. Graphene and similar materials are often referred to as two-dimensional because they are only one atom thick. Graphene has extraordinary electronic properties. For example, its electron mobility is tens of thousands of times greater than that of TMDCs.

However, two-dimensional TMDCs like molybdenum diselenide have attracted intense interest because their electronic properties are complementary to graphene. For example, pure graphene has no bandgap — a useful electronic property that engineers can exploit to make FETs that are easily switched on and off.

As with many nanomaterials, scientists have found that the physical properties of TMDCs change markedly when the material has nanoscale properties. For example, a slab of molybdenum diselenide that is even a micron thick has an “indirect” bandgap while a two-dimensional sheet of molybdenum diselenide has a “direct” bandgap. The difference is important for electronics because direct-bandgap materials can be used to make switchable transistors and sensitive photodetectors.

“One of the driving forces in Rice’s Department of Materials Science and NanoEngineering is the close collaborations that develop between the people who are focused on synthesis and those of us involved with characterization,” said Ringe, who joined Rice’s faculty in January. “We hope this will be the beginning of a series of new protocols to reliably synthesize a variety of 2-D materials.”

The research was supported by the Army Research Office, the Semiconductor Research Corporation’s FAME Center, the Office of Naval Research and Singapore’s MOE Academic Research Fund.

Additional study co-authors include Xingli Wang, Yongji Gong, Gang Shi, Kunttal Keyshar, Gonglan Ye, Robert Vajtai and Jun Lou, all of Rice, and Wai Leong Chow, Zheng Liu and Beng Kang Tay, all of Nanyang Technological University.

The global semiconductor materials market decreased 3 percent in 2013 compared to 2012 while worldwide semiconductor revenues increased 5 percent. Revenues of $43.5 mark the second consecutive year of contraction for the semiconductor materials market.

Total wafer fabrication materials and packaging materials were $22.76 billion and $20.70 billion, respectively. Comparable revenues for these segments in 2012 were $23.44 billion for wafer fabrication materials and $21.36 billion for packaging materials. For the second year in a row, substantial declines in silicon revenue, advanced substrates, and bonding wire contributed to the year-over-year decrease to the total semiconductor materials market.

For the fourth consecutive year, Taiwan was the largest consumer of semiconductor materials due to its large foundry and advanced packaging base, despite not experiencing any annual growth. The materials market in North America also remained flat year-over-year. The materials markets in China and Europe increased in 2013, benefiting from strength in wafer fab materials. The materials market in Japan contracted 12 percent, with markets also contracting in South Korea and Rest of World. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.)

2012-2013 Semiconductor Materials Market by World Region
(Dollar in U.S. billions; Percentage Year-over-Year)

Region

2012*

2013

% Change

Taiwan

8.97

8.96

0%

Japan

8.24

7.29

-12%

South Korea

7.22

6.94

-4%

Rest of World

7.17

6.76

-6%

China

5.50

5.70

4%

North America

4.75

4.75

0%

Europe

2.95

3.07

4%

Total

44.80

43.46

-3%

Source: SEMI April 2014

Note: Figures may not add due to rounding.

* 2012 data were revised based on the recently released Global Semiconductor Packaging Materials Outlook- 2013/2014.

2013: A year in review


April 4, 2014

By Lara Chamness, senior market analyst manager, SEMI

Semiconductor Market Trends

2013 was a record year in terms of semiconductor device revenues; the industry finally exceeded the long elusive $300 billion mark, registering almost 5 percent growth according to the SIA. While 2013 was a growth year for the chip industry, it was the second consecutive year of declining revenues for both semiconductor equipment and materials; the 2013 semiconductor equipment and materials markets contracted 14 percent and 3 percent, respectively.

Materials-chart-1

Source: SIA, SEMI, SEMI/SEAJ

When looking at revenue trends, it is important to consider the impact of the weakened Yen on total revenues. The Table shows the impact of the weakened Yen on Semiconductor Equipment Association of Japan’s (SEAJ) book-to-bill data. If the data were kept in Yen, the 2013 market for Japan-based suppliers would be down 14 percent. However, when the Yen are converted to dollars the 2013 equipment market for Japan-based suppliers declined almost 30 percent. Since Japan-headquartered suppliers represent a significant portion of the equipment market, this has the effect of dragging down the global equipment market. Given the importance of Japanese suppliers to the materials market, the weakened Yen also contributed significantly to the decline of semiconductor materials revenues in 2013. For a more detailed discussion of the impact on the semiconductor equipment and materials market please refer to Dan Tracy’s article in the March SEMI Global Update.

Weakening Yen Impact on Japan Supplier Annual Billings

Materials-chart2

Semiconductor Equipment

Worldwide sales of semiconductor manufacturing equipment totaled $31.6 billion in 2013, representing a year-over-year decrease of 14 percent and spending on par with 2005 levels. Looking at equipment sales by major equipment category, 2013 saw contractions in all major categories, Wafer Processing equipment contracted 11 percent, while Assembly and Packaging and Test equipment contracted 26 and 24 percent, respectively. The Other Front-end segment (Other Front End includes Wafer Manufacturing, Mask/Reticle, and Fab Facilities equipment) contracted 34 percent.

TSMC continued with its aggressive investments in 2013, resulting in the Taiwan market increasing 11 percent to maintain the top spot ($10.6 billion) in equipment spending. The only other region to experience year-over-year growth was China spurred by investments by SK Hynix, Samsung, and SMIC, with an increase of 30 percent. North America surpassed South Korea to claim the second spot, device makers reduced their spending in Korea last year. Japan remained in the fourth top spot, just above China, with $3.4 billion in equipment sales. Equipment sales to Europe decreased 25 percent in 2013. Investments in the Rest of World region remained relatively flat when compared to 2012.  Rest of World region aggregates Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.

Materials-chart3

Semiconductor Materials

The global semiconductor materials market, which includes both fab and packaging materials, contracted 3 percent in 2013 totaling $43.5 billion. Even with the decrease, the semiconductor materials market has been larger than the equipment for the past six years.

Taiwan maintained the top spot for the fourth year in a row, followed by Japan, South Korea, Rest of World, and China. Driving the materials market in Taiwan are advanced packaging operations and foundries. While Japan still claims the largest installed fab capacity globally and has a tradition in domestic-based packaging, many companies in Japan have rapidly adopted a fab lite strategy and have consolidated their fab and packaging plants. South Korea passed Rest of World (primarily SE Asia) as the third largest market for semiconductor materials given the dramatic increase in advanced fab capacity in the region in recent years. Looking at the materials market by wafer fab and packaging materials, both segments contracted 3 percent.

Materials-chart4

Outlook

Most analysts predict mid- to high single-digit growth for the semiconductor device market for the year. Initial monthly data for silicon shipments and semiconductor equipment are proving to be encouraging. Given growth expectations for the device market, it is projected that the semiconductor materials market will increase 2 percent this year. Given two consecutive years of double-digit decline, the outlook for semiconductor equipment is much more optimistic with current expectations positive with spending potentially growing 20 percent or more

2013 was another disappointing year for equipment and materials suppliers as device manufacturers finally exceed revenues of $300 billion. Anemic sales, downward price pressure, combined with a weakened Yen proved to be a significant challenge on the semiconductor supply chain. 2014 is promising to be better for the entire market with device, materials and equipment markets are all anticipated to increase for the year.

Today, GaN on Sapphire is the main stream technology for LED manufacturing. GaN-on-Si technology appeared naturally as an alternative to sapphire to reduce cost. Yole Développement’s cost simulation indicates that the differential in silicon substrate cost is not enough to justify the transition to GaN-on-Si technology. The main driver is the ability to manufacture in existing, depreciated CMOS fabs in 6 inch or 8 inch.

“Despite potential cost benefits for LEDs, the mass adoption of GaN-on-Si technology for LED applications remains unclear. Opinions regarding the chance of success for LED-on-Si vary widely in the LED industry from unconditional enthusiasm to unjustified skepticism. Virtually all major LED makers are researching GaN-on-Si LED, but few have made it the core of their strategy and technology roadmap. Among the proponents, only Lattice Power, Plessey and Toshiba have moved to production and are offering commercial LED-on-Si,” explains Dr. Hong Lin, Yole Developpement analyst.

At Yole Développement, analysts believe that although significant improvements have been achieved, there are still some technology hurdles (performance, yields, CMOS compatibility). They consider that if the technology hurdles are cleared, GaN-on-Si LEDs will be adopted by some LED manufacturers, but will not become the industry standard. Yole Développement expects that Silicon will capture less than five percent of LED manufacturing by 2020.

GaN-on-Si technology will be widely adopted by power electronics applications

The power electronics market addresses applications such as AC to DC or DC to AC conversion, which is always associated with substantial energy losses that increase with higher power and operating frequencies. Incumbent silicon based technology is reaching its limit and it is difficult to meet higher requirements. GaN based power electronics have the potential to significantly improve efficiency at both high power and frequencies while reducing device complexity and weight. Power GaN are therefore emerging as a substitution to the silicon based technology. Today, Power GaN remains at its early stage and presents only a tiny part of power electronics market.

“We are quite optimistic about the adoption of GaN-on-Si technology for Power GaN devices. GaN-on-Si technology have brought to market the first GaN devices. Contrary to the LED industry, where GaN-on-Sapphire technology is main stream and presents a challenging target, GaN-on-Si will dominate the GaN based power electronics market because of its lower cost and CMOS compatibility,” says Dr. Eric Virey, analyst at Yole Developpement. Although GaN based devices remain more expensive than Si based devices today, the overall cost of GaN devices for some applications are expected to be lower than Si devices three years from now, according to some manufacturers.

“In our nominal case, GaN based devices could reach more than seven percent of the overall power device market by 2020,” adds Virey. GaN-on-Si wafers will capture more than one point five percent of the overall power substrate volume, representing more than 50 percent of the overall GaN-on-Si wafer volume, subjecting to the hypothesis that the 600V devices would take off in 2014-2015.

GaN-on-Si epiwafer: buy it or make it? Which business will be dominated?

GaN on Si LED

To adopt the GaN-on-Si technology, device makers have the choice between buying epiwafers or templates on the open market, or buying MOCVD reactors and making epiwafer by themselves. Today, there is a limited number of players selling either epiwafers or templates or both on the open market. These players comes from Japan, US and Europe. We have not observed an absolute dominance from one region.

As perceived by device markers, each business model has its pros & cons in terms of IP, technology dependence, R&D investments, and time. According to Yole Développement’s reports, analysts do not expect to see a significant template/epiwafer business emerge for LEDs and consider that LEDs makers would prefer making their epiwafers internally for mass production. For the power electronics industry, the opinion is divided. Yole Dévelopement considers that buying epiwafers could work as long as the price of the epiwafer on the open market keeps decreasing.

SanDisk Corporation today announced that it has filed a civil lawsuit against Korea’s SK Hynix, Inc., SK Hynix America and related entities in Santa Clara Superior Court. The lawsuit seeks damages, an injunction and other remedies against Hynix for trade secret misappropriation under California’s Uniform Trade Secret Act.

Additionally, SanDisk has submitted a criminal complaint with the Tokyo Metropolitan Police Department against a former employee.

These actions relate to the theft of trade secrets related to NAND flash technology by a former engineer of SanDisk who left the company in 2008 to work for SK Hynix. This engineer is alleged to have illegally taken SanDisk’s proprietary technical information and to have subsequently provided it to SK Hynix.

Tokyo Metropolitan Police today announced the arrest of the former employee, who worked at SanDisk’s joint venture manufacturing facility in Yokkaichi, Japan. SanDisk has been and continues to cooperate with law enforcement in their investigation.

SanDisk’s joint venture relationship with Toshiba Corporation has been in place for nearly 15 years and represents one of the most successful partnerships in the semiconductor industry. SanDisk and Toshiba together have enabled more than 10 generations of NAND flash technologies over these years.

“SanDisk strongly believes in the value of IP, and takes protecting trade secrets seriously,” said Judy Bruner, executive vice president, administration, and chief financial officer at SanDisk. “We are working diligently with the authorities as well as our partner on these matters and are aggressively pursuing all legal remedies available to us.”

Related news: Toshiba brings civil suit against SK Hynix

Most modern electronics, from flat-screen TVs and smartphones to wearable technologies and computer monitors, use tiny light-emitting diodes, or LEDs. These LEDs are based off of semiconductors that emit light with the movement of electrons. As devices get smaller and faster, there is more demand for such semiconductors that are tinier, stronger and more energy efficient.

This graphical representation shows the layers of the 2-D LED and how it emits light.

U of Washington

This graphical representation shows the layers of the 2-D LED and how it emits light.

University of Washington scientists have built the thinnest-known LED that can be used as a source of light energy in electronics. The LED is based off of two-dimensional, flexible semiconductors, making it possible to stack or use in much smaller and more diverse applications than current technology allows.

“We are able to make the thinnest-possible LEDs, only three atoms thick yet mechanically strong. Such thin and foldable LEDs are critical for future portable and integrated electronic devices,” said Xiaodong Xu, a UW assistant professor in materials science and engineering and in physics.

Xu along with Jason Ross, a UW materials science and engineering graduate student, co-authored a paper about this technology that appeared online March 9 in Nature Nanotechnology.

Most consumer electronics use three-dimensional LEDs, but these are 10 to 20 times thicker than the LEDs being developed by the UW.

“These are 10,000 times smaller than the thickness of a human hair, yet the light they emit can be seen by standard measurement equipment,” Ross said. “This is a huge leap of miniaturization of technology, and because it’s a semiconductor, you can do almost everything with it that is possible with existing, three-dimensional silicon technologies,” Ross said.

The UW’s LED is made from flat sheets of the molecular semiconductor known as tungsten diselenide, a member of a group of two-dimensional materials that have been recently identified as the thinnest-known semiconductors. Researchers use regular adhesive tape to extract a single sheet of this material from thick, layered pieces in a method inspired by the 2010 Nobel Prize in Physics awarded to the University of Manchester for isolating one-atom-thick flakes of carbon, called graphene, from a piece of graphite.

In addition to light-emitting applications, this technology could open doors for using light as interconnects to run nano-scale computer chips instead of standard devices that operate off the movement of electrons, or electricity. The latter process creates a lot of heat and wastes power, whereas sending light through a chip to achieve the same purpose would be highly efficient.

“A promising solution is to replace the electrical interconnect with optical ones, which will maintain the high bandwidth but consume less energy,” Xu said. “Our work makes it possible to make highly integrated and energy-efficient devices in areas such as lighting, optical communication and nano lasers.”

The research team is working on more efficient ways to create these thin LEDs and looking at what happens when two-dimensional materials are stacked in different ways. Additionally, these materials have been shown to react with polarized light in new ways that no other materials can, and researchers also will continue to pursue those applications.

A close-up view of a single layer of atoms of the semiconductor material

U of Washington

A close-up view of a single layer of atoms of the semiconductor material, tungsten diselenide, on silicon oxide. The ability to see the contrast of the single layer of atoms against the background shows how strongly these materials interact with light.

Co-authors are Aaron Jones and David Cobden of  the UW; Philip Klement of Justus Liebig University in Germany; Nirmal Ghimire, Jiaqiang Yan and D.G. Mandrus of the University of Tennessee and Oak Ridge National Laboratory; Takashi Taniguchi, Kenji Watanabe and Kenji Kitamura of the National Institute for Materials Science in Japan; and Wang Yao of the University of Hong Kong.

The research is funded by the U.S. Department of Energy, Office of Science, the Research Grant Council of Hong Kong, the University Grant Council of Hong Kong and the Croucher Foundation. Ross is supported by a National Science Foundation graduate fellowship.

The Semiconductor Industry Association this week presented its University Research Award – in consultation with Semiconductor Research Corporation (SRC) – to University of Minnesota professor Sachin Sapatnekar in recognition of his outstanding contributions to semiconductor research.

“We are pleased to recognize Dr. Sapatnekar for his trailblazing work in the field of semiconductor research,” said Dr. John E. Kelly III, IBM senior vice president, director of IBM Research, and 2014 SIA chairman. “Research is critical to sustaining the pipeline of discoveries that drive growth in the semiconductor industry and our economy. We commend Dr. Sapatnekar for his outstanding achievements.”

SIA

Dr. Sapatnekar holds the Distinguished McKnight University Professorship and the Robert and Marjorie Henle Chair in Electrical and Computer Engineering at the University of Minnesota. He was chosen for the award because of his work in developing computer-aided techniques for the analysis and optimization of integrated circuits, with his most recent work covering CMOS technologies as well as spintronics. Specifically, Professor Sapatnekar’s research has made significant impact in verifying and optimizing the power delivery networks of central processing units (CPUs) and other system on chips (SoCs). Analysis techniques developed by Professor Sapatnekar and his research group have dramatically advanced this capability in the design community.

He has authored nine books and numerous papers in this area and has received six conference Best Paper Awards and a Best Poster Award, as well as the ICCAD Ten-Year Retrospective Most Influential Paper Award, an award that recognizes a paper that has had a significant impact ten years after its publication.

“Our mission at SRC is to seed innovation and help provide the people and ideas to keep the U.S. semiconductor industry competitive, and Dr. Sapatnekar is an ideal example of this collective effort,” said SRC President Larry Sumney. “We salute Dr. Sapatnekar for the role he has played in our university research engine that has made the U.S. the cradle of discovery and technology development.”

Dr. Sapatnekar has served as the Editor-in-Chief of the IEEE Transactions on Computer-Aided Design and as General Chair for the ACM/IEEE Design Automation Conference, the two top publication venues in his research area, as well as leadership roles (General Chair and/or Technical Program Chair) in the ACM International Symposium on Physical Design, the IEEE/ACM Tau Workshop, and the International Conference on VLSI Design. He was conferred with a Fulbright award as a Senior Researcher in Spain in the Fall of 2013, and held the D.J. Gandhi Visiting Professorship at IIT Bombay in early 2014. He has received the NSF Career Award and the Semiconductor Research Corporation Technical Excellence Award, and he is a Fellow of the IEEE.

MIT researchers sponsored by Semiconductor Research Corporation have introduced new directed self-assembly (DSA) techniques that promise to help semiconductor manufacturers develop more advanced and less expensive components.

The MIT study demonstrates that complex patterns of lines, bends and junctions with feature sizes below 20nm can be made by block copolymer self-assembly guided by a greatly simplified template. This study explained how to design the template to achieve a desired pattern. Electron-beam lithography was used to produce the template serially, while the block copolymer filled in the rest of the pattern in a parallel process. This hybrid process can be five or more times faster than writing the entire pattern by electron beam lithography.

Related new: EUV is late but on the way for 10nm; DSA is promising

“We believe our research will help Moore’s Law to be continued,” said Caroline Ross, MIT professor of Materials Science and Engineering. “To increase the density of transistors in a given area, the pitch of the features in a transistor should be scaled down, but the increasing time and cost of manufacturing such fine and dense features becomes more problematic. Our research suggests a solution to this problem.”

Leveraging block copolymer self-assembly to produce dense, high resolution patterns was proposed and demonstrated several years ago, but there was no systematic way to design templates to achieve a complex block copolymer pattern. The MIT study developed a simple way to design a template to achieve a specific block copolymer pattern over a large area. Although the work used electron-beam lithography to define the template, other methods such as photolithography with trimming could be used to produce the templates.

Block copolymer lithography is already on the semiconductor industry roadmap as directed self-assembly, but the process is still in its infancy. Although DSA patterning has been demonstrated on 300 millimeter wafers, these early trials used templates fabricated by photolithography with limited resolution and limited control of the feature geometry. The MIT process offers a path to far more complicated geometries using relatively simple templates. Next steps involve the research being shared with semiconductor companies for further studies.

“The demand for computing processors with higher bandwidth and memories of larger capacity continues to grow, but the manufacturing cost of these devices is also increasing as the transistor and associated interconnect dimensions shrink,” said Bob Havemann, Director of Nanomanufacturing Sciences at SRC. “Lithography research such as the work completed by the MIT team is critically important as the required feature sizes in semiconductor manufacturing scale below what is achievable with conventional lithography techniques.”

A research collaboration consisting of IHP-Innovations for High Performance Microelectronics in Germany and the Georgia Institute of Technology has demonstrated the world’s fastest silicon-based device to date. The investigators operated a silicon-germanium (SiGe) transistor at 798 gigahertz (GHz) fMAX, exceeding the previous speed record for silicon-germanium chips by about 200 GHz.

Although these operating speeds were achieved at extremely cold temperatures, the research suggests that record speeds at room temperature aren’t far off, said professor John D. Cressler, who led the research for Georgia Tech. Information about the research was published in February of 2014, by IEEE Electron Device Letters.

Dr. John Cressler (red shirt) in his lab with student Partha Chakraborty

“The transistor we tested was a conservative design, and the results indicate that there is significant potential to achieve similar speeds at room temperature – which would enable potentially world changing progress in high data rate wireless and wired communications, as well as signal processing, imaging, sensing and radar applications,” said Cressler, who hold the Schlumberger Chair in electronics in the Georgia Tech School of Electrical and Computer Engineering. “Moreover, I believe that these results also indicate that the goal of breaking the so called ‘terahertz barrier’ – meaning, achieving terahertz speeds in a robust and manufacturable silicon-germanium transistor – is within reach.”

Meanwhile, Cressler added, the tested transistor itself could be practical as is for certain cold-temperature applications. In particular, it could be used in its present form for demanding electronics applications in outer space, where temperatures can be extremely low.

IHP, a research center funded by the German government, designed and fabricated the device, a heterojunction bipolar transistor (HBT) made from a nanoscale SiGe alloy embedded within a silicon transistor. Cressler and his Georgia Tech team, including graduate students Partha S. Chakraborty, Adilson Cordoso and Brian R. Wier, performed the exacting work of analyzing, testing and evaluating the novel transistor.

“The record low temperature results show the potential for further increasing the transistor speed toward terahertz (THz) at room temperature. This could help enable applications of Si-based technologies in areas in which compound semiconductor technologies are dominant today. At IHP, B. Heinemann, H. Rücker, and A. Fox supported by the whole technology team working to develop the next THz transistor generation,” according to Bernd Tillack, who is leading the technology department at IHP in Frankfurt (Oder), Germany.

Silicon, a material used in the manufacture of most modern microchips, is not competitive with other materials when it comes to the extremely high performance levels needed for certain types of emerging wireless and wired communications, signal processing, radar and other applications. Certain highly specialized and costly materials – such as indium phosphide, gallium arsenide and gallium nitride – presently dominate these highly demanding application areas.

But silicon-germanium changes this situation. In SiGe technology, small amounts of germanium are introduced into silicon wafers at the atomic scale during the standard manufacturing process, boosting performance substantially.

The result is cutting-edge silicon germanium devices such as the IHP Microelectronics 800 GHz transistor. Such designs combine SiGe’s extremely high performance with silicon’s traditional advantages – low cost, high yield, smaller size and high levels of integration and manufacturability – making silicon with added germanium highly competitive with the other materials.

Cressler and his team demonstrated the 800 GHz transistor speed at 4.3 Kelvins  (452 degrees below zero, Fahrenheit). This transistor has a breakdown voltage of 1.7 V, a value which is adequate for most intended applications.

The 800 GHz transistor was manufactured using IHP’s 130-nanometer BiCMOS process, which has a cost advantage compared with today’s highly-scaled CMOS technologies. This 130 nm SiGe BiCMOS process is offered by IHP in a multi-project wafer foundry service.

Dr. John Cressler's lab

The Georgia Tech team used liquid helium to achieve the extremely low cryogenic temperatures of 4.3 Kelvins in achieving the observed 798 GHz speeds. “When we tested the IHP 800 GHz transistor at room temperature during our evaluation, it operated at 417 GHz,” Cressler said. “At that speed, it’s already faster than 98 percent of all the transistors available right now.”

By Dr. Phil Garrou, Contributing Editor

ibm photo

 

 

 

 

The Financial Times (FT) is reporting that IBM Corp is exploring the sale of its semiconductor business and has hired Goldman Sachs to find potential buyers. [link] The FT report continues that another financial option may be to find a partner for a JV to jointly run its semiconductor business.

FT projects that the most likely buyers would be Global Foundries or TSMC  since it is likely that these two foundry giants along with Samsung and Intel will be the only players left in advanced chip manufacturing as the cost of 20nm and lower fabs now exceeds $6B.

This should not come as a shock to readers of SST’s IFTLE blog (Insights From the Leading Edge) which reported early rumors of such a sale back in the summer of 2010. [ see IFTLE 8 “3D Infrastructure Announcements and Rumors” July 2010]

While the semiconductor business has become an increasingly less important part of IBM’s operations in recent years as it has expanded in IT software and services, any sale or joint venture would surely have to ensure that IBM still had a guaranteed supply of the advanced chips required for its mainframe and high end server businesses.

GlobalFoundries is the most likely candidate for sale or JV since they are a member of the IBM common platform, have been working with IBM for over a decade [link] and have placed their latest fab (Fab 8) in IBMs back yard in upstate NY [link] .

This report comes two weeks after the announcement that, pending government approval, IBM will sell its low-end server business for $2.3 billion to Chinese PC maker Lenovo.  Some may recall that  a  decade ago Lenovo bought IBM’s ThinkPad PC business for $1.75B [link].

This low end server decision was likely driven by the trend for many major corporations to move their IT requirements to “the cloud” with companies such as Amazon web services. With customers having more choices for handling their IT, they will be reluctant to get locked into client-server service contracts with IBM.

In fact IBM has just announced [link] plans to commit  over $1.2B to significantly expand its global cloud footprint. IBM plans to deliver cloud services from 40 data centers worldwide in 15 countries and five continents globally, including North America, South America, Europe, Asia and Australia.  IBM will open 15 new centers worldwide adding to the existing global footprint of 13 global data centers from SoftLayer, which it acquired in July of 2013, and 12 from IBM.