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Attendees at this year’s International Electron Devices Meeting (IEDM) were delighted and perhaps somewhat horrified when the plenary speaker popped some electronics gear in his mouth and proclaimed, “It tastes like chicken!” The speaker, John Rogers from the University of Illinois at Champaign-Urbana, was demonstrating the edible nature of what he called transient electronics, which are designed from elements that rapidly decompose and are harmless to the human body and to the environment. One possible application of such bio-integrated electronics: They could be placed below a suture and provide enough heat through a resistive element to kill bacteria over a two week period. Bacteria sewn into the body during an operation are often the cause of a return trip to the hospital and delayed recovery.

He demonstrated that a very thin layer of silicon will dissolve in water fairly rapidly, in a matter of hours, turning into a salicylic acid. Circuits were completed with silicon dioxide as a gate dielectric and insulator and Manganese as the interconnect and resistor material. Levels were well below the FDA’s recommended daily allowance. Silk, already approved by the FDA for such applications, was used as the substrate. “You don’t want to chew,” Rogers quipped during his demonstration.

He said other applications of transient electronics include the use of sensors in chemical spills, which would monitor the presence of the chemical over time and then dissolve away, and even in consumer electronics, where lifetime would be measured in years instead of weeks.

Rogers also described another class of bioelectronics he called silicon membranes. By making silicon-based electronics thin enough, they can be stretchable. With a serpentine design, an applied strain of 30% induces strains that are less than 0.65%. These devices can conformally laminate onto the surface of the skin, in a manner that is mechanically invisible to the user, much like a temporary transfer tattoo. The systems, referred to as epidermal electronics, attach intimately and physically couple to rough skin surfaces, via van der Waals forces alone, with the ability accommodate natural and induced motions, Rogers noted in the accompanying paper.

Other bioelectronic applications include brain surgery, interfaces for human/computer control systems, skin-based physiological status monitors, high resolution electrical mapping systems for electrocorticography, and “instrumented” multifunctional balloon catheters for cardiac ablation therapy.

Rogers provides an overview of transient applications in this video and more details on his website.

ATMI Inc. has introduced the eVOLV process and system that represents a sustainable solution for recycling electronic waste (e-waste). The safe, cost-effective process is fully automated and uses energy-efficient methods in a scalable, closed-loop system to recover metal resources from electronic circuit boards.

ATMI’s  news came on the second day of the e-Waste Management Summit  in Las Vegas, NV, as part of a panel discussion that included executive director of the Basel Action Network and toxic trade activist Jim Puckett and ATMI’s senior director of sustainable technologies, Dr. Michael Korzenski.

Following green chemistry development principles, the eVOLV process and system was designed as a chemical-based, non-toxic approach that is environmentally benign. It would comply with government guidelines to be free from the restrictions and hazards of traditional "dirty" approaches.

The process includes de-soldering, component/chip recovery, and metal reclaim, with 99% of most metals extracted, and at 99% purity. These metals, which include gold, silver, copper, palladium, lead, and tin, can be recovered and redeployed significantly faster and safer than in most other processes and can re-enter the supply chain as "process-ready" materials.

The amount of e-waste being generated continues to be a growing global concern. According to industry sources, more than 50 million metric tons of e-waste is generated per year, with approximately 72 million metric tons projected by 2014. Much of it ends up in developing countries, where toxic and dangerous processes are being utilized to recover precious metals and components.

The eVOLV chemistries were designed using the 12 principles of Green Chemistry, an approach developed and advocated by the Warner Babcock Institute of Green Chemistry.

While representing less than 2% of the mass in U.S. landfills today, e-waste accounts for 70% of the heavy metals. Approximately 5% of e-waste by weight consists of PWBs and, while some are repaired and resold, most are shipped to destinations outside the U.S. for disposal. Those with high metal value are sold to overseas smelters. Those with low value are sent to Asia or Africa where the chips are manually de-soldered and the trace precious metals are collected either by dangerous open-burning or from chemical leaching using highly toxic chemicals such as hot aqua regia and cyanide–processes that have adverse environmental and personal health implications.

While environmentally impactful, there is also a commercial advantage in recycling. For example, the resource recovery available from recycling one ton of used mobile phones, around 6,000 handsets, is about 3.5 kg of silver, 340 g of gold, 140 g of palladium, and 130 kg of copper. The combined value is just over $25,000, which equates to around $4.2 billion annually. What’s more, one metric ton of e-waste from personal computers contains more gold than that recovered from 17 tons of gold ore.

ATMI is currently processing waste circuit boards at its Danbury, CT, headquarters using the eVOLV system. For more information, end an email to [email protected] or go to www.atmi-evolv.com.

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM). They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction and improves manufacturability. The new architecture also enables the use of a novel “staircase” bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75 nm, 64 cells per string and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional sub-20nm 2D NAND, it can provide 1 Tb of memory if further scaled to 25nm feature sizes. At that size the Macronix device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density.

A previously proposed 3D vertical gate NAND architecture.

An overview of the proposed architectural layout that is said to be an improvement.


A cross-sectional views of the new device.


TEM electron microscope views of the staircase bitline contacts.

Graphene, a one-atom-thick sheet of carbon atoms, is seen as a potential replacement for silicon in future transistors because it has an exceptional set of properties (high current density, mobility and saturation velocity). However, transistors made of graphene cannot be turned off because graphene has almost no band gap.

Researchers have begun to investigate a new 2D material—molybdenum sulfide (MoS)—which has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly. At the upcoming International Electron Devices Meeting (IEDM), an MIT-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter). The transistors demonstrated record MoS mobility (>190 cm2/Vs), an ultra-high on/off current ratio of 108,  record current density (~20 µA/µm) and saturation, and the first GHz RF performance from MoS. The results show MoS may be suitable for mixed-signal applications and for those which require high performance and mechanical flexibility.


The lattice structure of MoS.


A schematic of the CVD process for growing single-layer MoS.


An optical micrograph of single-layer MoS sheets grown by this process, showing great uniformity and coverage.



While conventional charge-based memory is approaching fundamental scaling limits, several so-called “emerging memories” have migrated from laboratory samples to integrated products. Among various emerging memory technologies, MRAM (magnetoresistive random access memory) has been making impressive progress, ahead of other emerging memories, and has demonstrated the capability to be a successor to DRAM or SRAM. MRAM data is stored via magnetic moments. Parallel or anti-parallel magnetic moments in MRAM stacks present the “0” or “1” state. In earlier generations of MRAM, these states were switched by current-induced magnetic field but that is an obstacle for scaling.

The invention of ST (spin-torque) MRAM, which is switched by injecting spin-polarized tunneling current, removes the scaling limitation. In an invited paper at the International Electron Devices Meeting, researchers from Everspin Technologies will describe how they built the largest functional ST-MRAM circuit ever built, a 64-Mb device with good electrical characteristics. The work shows that MRAM technology is fast approaching commercialization.

Everspin MRAM products employ a one transistor, one magnetic tunnel junction (MTJ) memory cell for the storage element. The MTJ is composed of a fixed magnetic layer, a thin dielectric tunnel barrier and a free magnetic layer. When a bias is applied to the MTJ, electrons that are spin polarized by the magnetic layers traverse the dielectric barrier through a process known as tunneling. The MTJ device has a low resistance when the magnetic moment of the free layer is parallel to the fixed layer and a high resistance when the free layer moment is oriented anti-parallel to the fixed layer moment.

ST-MRAM uses an alternate method for programming an MTJ element that has the potential to further simplify the MRAM cell and reduce write power. Programming is accomplished by driving current directly through the MTJ to change the direction of polarization. The read operation is accomplished by sensing the MTJ resistance, just like Toggle MRAM.

Everpsin says that ST-MRAM products will offer a new storage class memory solution for non-volatile buffers and caching applications as well as deliver a new nanosecond-class, gigabyte-per-second non-volatile storage tier. Using a spin-polarized current for switching, ST-MRAM can overcome scaling limitations to address persistent DRAM applications in densities from megabits to gigabits.


The device has a wide separation between applied and breakdown voltages— the more separation, the wider the device operation margin.


This “shmoo plot,” is a graphical display of the ST-MRAM’s performance over a range of voltages. The green area signifies there were no failures of the memory as voltages increased, indicating that its design is robust.

CMOS technology uses the two types of MOSFET transistors (N and P) working together in a complementary fashion: when one is on, the other is off. However, the conflicting materials and design requirements for N- and P-type devices make achieving balanced performance and desired threshold voltage challenging.

Meanwhile, extremely thin SOI (ETSOI) technology is a viable device architecture for continued CMOS scaling to 22nm and beyond. Among the reasons why are that it offers superior short-channel control and low device variability with undoped channels.

At the International Electron Devices Meeting (IEDM) in December, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device. They integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. A novel STI-last (isolation-last) process makes the hybrid architecture possible. The researchers built a ring oscillator circuit to benchmark performance, and the hybrid planar devices enabled the fastest ring oscillator ever reported, with a delay of only 11.2ps/stage at 0.7V, even better than FinFETs.


An electron microscope view at the top and an EDX (energy-dispersive X-ray) spectroscopic view below it of a SiGe-channel PFET with 6-nm channel thickness, 22-nm gate length, 100-nm contacted gate pitch, high-k/metal gate architecture and ISBD SiGe raised source drain. Source: IBM.

Overlay error is the offset in alignment between pattern at one step of a semiconductor process and pattern at the next step. Traditionally overlay error has referred to successive device layers, but in the case of double-patterning lithography, overlay error may stem from interwoven patterns at the same layer. Regardless, controlling overlay error is one of the most difficult issues that lithography engineers face in this era of shrinking design rules and complex, advanced lithography techniques. Because overlay error can affect yield, device performance and reliability, it must be measured precisely, and all sources of systematic overlay error must be discovered and addressed. These may include mask pattern placement error, deviations from wafer planarity, scanner nonlinearities and process variation.

In most cases, overlay error is measured optically by capturing an image of a specially designed alignment mark called an overlay target. Half of the overlay target is printed during the first process step, and the other half of it is printed during the second process step.


A standard overlay target is printed in two steps,  indicated in red and blue, and structured to measure the errors in x and y.

An overlay metrology tool captures the image and quantifies the alignment between the first and second parts of the target. The result is reported as a vector quantity, having a magnitude and direction corresponding to the x and y offsets. The procedure is repeated for each of the overlay targets on the wafer. Overlay error maps are comprised of a circular field of tiny vectors, representing the overlay error across the wafer. These maps are used to adjust the scanner or to uncover issues with the mask pattern, the wafer shape or the process. Overlay error maps are also used to disposition wafers.

Flexible, robust multi-layer target allows simultaneous measurement of overlay error within the same layer and between layers.

A recent development in the area of overlay measurement is extension of measurement capability to new layers and new materials (see above). When overlay error between layers is measured, the optical properties of the top layer are critical to the quality of the data. The metrology tool needs to be able to send photons through the top layer to detect the pattern underneath, and the quality of the image of the buried pattern is critical to the quality of the overall measurement. Because semiconductor processes use a variety of materials, and the optical absorption of a given material generally varies with wavelength, the well-equipped metrology system can select from a variety of wavelengths to achieve sufficient image quality for the buried pattern to enable an accurate, repeatable measurement. The alternative—introducing an extra process step to etch a “window” in the top layer before patterning it—adds significant cycle time and may degrade the underlying pattern. Cycle time pressures are ever-present and well known. Furthermore, when the entire overlay error budget is limited to a small number of nanometers, lithographers cannot afford to allot a large portion of the budget to uncertainty in the output of the overlay metrology tool.

Examples of particularly challenging classes of materials are those used to build 3D transistors, and hard mask materials used during litho-etch-litho-etch lithography. Hard mask materials are opaque to visible light, and their optical properties may fluctuate with composition and even with annealing temperature.  The latest overlay metrology systems can provide an appropriate wavelength that penetrates the top layer, making overlay metrology feasible without additional process steps.

Another new development in the field of overlay metrology is the use of multi-layer overlay targets. New target designs now allow a lithography engineer to measure within-layer overlay and between-layer overlay using one target. These innovative targets are small enough to be inserted into the die without consuming an unfeasible amount of valuable real estate. Their designs are flexible and robust, allowing adjustments for specific process and layer requirements. They are compatible with various pitch-splitting and double-patterning schemes. Most importantly, the new multi-layer targets allow lithographers to measure within- and between-layer overlay error with one image and, at the same time, reduce systematic errors that could degrade the measurement if separate targets had been used.

Overlay metrology remains one of the most challenging issues that lithographers currently face. Innovations in overlay metrology tool and target design must continue, to enable our industry to make smaller, faster, lower power, more affordable chips.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Amir Widmann is a senior director in the Optical Metrology division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

The 58th annual International Electron Devices Meeting (IEDM) will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.

Highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel’s unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM’s demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to vanishingly small sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.

“The IEDM can be a crystal ball looking into the future of technology evolution. Leading-edge technologies and novel devices reported at the conference will shine light on the industrial mainstream in the next three-to-five years,” said Tzu-Ning Fang, IEDM 2012 Publicity Chair and Senior Member, Technical Staff, at Spansion, Inc. “This year’s program shows a tremendous amount of work being done in emerging technologies, including novel materials such as molybdenum sulfide, new structures, 3D NAND memories, wider use of III-V materials, MRAM, nanowires and more.”

Besides the IEDM technical program, attendees will enjoy evening panel sessions, Short Courses, award presentations and other events, as follows:

90-Minute Tutorials — Saturday, Dec. 8

Back by popular demand for the second year, the IEDM will hold 90-minute tutorial sessions on emerging topics presented by experts in the fields. They are meant to bridge the gap between established textbook-level knowledge and the leading-edge research as presented during the conference. The tutorial sessions will be presented in parallel in two time slots. Advance registration is required.

2:45-4 p.m.

High Mobility Channel CMOS Transistors – Beyond Silicon by Shinichi Takagi, University of Tokyo

Fundamentals of GaN Based High Frequency Power Electronics by Tomas Palacios, M.I.T.

Spintronics for Embedded Non-Volatile Electronics by Tetsuo Endoh/Tohoku University and Arijit Roychowdhury/Intel


2D semiconductors – Fundamental Science and Device Physics by Ali Javey, University of California, Berkeley

Scaling Challenges of Analog Electronics at 32nm and Beyond by Mustafa Badaroglu/IMEC and Bram Nauta/University of Twente

Beyond Charge-Based Computing by Kaushik Roy, Purdue University

Short Courses — Sunday, Dec. 9

The IEDM offers two day-long short courses on Sunday, prior to the technical sessions. They provide the opportunity to learn about emerging areas and important developments, and to benefit from direct contact with expert lecturers. Advance registration is required. This year’s courses are:

Emerging Technologies for Post-14nm CMOS

Circuit and Technology Interaction

Plenary Presentations — Monday, Dec. 10

IEDM 2012 will open on Monday, Dec. 10 at 9 a.m. with three plenary talks:

Flexible Bio-Integrated Electronics by John A. Rogers, University of Illinois

State of the Art and Future Prospects in Display Technologies by Joo-Tae Moon, Senior VP, Director R&D Center, Samsung Display Company

Ultimate Transistor and Memory Technologies: Core of a Sustainable Society by Luc Van den hove, CEO and President IMEC

Emerging Technologies Session — Tuesday morning, Dec. 11

This year’s Emerging Technologies session is on the topic Spintronics: Magnetic Materials and Device Applications, organized by Stefan De Gendt of IMEC. Invited speakers from academia and industry will discuss the challenges, prospects and recent advances in spin-based technology, devices and systems. Following the discovery of the giant magnetoresistance (GMR) effect more than a decade ago, this field has witnessed a veritable revolution encompassing materials and physical phenomena. Electronic devices based on spin transport are expected to play a major role in future information and communication technologies, as spintronic devices will use the spin degree of freedom to store, transport and process information. Papers in this session are:

Spin Transport in Graphene: Fundamental Concepts and Practical Implications by Abdelmadjid Anane et al, Unité Mixte de Physique CNRS/Thales

Thermal Spin Transport and Applications by S. Y. Huang et al, Johns Hopkins/National Tsing Hua University/Academia Sinica

Progress of STT-MRAM Technology and the Effect on Normally-Off Computing Systems, by H. Yoda et al, Toshiba

 Spin Transport in Metal and Oxide Devices at the Nanoscale, by Subir Parui et al, Zernike Institute for Advanced Materials

Error Immunity Techniques for Nanomagnetic Logic, Brian Lambson et al, University of California, Berkeley/Lawrence Berkeley National Lab

Boolean and Non-Boolean Computation With Spin Devices, Mrigank Sharad et al, Purdue University

Luncheon Presentation — Tuesday, Dec. 11

The IEDM Luncheon presentation will be given by Ajit Manocha, CEO of GLOBALFOUNDRIES, Inc., on the topic Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!

Evening Panel Sessions — Tuesday evening, Dec. 11

The IEDM will offer attendees two evening panel discussions. Audience participation is encouraged, with the goal of fostering an open and vigorous exchange of ideas. The panel topics are:

"Will Future Non-Volatile-Memory Contenders Disrupt NAND?" moderated by Al Fazio, Intel

 “The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?” moderated by Suresh Venkatesan, GLOBALFOUNDRIES.

Entrepreneurs Lunch — Wednesday noon, Dec. 12

New for 2012 is an entrepreneurs lunch. The speaker will be Weili Dai, cofounder of Marvell Technology Group and Vice President and General Manager of Marvell’s Communications and Consumer Business. One of the most successful women entrepreneurs in the world, she was named No. 89 on the Forbes list of “The World’s 100 Most Powerful Women” earlier this year.

Further information

For registration and other information, interested persons should visit the IEDM 2012 home page at www.ieee-iedm.org.

August 23, 2012 — Global semiconductor market revenue in Q2 2012 fell by 3% year-on-year (Y/Y) to $75.2 billion, resulting in widespread revenue declines for chip suppliers, particularly those headquartered in Japan and Europe, according to the IHS iSuppli Competitive Landscaping Tool.

In a troubling sign for the health of the semiconductor market in 2012, Q2 revenue increased by less than 3% compared to the typically weak first quarter. If the semiconductor industry were on a trajectory for stronger annual growth in 2012, sequential growth would be expected to amount to at least 4% or more in Q2.

The disappointing sequential growth came amid economic concerns such as “the Eurozone crisis, slowing manufacturing growth in China and stubbornly highly unemployment in the US,” said Dale Ford, senior director of electronics and semiconductor research at IHS. “Approximately two-thirds of the world’s semiconductor suppliers saw their revenues decline in the second quarter compared to the same period in 2011. This weak performance bodes ill for the semiconductor industry’s growth prospects for the entire year.”

Also read: 2012 semiconductor revenue forecast bumped up 1 point at IHS and Semiconductor industry revenue targets $323.2B in 2012

Global semiconductor revenue expanded by a marginal 1.4% in 2011. The new IHS forecast calls for an even weaker market in 2012. However, given weakness in the first half of the year, that forecast is likely to be downgraded even further.

Table 1. IHS ranking of the world’s Top 10 semiconductor suppliers in the second quarter based on revenue ($M).



Company Name




of Total












Samsung Electronics








Texas Instruments
























SK Hynix
















Renesas Electronics Corp.
















Micron Technology








Other Companies








Total Semiconductor







Top 10 semiconductor makers face challenges

The revenue decline was felt by companies in all regions. Companies based in all four major global regions saw their collective semiconductor revenues fall Y/Y in Q2.

The drop in revenues among leading suppliers exacerbated the situation. Among the world’s Top 10 semiconductor suppliers, six companies saw their revenues decline compared to the second quarter of 2011.  Four of those companies suffered double-digit revenue declines.


Eurozone crisis

European-based firms took the brunt of the downturn, as the economic crisis in the region took its toll on chip sales.

Among all semiconductor suppliers in Europe, combined revenue in the second quarter fell by 8.3% compared to a year earlier, the worst performance among all global regions, as shown in the figure attached. Two-thirds of all European suppliers saw their revenues fall during the period.


Top European semiconductor suppliers STMicroelectronics and Infineon Technologies saw double-digit year-over-year revenue declines of 16.4% and 12.9%, respectively.


Japanese face seasonal slump

Collective revenue for Japanese semiconductor suppliers retreated by 7.5% in the second quarter compared to the first quarter.

Half of the Japanese chip suppliers experienced decreases in revenue. However, deep drops in revenue by leaders such as Toshiba Corp., Renesas Electronics Corp., Fujitsu Semiconductor Ltd. and Mitsubishi magnified the overall decline.


“This has become a standard pattern for revenue growth for Japanese chip suppliers, as they typically see strong growth during their fiscal year ending March each year — followed by a decline during their first fiscal quarter ending in June,” Ford said. “The expectation is that Japanese suppliers will see a rebound in their revenues in the quarter ending in September.


Table 2. Total Semiconductor Revenue Change by Company Headquarters Location.

Company Headquarters

Q2-11 to Q2-12

Q1-12 to Q2-12

















Figure. Total semiconductor revenue change by company HQ.

Semiconductor winners

Among the world’s Top 10 semiconductor suppliers, Qualcomm stood out with its 23.7% growth, which boosted it to No. 4 in overall rankings, up from seventh place one year earlier. Broadcom also achieved double-digit growth at 10.0%. This pushed the company up one position in the rankings to ninth place.

No. 2-ranked Samsung’s revenues grew by 5.8%, boosted primarily by its acquisition of Samsung Electro-Mechanics.

IHS (NYSE: IHS) is the leading source of information and insight in critical areas that shape today’s business landscape, including energy and power; design and supply chain; defense, risk and security; environmental, health and safety (EHS) and sustainability; country and industry forecasting; and commodities, pricing and cost. For more information, visit www.ihs.com.

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August 21, 2012 — A ranking of the forecasted top 2012 semiconductor foundries (pure-play and IDM) was released by IC Insights. TSMC is expected to remain the leading foundry, with sales almost 4x that of second-ranked GLOBALFOUNDRIES, which in turn is expected to have more than 2x the sales of the fifth-ranked foundry SMIC. Samsung is expected to be the largest of only three IDM foundries in the 2012 ranking with almost 8x the sales of IBM, its closest IDM foundry competitor.

Table. Top 12 IC foundries of 2012. SOURCE: IC Insights, company reports.

2012F rank

2011 rank


Foundry type


2010 sales ($M)

2011 sales ($M)

11/10 change (%)

2012F sales ($M)

12/11 change (%)



































South Korea




























Grace/HHNEC (2012 merger)






















South Korea


















WIN (GaAs)












South Korea






In total, the top 12 foundries in the table are expected to represent 89% of the total foundry sales (IDM and pure-play) in 2012. This share is eight points higher than the 81% figure the top 12 represented in 2009 (before Samsung dramatically ramped up production for Apple). With the barriers to entry (e.g., fab costs, access to leading edge technology, etc.) into the foundry business being so high and rising, IC Insights expects this “top 12” marketshare figure to steadily rise in the future.

For the second year in a row, Samsung is expected to be ranked as the fourth largest IC foundry. However, IC Insights believes that the company will challenge UMC for the number three spot in the ranking in 2013. Samsung has the ability (i.e., leading-edge capacity and a huge capital spending budget) and desire to become a major force in the IC foundry business. It is estimated that the company’s capacity dedicated to its IC foundry business reached 130K 300mm wafers per month in mid-2012. Using an average revenue per wafer figure of $2,500, Samsung currently has the potential to produce annual IC foundry sales of about $3.9 billion.

In 2Q12, Samsung was by far the largest supplier of smartphones in the world, shipping an estimated 54 million handsets with Apple coming in second after selling about 26 million iPhones. Thus, in total, Samsung and Apple represented almost half of the total worldwide smartphone shipments (168 million) in 2Q12. As a result, Samsung is enjoying a tremendous amount of synergy by supplying application processors to the largest (i.e., itself) and second-largest (i.e., Apple) suppliers in the world of one of the hottest electronic system products in the world — smartphones.

After surging by 82% in 2011, Samsung’s IC foundry sales are forecast to jump by another 54% in 2012, which would make it the fastest growing top-12 IC foundry last year and this year. Moreover, Apple’s 2012 share of Samsung’s total foundry sales is expected to be 85%. However, as Apple begins to engage other foundries (e.g., TSMC) to produce its custom processors, Samsung will need to make up for these lost sales by signing up additional large-scale customers.

While Apple and Samsung are currently embroiled in a dramatic courtroom battle concerning various lawsuits and counter-lawsuits regarding system level patents, Apple is still very reliant on Samsung for advanced IC processor production for its iPad tablets, iPhone handsets, and iPod portable media players. It should be noted that TSMC was working at over 100% utilization in mid-2012 and essentially had no ability to allocate large amounts of leading-edge IC production capacity to Apple.

One important factor that is oftentimes overlooked with regards to the Samsung/Apple IC supply relationship is the large amount of memory, both DRAM and flash, that Apple buys from Samsung, the largest IC memory manufacturer in the world. Since Apple is such a big memory customer, Samsung is able to “bundle” its IC offerings to Apple and deliver a cost-effective high-volume supply of leading-edge flash memory, DRAM, and processors to the company. It should be noted that, as of mid-2012, no other foundry in the world could come close to matching Samsung’s total IC supply capabilities. Thus, while Apple and Samsung battle it out in the courtroom over system level issues, at the chip level, Apple must continue to endure its “marriage of convenience” with Samsung.

There is no doubt that Apple is looking to diversify away from being so reliant on its major system level competitor (Samsung) for the production of its advanced ICs. However, IC Insights believes this transition is likely destined to happen over a few years rather than a few quarters.

Overall, IC Insights believes that the leading-edge IC foundry business is going to be very competitive between the four major advanced technology suppliers—TSMC, GlobalFoundries, Samsung, and UMC. With the continued success of the fabless companies as well as the strong movement by many IDMs (Integrated Device Manufacturers like TI, Renesas, ST, etc.) to the fab-lite business model, IC Insights expects the IC foundries to witness very strong demand for their services over the next few years.

IC Insights recently released the 200+ page Mid-Year Update and 30-page August Update to the 2012 edition of The McClean Report. Learn more about IC Insights’ reports and events at www.icinsights.com.

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