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by Debra Vogler, SEMI

In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.

Likely enhancements on the logic roadmap below 20nm are a move to FinFET, improved FinFET implementation, high mobility channel, and gate all around (GAA) structures, noted Adam Brand, senior director, Transistor Technology Group at Applied Materials. He told SEMI that, “The increased complexity of the FinFET, high mobility channel, and GAA devices in combination with continued scaling requires more precision in structure formation and improved materials to address structure formation and parasitic effects.”

The key steps for maintaining the structural integrity of the fin are precision etch, void-free STI fill, recess, and precisely tailored corner rounding through dummy gate oxidation. Dummy gate oxidation addresses the challenge of ensuring that electric fields can be avoided in the corner explained Brand, who will present at SEMICON West 2013 (http://www.semiconwest.org). “The dummy gate serves two purposes,” said Brand. “It’s a structural element and it’s there when you do the transistor formation so it can serve roles such as being the etch stop for the gate etch. It’s also able to play a role in shaping the fin.” The fin can be shaped by changing the oxidation rate depending on the amount of oxidation needed for the side vs. for the corner.

Precision again comes into play when forming the gate — precision CMP is required to control the dummy gate and replacement metal gate height. The dummy gate material must also be easily removed. “Advanced CVD materials offer more choices in materials for differentiating selective removal,” said Brand. “Implant-based precision material modification (PMM) has been effective in changing selectivity to obtain better structure control.” He noted that in the past, CMP had not played a role in directly affecting the geometry of the transistor, but now, it is playing a much more direct role in determining the size of the transistor features. For example, in the replacement metal gate step, CMP is used to polish the metals used for the replacement gate structure and it’s also used for the self-aligned contact polish. “So now, you’re polishing the gate at least three times in order to form it, and you need very precise gate height control because it affects the overall stack height and contact height.”

Further complicating transistor scaling is that the 3-D structure adds complexity in strain-related mobility enhancement. “Source/drain stressor shaping is needed to optimize strain and control unwanted increase in the Miller capacitance,” said Brand.  “Lower k dielectrics are also needed to manage the Miller capacitance.” He further explained that when strain is implemented in a FinFET, each source/drain area is a separate fin — as opposed to when strain is being implemented on planar devices. “When you grow the source/drain [in a FinFET], it grows both horizontally and vertically, so when you scale the pitch of the fins, there’s the challenge that eventually those source/drain stressors come very close to each other and they might merge.” The solution, therefore, has to allow the stressors to grow without having them merge between the transistors and still obtain the amount of strain that is wanted. The solution must also address the Miller capacitance. 

The SOI value proposition changes below 20nm

Gary Patton, VP at IBM’s Semiconductor Research and Development Center, told SEMI that in order for the full benefit of the FinFET to be realized below 20nm, a dielectric isolation scheme is necessary to counter the uniformity and variability challenges. “The arrival of the FinFET era has brought about a fundamental paradigm shift in the SOI value proposition such that the advantages of SOI-based innovation now extend well beyond just device performance as in the planar case,” said Patton.  Indeed, Soitec, and others, such as STMicroelectronics, are betting that SOI-based technology will be used as a bridge enabling the industry to get the performance benefits of a fully-depleted transistor while staying with a planar transistor all the way from 28nm down to 14nm, or perhaps even sub-14nm.

To those who question the added cost of going with an SOI-based platform, Patton said that the cost of dealing with the isolation challenge offsets the cost of using SOI substrates. “Offset costs are due to both additional process steps required for bulk, and increases to die area,” said Patton. “An STI isolation module must be added for bulk FinFETs, as well as a series of masking steps and implants for isolation-leakage control and latch-up avoidance. Estimated additional processing costs of bulk isolation offsets the cost advantage of bulk substrates over SOI.” He also pointed out that die area increases are driven by the need for well contacts, and I/O guard-rings (latch-up avoidance). “We also anticipate the overall die yield to be challenging for the bulk FinFET process due to variability and the need for matching performance of critical circuit paths in a chip.”

Another consideration for proponents of SOI-based technology is the issue of process variability. “A buried oxide layer (BOX) in SOI fins is responsible for three areas of improvement in variability over bulk-isolated FinFETs,” Patton told SEMI. “First, the top silicon layer is terminated by the buried oxide, is proven to be extremely uniform in thickness, and defines the height of the fin both physically and electrically, since any fin over etch does not contribute to the fin height.” He further explained that the source and drain are completely separated by the gated channel, unlike in a bulk FinFET, where there is a continuous path for leakage, requiring a highly doped punch-through stop.

“The non-abrupt nature of doping introduces a non-uniform doping profile, and hence, turn-on current, between the top and bottom of the fin, further eroding the FinFET advantage.” Patton noted that a more practical consideration is the slope or taper of the fin itself. “From an electrical point of view, the ideal fin would be perfectly vertical and of uniform thickness from top to bottom. In a bulk fin process, a degree of taper must allow for the subsequent oxide fill and etch-back, and also to accommodate a reduced spacer over-etch budget (vs. an SOI fin). The fin taper introduces further non-uniformity to the FinFET, which reduces switching speed.”

EDA tackles variability

Reducing/mitigating process variability is ever more critical to yield as the industry scales transistors below 20nm, and much can be done in the design arena to help. For example, EDA considerations can mitigate “noise” in the optical system [lithography] that is a source of variability.

Mike Rieger, group director, R&D, Silicon Engineering Group at Synopsys, uses communication theory to analyze certain aspects of a lithographic system. He told SEMI that when there are optical systems [lithography] without tuning, i.e., a “plain vanilla” system — all the spatial frequencies in the visible limit are present. Conversely, when the design is friendly to specific spatial frequencies and you then try to print that design with an optical system that is friendly to all spatial frequencies, there are other frequencies that leak through. This “leakage” causes a lowering of the contrast in the optical image. “With the lower contrast, the image is more susceptible to other sources of variation like defocused variation, or dose variation, and that translates into your printed features having more variation in their dimensions,” said Rieger, another speaker at the upcoming SEMICON West (http://www.semiconwest.org).

Rieger added that, if you can prevent the unwanted frequencies from even being passed through the optical system, the net result is that the contrast is improved. Additionally, by tuning these frequencies, the diffraction orders in the stepper (the rays of light used to form the image) are manipulated. “You can eliminate the zero order ray. This zero order ray reduces contrast and it also limits the maximum frequency that you can image.” The tuning process – also known as source mask optimization (SMO) – really isn’t the end game, noted Rieger. “It’s source design optimization that is the end game. You tune the configuration of your design to be consistent with the optimization of the source.”

Regarding the parallel paths the industry is taking – extending optical lithography while developing EUVL — Rieger is realistic in his assessment of what EDA can bring to the table. “We’re going to be using 193i for the foreseeable future — it will be years before 193i is replaced,” said Rieger. But, “Optical lithography on a single exposure is maxed out in terms of the density it can print, so if you want to get more transistors per chip or more details per chip, you must do a couple of things.” Those are: tuning the optics, which comes at a cost, and using multiple exposures. “To get an effective result, the whole process of the tuned optics and the multiple exposures must be comprehended in the physical layout software, and some of the things that need to be done go beyond what you can accomplish with the traditional rule-based constraint that you put on the layout.”

For more information on SEMICON West 2013, visit http://www.semiconwest.org. To view all the TechXPOT info, visit http://www.semiconwest.org/SessionsEvents/TechXPOTs.

Register through June 7 at only $50 here: http://www.semiconwest.org/registration. Note that registration fees increase on June 8.


In the second of two installments, Linx Consulting reports a steady growth in semiconductor production, as released in The Econometric Semiconductor Forecast.  The first installment focused on regional developments that will affect semiconductor industry growth.

Semiconductor production to see steady growth after 2013

The weakness in economic growth spills into end products containing semiconductors in 2012 and early 2013.  Our model relating final demands to aggregate semiconductor production (measured by SEMI’s Million Square Inches of silicon processed, MSI) suggests weak demand was anticipated in 2012, and that by early 2013, enough improvement in end markets occurs to push growth up at a modest pace that averages slightly less than 6% for the full year.   By 2014, growth should recover to long-term potential growth for MSI of approximately 7%/year.


Figure 1: Aggregate semiconductor production from 1955 to present, with forecast to 2015.

Key assumptions driving this forecast include some solution to the fiscal cliff dilemma that permits US consumers and businesses to begin to return to more normal conditions.  Removing uncertainty drives a modest expansion US spending on technology goods of around 2.3%, up from the anemic 0.8% growth anticipated for 2012.  Most of that growth will occur in the second half of 2013, as it will take some time for businesses to analyze the new policy environment and then implement investment plans.  Inventory-shipment ratios for technology goods, which are spiking in the last half of 2012, are assumed to recede on a steady pace to more typical levels through 2013.  If shipments in IT goods do not develop as expected, the quarterly pattern above would most likely show a steeper decline in 2012Q4 and a further decline in 2013Q1, followed by strong gains in Q2 or Q3.


Figure 2: The difference between Segment Demand and Total Silicon Area (includes test and monitor wafers).

Strongest growth will remain in flash memories and logic devices

The overall picture of MSI growth breaks down into the expected performance of device segments and technology nodes.  Despite the shift to consumer electronics and mobile platforms, we expect growth to be concentrated in CMOS products with a continuing slowing of unit growth and analog and discrete devices.  Strongest growth will remain with flash memories, and advanced foundry logic devices targeted at tablets and phones.

In contrast with advanced memory and logic processing, approximately 56% of the market continues to be produced at design dimensions in excess of 100 nm on wafer sizes at 200 mm or smaller.  This market segment is extremely sensitive to economic volatility and has slowed significantly in the last four years.  Manufacturers of these devices are often capital constrained and extremely cost sensitive, leading to little process innovation and limited capacity expansion.

More silicon area at 32 nm produced in 2012 than any other node

On a technology basis, despite tight capital budgets, the introduction of devices at 28 and 22nm half pitches continues apace, and significant process challenges are driving increased complexity and resultant challenges in patterning, cleaning, CMP and deposition throughout the device manufacturing process.  2012 is forecast to have produced more silicon area at 32nm than any other node, and the introduction of low 20nm half pitches and flash has continued to grow startling rates. 

In total devices manufactured at 65nm and below continued to show strong area growth in 2012 of 14%, with devices at 90nm and above largely offsetting declines from 2011 with 8% growth in 2012, but flat performance on average.



LED market discussedWith increasing awareness of global climate change and the importance of energy conservation, more and more countries have launched LED lighting projects and subsidy policies. As a result, even though the growth of the LED market in 2012 was hampered by global economic challenges, overall demand has continued to be on the rise. To help the Taiwan LED industry tackle the increasing challenges, an in-depth analysis of LED global market opportunities and technology breakthroughs were recently provided at the 2013 LED Market and Outlook seminar held by SEMI Taiwan.

Demand for high-power white LED is now growing at a rapid pace. Yellow and natural light LEDs will both exceed 200 lumen/watt in power rating by 2015 and even surpass 250 lumen/watt by 2020. OEM bulb prices are expected to drop from US$ 23 per 1,000 lumen in 2012 to $10 per 1,000 lumen in 2015 and then down to $5 per 1,000 lumen by 2020. The next few years will therefore see strong growth in the LED lighting market.

LED lighting market continues to grow from 2011 to 2016

Daphne Kuo, an analyst with ITRI Industrial Economics & Knowledge Center, added that the global market for general lighting has an annual growth rate of between 3 and 6%. The global market is expected to be worth $114.7 Billion in 2020, with the LED lighting market reaching a compound annual growth rate of 45% between 2011 and 2016, and 15% between 2016 and 2020. The LED lighting market could therefore reach a value of $79 billion.

In terms of the LED lighting market structure, LED home lighting will be the largest market in 2020 at $32.1 billion accounting for 41 percent of the total LED lighting. The next two largest markets will be outdoor and office lighting, with both approaching $11.3 billion. The overall market will itself be divided into the new installation market and the replacement market. The relative scale of the two markets is approximately 80:20. The scale of the replacement market is however expected to begin contracting after 2015 as LED penetration increases and lighting technology improves.

Different regions show different approaches to LED market

According to Kuo, currently Western nations account for 50% of the general lighting market and the Asian market accounts for 40%, so these two large regional markets remain evenly balanced. However, future growth will be driven mainly by emerging nations, and the BRICs in particular, because of strong government support for LED lighting. China will be the largest among them and account for approximately 70% of the BRIC lighting market. The China market is estimated to account for 45% of all demand in Asia, or 18% of the global lighting market.

Nevertheless, demand for LED lighting in China mainly comes from government projects. With local firms and governments joining forces to protect their vested interests, it is very difficult for outside firms to make any headway. Any company wishing to enter the China market must pay attention to the parochial nature of the lighting market. Adopting a profit sharing model and establishing a solid partnership with regional lighting channel operators is essential when entering the LED lighting market in China.

Keys to market: Lower production cost and improve efficiency

In addition to the market challenges, there will also be a number of technological challenges in the future. EPISTAR’s Carson Hsieh noted that solving problems with thermal resistance remains the number one priority. The current trend is using Flip-Chip technology to reduce chip-level thermal resistance. Another approach is to improve light emission efficiency. Light emission efficiency is in turn governed by internal quantum efficiency and light extraction efficiency. While improvements have been made in internal quantum efficiency, factors such as material absorption, uneven current distribution, and threshold loss mean that even high internal quantum efficiency within the LED produces relatively little external light. The bottleneck in LED light extraction efficiency must therefore be overcome.

The current trend is using Patterned Sapphire Substrate (PSS) technology as it has the advantage of increasing LED light extraction efficiency. Another method, called Nano Patterned Sapphire Substrate (NPSS), not only increases light extraction efficiency but also boosts epi wafer output. Increasing light extraction efficiency will not only boost overall light emission efficiency but also reduce thermal loss, allowing LED bulbs to do away with heat sinks and reduce costs even more.

By using GaN LED on Si technology to grow the epi layers on large silicon wafers, it will also be possible to adopt a production process that is compatible with semiconductor production lines and significantly reduce overall costs as well. However, GaN has a far higher thermal expansion coefficient than silicon so this may lead to technical problems such as epitaxial film rupture or wafer warping that will need to be overcome in the future.

Technology breakthroughs lead to further reductions in LED costs. This will in turn increase market acceptance and usher in of the era of high growth for the LED lighting market.

STATS ChipPAC Ltd. (SGX-ST: STATSChP) and United Microelectronics Corp. (NYSE: UMC; TWSE: 2303) announced the world’s first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. The 3D chip stack, consisting of a wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, successfully reached a major milestone on package-level reliability assessment.

"The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models," said Shim Il Kwon, VP of Technology Innovation of STATS ChipPAC.

S.C. Chien, vice president of Advanced Technology Development at UMC, said, "We see no imperative to restrict 3D IC to a captive business model, as UMC’s development work with nearly all the major OSAT partners for 3D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach. This model should work especially well for our mutual 3D IC customers, as foundry and OSAT can utilize their respective core strengths during development and delivery, while customers can benefit from keeping supply chain management flexible and realize better transparency over technology access compared to closed, captive 3D IC business models."

Under the 3D IC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC’s 28nm poly SiON process flow. The know-how developed will be applied towards implementation on the foundry’s 28nm High-K/metal gate process. For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking.

Chip inventory held by semiconductor suppliers reached alarmingly high levels in the third quarter of 2012 amid weak market conditions, according to an IHS iSuppli Semiconductor Inventory Insider Market Brief from information and analytics provider IHS (NYSE: IHS).

Overall semiconductor revenue declined by 0.7 percent sequentially during the fourth quarter last year. The poor results came after inventory reached exceedingly high levels by the end of the third quarter in 2012, amounting to 49.3 percent of total semiconductor revenue—more elevated than at any point since the first quarter of 2006.

Chip stockpiles among semiconductor suppliers had actually gone down during the final two quarters of 2011, showing a promising drawdown, as depicted in the figure attached. But then inventories steadily ticked up again after that, reaching 47.5 percent of total revenue in the second quarter before hitting the current peak in the third—the latest time for which full figures are available.

The inventory level being measured refers to chip stockpiles specifically in the hands of semiconductor suppliers, not to inventory throughout the electronics supply chain. Chip level at the supplier level is then compared against combined revenue from a sample of 75 semiconductor supplier companies excluding memory, which is tracked separately because of that market’s typical late results. A low inventory-to-revenue ratio is preferable, given that higher levels indicate not only unsold stockpiles but also unrealized revenue tied up with the stagnant inventory.

 “The uncomfortably high level of inventory among semiconductor manufacturers of nearly all stripes is a result of key demand drivers failing to materialize,” said Sharon Stiefel, analyst for semiconductor market intelligence at IHS. “Demand for semiconductor devices has typically come from new products that consumers feel compelled to purchase. But going into the holiday season last year, no such new products marshaled enough impetus to overcome consumer fears about lingering economic woes. Two months prior to Christmas, consumer purchases of electronics had grown by only 0.7 percent, the worst performance since 2008.”

Also contributing to depressed conditions was the poor performance of the industry’s data processing segment, traditionally the largest user of semiconductors. In fact, mobile PCs were projected to decline in 2012 when final figures are tallied, toppled from dominance by media tablets. Ultrabooks and other ultrathin PCs, meanwhile, did not produce the demand for semiconductors originally expected as the year progressed.

Despite the collective rise in inventory stockpiles, some semiconductor segments performed better than others. For instance, with feature-rich smartphones and tablets taking the place of traditional PCs among consumers and eroding PC market share, the devices were anticipated to provide the strongest demand in the final quarter of 2012. As a result, semiconductor revenue for the wireless segment was expected to climb almost 4 percent. Semiconductor sectors benefiting from the tremendous growth of handsets and tablets included logic, analog and NAND flash memory, with those semiconductor channels refilling following strong shipments even into the beginning of this year.

The first quarter of 2013 likely will see growth in the industrial and automotive electronics segments. Other semiconductor markets, for their part, will overcome the seasonal decline normally expected at this time of year and then start to rebound around the second and third quarters. Such assumptions, however, rest on the even larger factor of the global economy, currently a volatile variable itself with no set outcome. If global economic forecasts perform according to positive expectations, semiconductor revenue could grow by 4 percent in the second quarter and by a very solid 9 percent in the third. However, if demand evaporates, semiconductor suppliers will find themselves in a deplorable oversupply situation, which would then lead to inventory write-downs throughout the year.

Thomas Edison invented the first incandescent light bulb 130 years ago, which greatly contributed to the advancement of civilization. However, that technology is antiquated, economically inefficient to operate, and fragile.

Fluorescent lights are energy efficient but they are bulky and have to ‘warm-up’ when turned on. Their bulbs contain phosphorus and mercury, which are toxic to the environment. Today’s LED lights are also energy friendly but are expensive and difficult to manufacture. The process to make conventional LEDs is very complicated, as it involves the growth of single crystal layers on the single crystal substrate. Each layer has to contain low defects for it to work. The cost of LED lights is usually ten times the cost of the incandescent bulb, because the equipment to produce them is expensive, the raw materials are expensive, and the environmental and safety issues are critical. Another disadvantage of the current LEDs is they do not produce white light from a single chip. This requires extra manipulation, such as using a set of 3 chips emitting different lights or adding a phosphors material to the blue or UV chip to produce the white light. 

Professor Yue Kuo of the Artie McFerrin Department of Chemical Engineering at Texas A&M University has fabricated a new type of LED, capable of producing a wide spectrum light while operating for long periods of time at atmospheric conditions. This device is based on a new concept of light emission from an ultra-thin amorphous dielectric layer.     

Figure (left) Low- and (right) high-magnification photos of light emission from the new LED.

An article published in Applied Physics Letters, describes the light emission mechanism, characteristics of the emission spectrum, fabrication method, and the operation parameter effects on this type of LED. The device was fabricated with the room-temperature sputter deposition method on a silicon wafer. The light emission intensity could be enhanced with a nanocrystal layer embedded in the dielectric film. Most importantly, the complete process and materials are compatible with the existing IC fabrication facility.

“There is a need for a new type of LED that is: low cost, long operation life, small in size, emits white light, and easy to fabricate with environmentally friendly materials and process.” Dr. Kuo says. “ What makes this new LED unique is it meets all of these requirements plus it is extremely easy to fabricate with the existing equipment in all semiconductor fabs.” 

The light emitted is composed of small bright dots evenly distributed across the electrode surface.  The input voltage controls the intensity or brightness of the LED.  Dr. Kuo is very optimistic with the results of his findings. “We have discovered this phenomenon and studied this kind of LED for more than a year. It can be operated continuously for more than ten hours. A longer operation time is expected.”

Kuo‘s discovery has larger implications than just lighting. These LEDs could potentially be integrated into a computer processor; dramatically increasing the speed by transporting signals optically rather than by electrons through copper lines.  They could have use in various industries, entertainment, medical, commercial, and military areas due to the compact size and low cost. 

By Rebecca Howland, Ph.D., and Tom Pierson, KLA-Tencor.

Is it time for high-brightness LED manufacturing to get serious about process control?  If so, what lessons can be learned from traditional, silicon-based integrated circuit manufacturing?

The answer to the first question can be approached in a straight-forward manner: by weighing the benefits of process control against the costs of the necessary equipment and labor.  Contributing to the benefits of process control would be better yield and reliability, shorter manufacturing cycle time, and faster time to market for new products. If together these translate into better profitability once the costs of process control are taken into account, then increased focus on process control makes sense.

Let’s consider defectivity in the LED substrate and epi layer as a starting point for discussion. Most advanced LED devices are built on sapphire (Al2O3) substrates. Onto the polished upper surface of the sapphire substrate an epitaxial (“epi”) layer of gallium nitride (GaN) is grown using metal-organic chemical vapor deposition (MOCVD).

Epitaxy is a technique that involves growing a thin crystalline film of one material on top of another crystalline material, such that the crystal lattices match—at least approximately. If the epitaxial film has a different lattice constant from that of the underlying material, the mismatch will result in stress in the thin film. GaN and sapphire have a huge lattice mismatch (13.8%), and as a result, the GaN “epi layer” is a highly stressed film. Epitaxial film stress can increase electron/hole mobility, which can lead to higher performance in the device. On the other hand, a film under stress tends to have a large number of defects.

Common defects found after deposition of the epi layer include micro-pits, micro-cracks, hexagonal bumps, crescents, circles, showerhead droplets and localized surface roughness. Pits often appear during the MOCVD process, correlated with the temperature gradients that result as the wafer bows from center to edge. Large pits can short the p-n junction, causing device failure. Submicron pits are even more insidious, allowing the device to pass electrical test initially but resulting in a reliability issue after device burn-in. Reliability issues, which tend to show up in the field, are more costly than yield issues, which are typically captured during in-house testing. Micro-cracks from film stress represent another type of defect that can lead to a costly field failure.

Typically, high-end LED manufacturers inspect the substrates post-epi, taking note of any defects greater than about 0.5mm in size. A virtual die grid is superimposed onto the wafer, and any virtual die containing significant defects will be blocked out. These die are not expected to yield if they contain pits, and are at high risk for reliability issues if they contain cracks. In many cases nearly all edge die are scrapped. Especially with high-end LEDs intended for automotive or solid-state lighting applications, defects cannot be tolerated: reliability for these devices must be very high.

Not all defects found at the post-epi inspection originate in the MOCVD process, however. Sometimes the fault lies with the sapphire substrate. If an LED manufacturer wants to improve yield or reliability, it’s important to know the source of the problem.

The sapphire substrate itself may contain a host of defect types, including crystalline pits that originate in the sapphire boule and are exposed during slicing and polishing; scratches created during the surface polish; residues from polishing slurries or cleaning processes; and particles, which may or may not be removable by cleaning. When these defects are present on the substrate, they may be decorated or augmented during GaN epitaxy, resulting in defects in the epi layer that ultimately affect device yield or reliability (see figure).

Patterned Sapphire Substrates (PSS), specialized substrates designed to increase light extraction and efficiency in high-brightness LED devices, feature a periodic array of bumps, patterned before epi using standard lithography and etch processes. While the PSS approach may reduce dislocation defects, missing bumps or bridges between bumps can translate into hexes and crescent defects after the GaN layer is deposited. These defects generally are yield-killers.

In order to increase yield and reliability, LED manufacturers need to carefully specify the maximum defectivity of the substrate by type and size—assuming the substrates can be manufactured to those specifications without making their selling price so high that it negates the benefit of increased yield. LED manufacturers may also benefit from routine incoming quality control (IQC) defect measurements to ensure substrates meet the specifications—by defect type and size.

Substrate defectivity should be particularly thoroughly scrutinized during substrate size transitions, such as the current transition from four-inch to six-inch LED substrates. Historically, even in the silicon world, larger substrates are plagued initially by increased crystalline defects, as substrate manufacturers work out the mechanical, thermal and other process challenges associated with the larger, heavier boule.

A further consideration for effective defect control during LED substrate and epi-layer manufacturing is defect classification. Merely knowing the number of defects is not as helpful for fixing the issue as knowing whether the defect is a pit or particle. (Scratches, cracks and residues are more easily identified by their spatial signature on the substrate.) Leading-edge defect inspection systems such as KLA-Tencor’s Candela products are designed to include multiple angles of incidence (normal, oblique) and multiple detection channels (specular, “topography,” phase) to help automatically bin the defects into types. For further information on the inspection systems themselves, please consult the second author.

Rebecca Howland, Ph.D., is a senior director in the corporate group, and Tom Pierson is a senior product marketing manager in the Candela division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

The International Data Corporation (IDC) is forecasting that semiconductor revenues worldwide will improve by 4.9% to $319 billion in 2013 and log a compound annual growth rate (CAGR) of 4.1% from 2011-2016, reaching $368 billion in 2016. Bright spots for the semiconductor market include smartphones, tablets, set-top boxes, and automotive electronics, which IDC expects will continue to be key drivers of growth over the coming years.

The group said that 2012 saw a nominal growth of less than 1% reaching $304 billion, due to weakness in PC demand, DRAM and overall memory price deterioration, and semiconductor inventory rationalization. This was coupled with continued global macroeconomic uncertainty from lower global GDP growth, a slowdown in China, the Eurozone debt crisis and recession, Japan’s recession, and ongoing fear of fiscal cliff negotiations’ impact on IT spending by corporations.

IDC expects semiconductor inventories to come into balance with demand in the second quarter of 2013 with growth to resume in the second half of 2013. "We expect lower, but positive global GDP growth in 2013. Semiconductors for smartphones will see healthy revenue growth as appetite for data, multimedia processing, and multitasking will drive high-end smartphone demand in developed countries while an ongoing transition to 3G networks will accelerate smartphone adoption in developing regions. PC demand will continue to remain in a period of transition next year until more technology and design innovation begin to change the course of demand," said Mali Venkatesan, research manager for semiconductors at IDC.

Regionally, Japan and Europe continue to be the two weakest regions. Although GDP growth has slowed in China, India, and Brazil, demand for smartphones, tablets, and automotive electronics remains strong. In the U.S., 4G phones, mobile consumer devices (tablets and e-readers), network infrastructure, and set-top box deployments will drive a healthy semiconductor growth cycle over the next five years.

Other key findings from IDC’s Semiconductor Application Forecaster include:

  • Semiconductor revenues for the Computing industry segment will log year-over-year growth of 1.7% for 2013 and will show a muted CAGR of only 1.7% for the 2011-2016 forecast period. Semiconductor revenues from mobile PC demand will register 5.5% year-over-year growth in 2013, after declining 7.7% in 2012.
  • Semiconductor revenues for the Communications segment will grow 6.5% year over year in 2013 with a five-year CAGR of 5.5%. Semiconductor revenues for 4G phones will experience annual growth of 140.1% in 2013 and a CAGR of 103.4% for 2011-2016.
  • Media tablets, e-Readers, set-top boxes, and blu-ray players, will continue to see above average semiconductor revenue growth. Sales of traditional devices such as DVD players, DVD recorders, DVD players, portable media players, and game consoles will continue to erode. Overall, semiconductor revenues for the Consumer segment will record year-over-year growth of 9.8% in 2013 and a 2011-2016 CAGR of 6.0%.
  • Driven by strong global demand for automobiles and increased semiconductor content (i.e. applications such as in-vehicle infotainment, automobile body electronics, and driver safety systems), semiconductor revenues for the Automotive segment is expected to grow 5.9% (CAGR) for the five-year forecast period.
  • Regionally, Asia/Pacific will continue to grow its share of semiconductor revenues, with year-over-year growth of 5.5% in 2013 and a five-year CAGR of 5.3%.

IDC’s Worldwide Semiconductor Applications Forecaster database serves as the basis for all IDC semiconductor supply-side documents, including market forecasts and consulting projects. This database contains revenue data collected from the top 100 semiconductor companies for 2006-2011 and market history and forecasts for 2006-2016. Revenue for over twelve semiconductor device areas, four geographic regions, six industries, and more than 80 end-device applications are also included in the database.

By Mark Thirsk, Managing Partner, Linx Consulting LLC.

Past contributors have often noted a correlation between the semiconductor market growth and global GDP.  With careful correction this correlation can be used to forecast future IC market trends, although the process is not straightforward.

The consensus forecast for global GDP 2013 is now below trend at 2.6%, only a slight improvement over 2012, and less than the 3.2% seen in 2011.  The US approach to solving fiscal Cliff is an excellent example of the difficulty governments are having in developing strategies to address unprecedented economic problems, although political solutions, however imperfect, helps to stabilize expectations, and solidify financial markets.  In Europe, mild recession will continue through most of 2013, and Asia (excepting Japan) will likely show the best overall growth rates in the coming 12 months as measures to cool the Chinese economy are relaxed.

These extraordinary conditions in the global economy lead to wide variations in economic forecasts with an upside as high as 3.5 % growth, and a pessimistic case as low as 1%.  Against this backdrop, meaningful macroeconomic demand-side forecasts are difficult to develop.

Linx has worked with Hilltop Consulting to implement a proven macroeconomic forecasting tool that takes into account the global economic shocks and volatility to develop an Silicon area forecast for the global semiconductor industry.  Predictions for 2013 show several notable trends: 

  1. Overall Si area growth for 2013 should average approximately 6%. 
  2. The first quarter and the second half are likely to show slower growth than the second quarter.  This trend is part of a seasonality which has been swamped by economic volatility over the last 3 to 4 years. 
  3. The modest growth forecast for 2013 is predominantly demand driven since inventory levels have not shown a significant spike in 2012.

The overall picture of Si area growth breaks down into the expected performance of device segments and technology nodes.  Despite the shift to consumer electronics and mobile platforms we expect growth to be concentrated in CMOS products at ≤ 65nm with a continuing slowing of unit growth and analog and discrete devices.  Strongest growth will remain with flash memories, and advanced foundry logic devices targeted at tablets and phones.

In contrast to advanced memory and logic processing, approximately 56% of the Si production continues at design dimensions in excess of 90 nm on wafer sizes of 200 mm or smaller.  This market segment is extremely sensitive to economic volatility and has declined somewhat in the last four years.  Manufacturers of these devices are often capital constrained and extremely cost sensitive, leading to little process innovation and limited capacity expansion.

On a technology basis, despite tight capital budgets, the introduction of devices at 28 and 22 nm half pitches continues apace, and significant process challenges are driving increased complexity and resultant challenges in patterning, cleaning, and deposition throughout the device manufacturing process.  2012 is forecast to have produced more silicon area at 32 nm than any other node, and the introduction of low 20 nm half pitches and flash has continued to grow startling rates.  Significant challenges also exist in the in the advanced device markets due to geometric constraints and physical limits in scaling planar devices.  At a time when lithography is unable to scale continuing device shrinks results in added complexity in critical patterning steps and demands the addition of multiple lithography steps to achieve a single pattern level.

Manufacturers of logic and memory alike are working to develop substitute technologies for planar transistors, MIM capacitors and floating gate structures.  The broad introduction of metal gate finFETs, new types of storage cells, and three-dimensional memory stacks is still several years away, and this is driving interest in the adoption of three-dimensional packaging technologies such as through silicon vias to continue delivering increasing functionality in a package.

Despite the headwinds of increasing layer counts to compensate for the lack of high resolution lithography, and the need for new deposition technologies needed for novel processes and device architectures, we expect a small group of wafer makers to continue to chase these advanced technologies, while also pushing to implement 450 mm wafers.  Few of these technologies will see implementation in 2013, but they will be the focus of headlines as new breakthroughs are made, while the semiconductor industry continues its trend of remarkable success.


By Jean-Christophe Eloy, President & CEO, Yole Développement

Sensors and optoelectronics will continue to grow faster than the mainstream semiconductor market. We currently expect 9%-13% growth in these sectors in 2013, accompanied by rapid changes in technology and  market structures as well, as the specialty markets become increasingly mature. 

MEMS and image sensors will continue to ride the smart phone and tablet wave, while declining LED bulb prices will start to push the technology towards wider adoption. Demand for power electronics will pick up after its 2012 plunge.

We expect the MEMS market to continue its steady double digit growth with an ~9-11% increase to around $12 billion in 2013, driven of course by increasing adoption of the sensors in the expanding smart phone and tablet business. We expect the penetration of accelerometers into mobile phones and tablets will approach 65% by the end of 2013, with magnetometers nearing 54% and gyroscopes flirting with 34%. Growth will begin to transition from discrete sensors to combinations of two sensors in one package with a single ASIC to reduce costs, and to increasingly sophisticated software solutions that translate the sensor data into usable functions.  These trends are driving changes in the competitive landscape, with a crowd of new players targeting the key 3-axis gyroscope market, others introducing other new MEMS applications for the mobile market, chipset and software suppliers taking over the sensor management tasks, and a diversification of business models as the industry evolves. Healthy increases in the smart phone applications—and in other consumer products increasingly enabled by these low cost, easy to integrate product—will be somewhat countered by slower growth in mature TV and printer applications.

The smart phone and tablet market is also driving healthy growth in CMOS image sensors.  We expect ~11-13% growth to $7.5B in 2013.  Backside illumination and 3D wafer-level packaging technologies will continue to rapidly gain market share, and new stacked sensor architectures will likely follow soon.  These technological changes are bringing changing business models as well, as IDMs who are not vertically integrated up through the systems level will increasingly turn to outsourcing production to foundries. 

In the high brightness LED market, the TV backlighting market has slowed and the solid state lighting market has yet to really take off, but we still expect respectable ~10% growth for packaged LED devices in 2013, as rapidly improving technology, and an excess supply of devices from the backlight side, will drive down LED bulb prices to start to drive wider adoption. We expect LED penetration of the lighting market across all segments  (residential, industrial, outdoor and commercial) to reach about 8% of all lamps sold in 2013, to occupy about 2% of all lamp sockets. As in most of these non CMOS chip sectors, however, demand for more die doesn’t necessarily translate into demand for more manufacturing equipment.  We expect sales of front end equipment in 2013 to recover about 30% from its 2012 dropoff, but not back to peak levels of the boom years. Companies will start adding capacity again in the second half of the year for the ramp up in wafer area needed for the volume lighting market.  But some of that capacity will come from stronger producers acquiring struggling suppliers and their underutilized equipment.

We expect recovering demand for discrete power devices to drive ~10%  growth in power electronics to some $20 billion in 2013, after what we estimate was a ~20% drop  in 2012 as China cut back on its big investments in railroad, solar power and wind power systems.  Going forward, green tech demand from hybrid/electric vehicles, wind and PV systems should again help spur sales in 2014-2015, and then support stable 6%-7% long term growth after 2016.