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January 3, 2012 — Solid State Technology asked top analysts and technologists to provide insights on the transition to 22nm semiconductor devices. Read through all the forecasts, or click by topic, from chip design to lithography, CMP, and materials, to the packaging side of the equation.

Check out the first article, from Dean Freeman of Gartner Inc:
Semiconductor process technology challenges at 22nm

And a design perspective, from Gary Smith of Gary Smith EDA:
At 22nm, leave chip layout to the experts

Defect discussion, with Howard Ko of Synopsys:
First order effects at 22nm

The lithography point of view, with Aki Fujimura, D2S:
Mask-wafer double simulation: A new lithography requirement at 22nm

What 22nm means for the packaging providers, from E. Jan Vardaman, TechSearch International:
22nm requires foundry-to-packaging-house cooperation

An in-depth look at gate stacks and materials, with Mohith Verghese, ASM America:
Strained silicon and HKMG take the stage at 22nm

The role of a mid-node, TSVs, and 450mm at 22nm, with Art Zafiropoulo, Ultratech:
Will 22nm need a mid-node?

The CMP point of view, from Michael A. Fury, Techcet Group:
Startups pave the way to CMP at 22nm

Driving technologies for 22nm lithography, from Franklin Kalk, Toppan Photomasks:
20nm mask technology relies on SMO and DPT

How 3D IC fits into the 22nm equation, with Paul Lindner, EV Group:
3D integration key to 22nm semiconductor devices

December 30, 2011 — As the semiconductor industry moves into the 22nm silicon technology node, device fabrication is not the only challenge that the industry will face. According to the International Technology Roadmap for Semiconductors (ITRS), a porous ultra-low-k (ULK) material will replace the traditional silicon dioxide. Stresses within the die must be controlled, not only during wafer fabrication, but also in packaging and assembly.

This will be even more challenging than the industry

December 30, 2011 — At the 20nm semiconductor process node and beyond, multiple masks — each with complex mask shapes — are needed to achieve sufficient process window in the wafer for the critical layers. The complex shapes are created by optical proximity correction (OPC) adding a large number of sub-resolution assist features (SRAFs) and main features requiring complex contours.

At these advanced nodes, where these assist features are smaller than 80nm in width, the challenge lies in printing the image faithfully on the mask. Because of the radius of the combined short-range blur from the electron beam (e-beam) used to write masks plus mask-process effects, a 60nm square feature, for example, does not print as a square, but as a smaller-sized circle with poor dose margin (DM).

Wafer simulation can provide insight into what will print on the wafer. However, all traditional wafer simulation technologies assume that mask writing is accurate within a small corner-rounding effect. Accurate mask-wafer double simulation is a new, required step for the 20nm node and beyond because corner rounding becomes the dominant effect with these small features, particularly when they have complex shapes that are not just orthogonal rectangles.

Mask-wafer double simulation is also necessary for advanced nodes because of the explosion of mask data volume caused by all the complex images required for advanced designs. Cost-effective manufacturing of semiconductors requires both reasonable mask write-times and good wafer yield. But more complex masks that produce good wafer results often cost too much in terms of mask write-times to be practical. Trade-offs must be made between results on the wafer and mask write-times; therefore, engineers require information on how a particular mask image will print, both on the mask and on the wafer, coupled with information on the shot-count required to produce that image.

Accurate mask-wafer double simulation for intelligent trade-offs should include views into each step of the mask/lithography process, including e-beam simulation, DM/edge-slope analysis, mask-process simulation for develop, bake and etch effects, lithography simulation and lithography contour simulation. The simulations must run fast enough to be interactive, so that various trade-offs can be compared in a reasonable timeframe.

As the semiconductor industry moves toward each new process node, new challenges arise. At the 20nm process node, mask fidelity and shot-count explosion are two of those problems that are now constraining the wafer results. The industry will need to transition from the traditional bundled models that assume mask fidelity to the separated-model approach provided by mask-wafer double simulation.

Aki Fujimura is CEO of D2S Inc. The company is managing sponsor of the eBeam Initiative.

This article is part 4 of a series of 22nm forecasts from Solid State Technology contributors.

Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner

Part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA

Part 3: Focus on first order effects at 22nm by Howard Ko, Synopsys

Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 7: Will 22nm need a mid-node? by Art Zafiropoulo, Ultratech

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group

December 28, 2011 — The transition from 32nm to 22nm silicon will have a major impact on the semiconductor design community. The most obvious is the increase in process variation. This affects timing, but more importantly, it affects power. Because of this, we are seeing a dramatic increase in the 22nm process design rules. More and more design teams will decide to leave the IC layout portion of the design to the experts.

The effects of 22nm on the EDA vendors will be a combination of opportunity and shrinking IC layout seat count. Although the new design rules moving toward structured silicon reduce the need for optical proximity correction (OPC) tools, the move to double-patterning lithography raises new challenges for OPC tools, resulting in overall market growth. The variation problems will also drive the demand for design-for-yield (DFY) tools. The new variation challenges require that IC place-and-route tools actively ensure the robustness of the final layout, therefore, growing the IC layout market for those tools that keep up with the 22nm challenge.

This shift in responsibility won

December 28, 2011 — According to the Mayan Calendar, the world is supposed to end in December of 2012. The microprocessor will be over 40 years old, and 22nm devices will be ramping in production. 2012 promises much for the semiconductor industry, and the world.

The chip industry will see two different device types ramping in 2012: second-generation 2xnm NAND flash, and Intel

December 26, 2011 — Yole Développement studies the evolution of inertial micro electro mechanical systems (MEMS) and magnetometers and provides reverse costing analysis of the MEMS devices in "Technology Trends for Inertial MEMS," volumes 1 & 2. The report considers 23 MEMS devices.

Four identifiable trends are revealed: future generation of sensors will deliver functions; sensor fusion, combining data from different sensors, is on the rise; new architectures are emerging; and price pressure is still very strong (5% drop per quarter for consumer applications), said Laurent Robin, activity leader, inertial MEMS devices and technologies at Yole Développement.

Yole’s report shares market drivers for inertial MEMS, including consumer, automotive, and high-end applications. Packaging and test trends for the devices are discussed. Over the last 3 years, inertial MEMS & magnetometers have been subject to dramatic market & technological evolutions. This has been driven by a large increase of the consumer market: mobile phones and tablets for accelerometers; gaming for gyros; mobile phones for magnetometers.

Along with “stand-alone” MEMS devices, inertial combo sensors, a combination of several inertial sensors into a single package, are also coming. Main applications are consumer (e.g. accelerometer with magnetometer or accelerometer with gyro) and automotive for ESC and rollover functions first.

On the technical side, form factor is ever decreasing with reduced footprint and thickness. And power consumption has been reduced to a few microA while performances are still increasing. The most successful type for inertial MEMS is based on capacitive transduction. Reasons are simplicity of the sensor element, no requirement for exotic materials, low power consumption and good stability over temperature. But will comb-drive architecture for accelerometers continue to be the main detection principle as MEMS die size keeps shrinking?

Regarding gyroscopes, most are falling into the categories of tuning vibrating fork/plate (STM, Bosch) or vibrating shells (Silicon Sensing Systems). This very common design gives ease of fabrication and possible integration in standard IC manufacturing industry.

For magnetometers, Hall Effect has been the dominant technology for a long time, but today it is changing as Magneto Impedance, Giant Magneto Resistance and Anisotropic Magneto Resistance are used. A new approach, Lorentz effect based on MEMS technology, is currently in R&D (VTT and others). This could bring easier integration in MEMS combo sensors.

"Testing has been also subject to strong evolution over the last years," said Dr. Eric Mounier, senior analyst, MEMS Devices & Technologies at Yole Développement. For example, combo sensors will require new test solutions compared to “stand-alone” sensors. Beyond the usual wafer-level electrical test and package-level electrical and mechanical or functional testing, these sensor combos will need module level testing and calibration of the combined sensors. If they include an MCU in the package, the communication between the sensors and the MCU will also need to be tested. Solutions need to be cost effective with high throughput to test multiple axes of multiple devices, either in parallel or in separate modules, rather like separate chambers in IC equipment.

The world of MEMS testing has moved in the last several years from internal development at MEMS makers to co-development with test suppliers to commercial off the-shelf equipment. So combo solutions that can test all axes of the module in a single tool for higher throughput will also likely be co-developed with the test equipment suppliers and available commercially. Assembly and test houses may also start to offer these test services on an outsource basis for fabless or fab-light MEMS makers. The Yole Développement report will analyze the latest trends in MEMS testing.

In order to understand the key evolutionary changes, a total of 23 different MEMS devices (9 accelerometers, 10 gyros, 3 combos and 1 magnetometer) — mostly consumer MEMS — have been disassembled, analyzed and cost simulations have been constructed for MEMS, ASIC and Packaging/Test. One of the key features of the reports is that ASICs have been analyzed as well. The MEMS have been analyzed and production costs have been simulated by System Plus Consulting, the reverse costing specialist company. The teardown analysis results have been compared in terms of performance, total cost, MEMS size, ASIC lithography node, ASIC size, package size, year for market introduction.

From its analysis, Yole Développement found there is a clear MEMS die size decrease over 2007-2011. For example, in 2008, the average size for an accelerometer (3-axis) was 4-5mm². 3 years later, size is about 2mm². ASIC size has been following the same trend with a lithography node in the range 0.18-0.35μ today. "With latest ST announcement about the use of through silicon vias for inertial, we can expect even lower cost and size in the future," said Robin. The same analysis has been performed for gyros comps, combos and magnetometers.

Companies cited in the report:
Accutronic, Advanced Microsensors, Advantest, Afore, Aichi, AIS/SSS, AKM, Analog Devices, ASE, Baolab, Bosch Sensortec, CascadeMicrotech, CEA Leti, Colibrys, Epson Toyocom, Freescale, Gladiator Technologies, Honeywell, Invensense, Jyve, Kionix, KYEC, Litef, Memsic, Multitest, Murata, Panasonic, Polytec, Qualtre, Rohm, Sensonor, Sensordynamics, Sony, SPEA, SSS, STM, Systron Donner,TEL, Teradyne, Thales, Tronics, VTI, VTT, Yamaha

Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. He previously worked atCEA LETI R&D lab in Grenoble, France in Marketing dept. Since 1998 he is a co-founder of Yole Developpement, a market research company based in France. At Yole Developpement, Dr. Eric Mounier is in charge of market analysis for MEMS, equipment & material. He is Chief Editor of Micronews, and MEMS’Trends magazines (Magazine on MEMS Technologies & Markets).

Laurent Robin is in charge of the Inertial MEMS & Sensors market research at Yole Developpement. He previously worked at image sensor company e2v Technologies (Grenoble, France) and at EM Microelectronics (Switzerland). He holds a Physics Engineering degree from the National Institute of Applied Sciences in Toulouse. He was also granted a Master Degree in Technology & Innovation Management from EM Lyon Business School, France.

Yole Développement provides market research, technology analysis, strategy consulting, media in addition to finance services. Access the report catalog at www.yole.fr.

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December 21, 2011 – BUSINESS WIRE — The global power semiconductor market will grow 5.0% in 2012 to $32 billion, says IMS Research. The modest increase is due to global economic uncertainties and inventory being flushed from the supply chain. 2013 will see a return to double-digit growth.

The power semiconductor market includes power discretes, power modules and power ICs.

IMS Research

December 20, 2011 — Cu metallization is now widely used in both logic and memory devices. With the adoption of Cu metallization, metal barriers such as TaN are needed to enhance the adhesion of metal to the dielectric and prevent the diffusion of Cu through the dielectric. As the feature size continues to shrink, barrier thickness must be scaled to enable void-free Cu fill and allow the maximum volume of Cu in the feature to reduce resistance. Conformal TaN deposition can enable the reduction of metal barrier thickness while providing a continuous metal barrier film. PVD has been the mainstream technique for TaN deposition, but as feature size scales down, achieving good step coverage becomes more of a challenge.

ALD TaN has attracted much attention due to its capability to produce a conformal film with precise thickness control and high film density. In this study, we investigated the film characteristics and process integration of TaN produced using iALD. High-density TaN with low resistivity and excellent conformality is demonstrated with this process. Robust VSM, EM, and dielectric reliability are observed when iALD TaN is integrated into dual damascene interconnects.

Experimental

All iALD TaN process development work was conducted on an iALD chamber that was attached to a INOVA platform. The system also included a Remote Plasma Module (RPM) for reducing CuOx and cleaning etch residue prior to TaN deposition while minimizing the damage to ULK, as well as PVD Ta (IONX2) and Cu (IONFLO) modules. This configuration allowed all process steps to be performed without a vacuum break.

Dual damascene structures with 65nm technology node dimensions were used to investigate the electrical and reliability performance of the iALD TaN film. Low-k SiOC dielectric with k=3.0 was used as the main dielectric. A thin PVD barrier/seed process optimized for 45nm technology node was used as the reference control [1]. The test split included 10