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June 25, 2012 — Barclays Capital checks in on the extreme ultraviolet lithography (EUV, EUVL) market potential and which semiconductor manufacturers will press adoption. The analysts also update their expectations for lithography tool suppliers on the EUV front.

Deep ultraviolet (DUV) lithography is reaching its limits in enabling cost-effective linewidth shrinks on semiconductor wafers. An increasing number of chip layers are resorting to multiple lithography/deposition/etch steps per layer. While the cost tradeoff of multiple patterning over EUVL is still a consideration for chipmakers, the number of litho masks required will continue to ramp for DRAM, NAND, and logic if EUV is not adopted.

Barclays expects DRAM to be the first EUV litho adopter, with the foundry sector following close behind, thanks to layer requirements for each. Intel is unlikely to be an early adopter; look instead to Samsung and TSMC. The EUVL adoption curve should materialize, Barclays says, assuming lithography tool supplier ASML is able to reach ~30-40 wafers per hour (WPH) throughput at a ~75-80% duty cycle on its EUV tool by the end of 2012, ~70WPH by Q1 2014, and ~125WPH by Q2 2015.

The biggest bottleneck to EUV readiness remains delays in EUV light source power output, reliability, and cleanliness. Of the 3 light source manufacturers, Cymer is the furthest ahead in terms of ramping power, throughput, and light source reliability; deploying light sources to chipmakers; and design-in wins (all of ASML’s 11 NXE 3300 tools on order currently use Cymer sources), Barclays reports. Lithography watchers will continue to focus on whether Cymer will meet its milestones, and whether Ushio will be able to catch up in 2013.

2012 is the year for meaningful breakthroughs in EUV lithography, but true EUV ramp will come in the 2014/2015 timeframe. This should coincide with DRAM transitioning to ~20nm and foundries to 14nm, reports Barclays. The analysts map out ~18 EUV tools to foundries, ~8 to DRAM, ~4 to Intel, and none to NAND (though ramping in 2016), for total 2015 shipments of 30-36 EUV tools.

Beyond 2015, further tool penetration and new income from service and parts will benefit Cymer in particular, as well as ASML.

Access Barclays Capital’s full report at http://live.barcap.com/PRC/servlets/dv.search?contentPubID=FC1833189&bcllink=decode

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June 25, 2012 — Solid State Technology will present 3D and 2.5D Integration: A Status Report on June 27, free for all attendees. William Chen, ASE, will join speakers David McCann, GLOBALFOUNDRIES and E. Jan Vardaman, TechSearch International. The webcast is sponsored by EV Group (EVG) and ALLVIA.

3D and 2.5D Integration: A Status Report will cover through-silicon via (TSV) formation, interposers, and other die stacking methods. What is the present status of these advanced packaging technologies?

Now, William Chen, senior technical advisor, Advanced Semiconductor Engineering Inc. (ASE US Inc.), had been added to the speaker list for this webcast. ASE is a leading semiconductor assembly and test services (SATS) provider, headquartered in Taiwan. William Chen recently spoke at The ConFab 2012, where he discussed the rise of

June 22, 2012 — SEMICON West is taking place July 10-12 at the Moscone Center in San Francisco, CA. Following are new products for semiconductor packaging and test that will be at the show, from wafer bonders to LED die attach materials.

Automated temporary bonding/debonding system

The EVG850 TB/DB XT Frame from EV Group is an automated temporary bonding and debonding system for thin wafer handling, configured to address high-volume 3D IC and TSV manufacturing. The system temporarily bonds a device wafer to a rigid carrier wafer for safe and efficient processing of the device wafer. After subsequent processing (back thinning, lithography, metallization, etching, through via processing, etc.), the device wafer is debonded from the carrier substrate using various techniques dependent of the intermediate material. The system can be configured for LowTemp debonding methods like ZoneBOND technology with the required EZR (Edge Zone Release) and EZD (Edge Zone Debond) modules. A thermal-activated, mechanical slide-off is utilized for thermo-plast materials, while UV-exposure and lift-off debond is utilized for UV-activated tapes. It accommodates up to 9 process modules and boasts a continuous-mode operation with an ultra-fast handling system, up to 4 FOUP load ports, a material buffer in the form of a local FOUP storage system holding up to 10 additional FOUPs, and in-line metrology module option. EV Group, South Hall, Booth 719.

Electrochemical deposition tool

TEL NEXX’s new plating tool, Stratus Thunder, is used for electrochemical deposition of TSV, middle and interposer, lead-free, copper pillar, and RDL advanced packaging materials. Stratus Thunder features a low-cost vertical plating architecture and additional features improve its productivity by up to 50%. TEL, South Hall, Booth 1531.

Spray coater

The MAX-800 is a large format, high speed X-Y-Z spray coating system designed for the thin, uniform application of a variety of coatings and suspensions used in semiconductor packaging, display manufacturing, fuel cell manufacturing and medical device manufacturing applications.  The system features USI

June 22, 2012 — North-America-based manufacturers of semiconductor fab equipment posted $1.61 billion in orders worldwide in May 2012, $1.54 billion in billings, and a 1.05 book-to-bill ratio, shows SEMI. 

The three-month average of worldwide bookings in May 2012, $1.61 billion, crept 0.6% above the final April 2012 level of $1.60 billion. May 2012 saw <1% decline year-over-year, down 0.7% from May 2011’s $1.62 billion in orders.

The three-month average of worldwide billings in May 2012, $1.54 billion, grew 5.3% over the final April 2012 level of $1.46 billion. May 2012 billings fell 8.0% from May 2011’s billings of $1.67 billion.

Chipmakers are adding capacity and process technologies to meet demand for chips in mobile applications — namely smart phones and tablets, said Denny McGuirk, president and CEO at SEMI. "Bookings a re at the highest levels since May 2011 and this is the fourth consecutive month that new orders have outpaced billings."

Table. The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings (3-mo. avg)

Bookings (3-mo.

avg)

Book-to-bill ratio

 

 

 

 

Dec 2011

1,300.0

1,102.9

0.85

Jan 2012

1,239.9

1,187.5

0.96

Feb 2012

1,322.8

1,336.9

1.01

March 2012

1,287.6

1,445.7

1.12

April 2012 (final)

1,458.7

1,602.8

1.10

May 2012 (prelim)

1,536.0

1,611.9

1.05

Source: SEMI June 2012

A book-to-bill of 1.05 means that $105 worth of orders were received for every $100 of product billed for the month.

Also read: Semiconductor fab tool makers see sequential increase in Q1

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS).

SEMI is a global industry association serving the nano- and micro-electronic manufacturing supply chains. For more information, visit www.semi.org.

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June 22, 2012 — A multidisciplinary research team at Massachusetts Institute of Technology (MIT) and the Universidad Autónoma de Madrid in Spain developed a new mathematical approach to simulating the electronic behavior of noncrystalline materials, with applications in organic light-emitting diodes (OLEDs), flexible printable organic (FPO) electronic circuits, and solar cells.

This mathematical technique, free convolution (a form of free probability applied to random matrices), has not previously been applied in physics or chemistry. It uses approximations rather than exact solutions, yet the resulting predictions match the actual electronic properties of noncrystalline materials with great precision.

The method takes a matrix problem that is too complex to solve easily by traditional mathematical methods and “approximates it with a combination of two matrices whose properties can be calculated easily,” without the complex calculations that would be required to solve the original problem, explained Jiahao Chen, a postdoc in MIT’s Department of Chemistry.

Simulating materials that lack an orderly crystal structure with random-matrix theory allows researchers to couple disorder in a material with its effect on electrical properties, Chen said. Typically, figuring out the electronic properties of materials from first principles requires calculating certain properties of matrices. The numbers in the matrix represent the energies of electrons and the interactions between electrons, which arise from the way molecules are arranged in the material.
To determine how physical changes, such as shifting temperatures or adding impurities, will affect such materials would normally require varying each number in the matrix, and then calculating how this changes the properties of the matrix. With disordered materials, where the values of the numbers in the matrix are not precisely known, this is a very difficult mathematical problem to solve.

Random-matrix theory’s probability distribution makes it possible to translate basic information about the amount of disorder in the molecular structure of a material into a prediction of its electrical properties.

While mathematicians have used such methods in the abstract, “to our knowledge, this is the first application of this theory to chemistry,” Chen says. The team also investigated why free convolution was so accurate, which led to new mathematical discoveries in free probability theory. The method derived for estimating the amount of deviation between the precise calculation and the approximation is new, Chen says, “driven by our questions” for the mathematicians on the team.

“Our results are a promising first step toward highly accurate solutions of much more sophisticated models,” Chen says. Ultimately, an extension of such methods could lead to “reducing the overall cost of computational modeling of next-generation solar materials and devices. There is a lot of interest in how organic semiconductors can be used to make solar cells” as a possible lower-cost alternative to silicon solar cells, Chen says. In some types of these devices, “all the molecules, instead of being perfectly ordered, are all jumbled up.”

The research is reported in the journal Physical Review Letters, to be published June 29.

The team included Chen, MIT associate professor of chemistry Troy Van Voorhis, chemistry graduate students Eric Hontz and Matthew Welborn and postdoc Jeremy Moix, MIT mathematics professor Alan Edelman and graduate student Ramis Movassagh, and computer scientist Alberto Suárez of the Universidad Autónoma de Madrid.

The work was funded by a grant from the National Science Foundation aimed specifically at fostering interdisciplinary research.

Courtesy of David Chandler, MIT News Office. Learn more at www.mit.edu.

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June 21, 2012 — To support the next cycle of LED manufacturing, tools such as MOCVD, plasma etch, lithography, and others must undergo cost efficiency and yield improvements, says Yole Développement. Trends include migrating to larger wafers, silicon substrates, and tools developed specifically for LED fab, rather than retooled from semiconductor manufacturing specs.

The light-emitting diode (LED) market experienced an unprecedented investment cycle in 2010-2011, according to Yole Développement. The LED chip cycle was driven by demand in liquid crystal display (LCD) backlights, anticipation of a general lighting market boom, and generous stimulus subsidies from the Chinese central and local governments. The resulting overcapacity situation will take 12-18 month to absorb.

The next investment cycle, driven by lighting applications, will start in 2013. Expect a more limited cycle due to improvements in fab equipment throughput and yields. To enable massive adoption in general lighting applications, significant technology and manufacturing efficiency improvements are still needed to reduce the cost per lumen of packaged LED.

Figure. LED front end equipment market revenue (MOCVD, lithography, dry etch, PECVD, PVD). SOURCE: Yole June 2012.

LED manufacturing equipment trends

Front-end LED manufacturing typically represents about 50% of the total cost of a packaged LED. LED structures and materials are undergoing performance, manufacturability, and cost improvements.

The metal-organic chemical vapor deposition (MOCVD) equipment market represents a $4.3 billion opportunity in the 2012-2017 period. MOCVD represents the single largest opportunity for front-end cost reduction in LEDs.

Additional equipment — lithography, plasma etch, plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) tools — together represent a $650 million opportunity and will essentially follow a similar trend, with some exceptions. The emergence of LED-dedicated tools has already contributed significantly to cost reduction in lithography, plasma, and PVD processing.

The market for dry etching tools is still growing in 2012 due to increasing adoption for patterned sapphire substrates (PSS).

Most lithography tools will see decreased market as LED makers transition to larger-diameter wafers. The number of wafer starts will see a moderate increase initially but start decreasing in 2015, said Eric Virey, senior analyst, LED, at Yole Développement.

PVD equipment will also experience moderate growth during the next investment cycle.

E-beam evaporators have turned into commodities, with systems available from dozens of vendors at very low cost. But opportunities exist in promoting sputtering for indium tin oxide (ITO) deposition, and sputtering could also gain some traction in metal deposition if the industry adopts large-diameter wafers and moves from batch to single-wafer processing. Sputtering equipment could then offer improved cost of ownership.

Learning from the semiconductor industry

With close to 100 companies involved in front-end LED manufacturing, the industry is too fragmented to generate significant economies of scale. Yole predicts massive consolidation within 3 years (2012-2015), which should speed up process and tools standardization and allow better economy of scale.

LED manufacturing still uses methods that would be considered outdated in most semiconductor industries. Consolidation and emergence of LED “giants” will also facilitate and speed up adoption of manufacturing paradigms coming from the IC industry.

Adoption of silicon substrates for LED manufacturing rapidly move LED epiwafer processing into existing, highly automated and fully depreciated CMOS fabs. This would also give LED makers access to extended “process toolboxes,” which could pave the way for entirely new LED architectures.

Traditional large semiconductor equipment suppliers are mostly absent from the LED manufacturing equipment markets. For MOCVD, the tools are very different than the epitaxy tools used in mainstream semiconductor manufacturing. Designing and building such equipment requires significant and unique expertise that Aixtron, Veeco and Taiyo Nippon Sanso, the leading companies in the sector, have acquired through almost 2 decades.

Other front-end LED manufacturing tools are similar in essence to those used in mainstream semiconductor fabs. However, they often require a full redesign to deliver optimum performance and cost of ownership for LED makers. Smaller companies eager to capture opportunity in this niche market are now offering LED-dedicated tools with cost of ownership (COO) payoffs.

Yole Développement’s new report, “LED Front-End Manufacturing,” is dedicated to the LED manufacturing technology & equipment market, including MOCVD, lithography, dry etching, PECVD and PVD tools.

Companies cited in the report:

ACC Silicon, Accretech, Advanced Dicing Technology, Advanced System Technology (AST), Advatool Semiconductor, Aixtron, ALSI, Altatech (Soitec), AM Technology, AMEC, And Corporation, Applied Materials, APT, Arima, ASM Pacific Technology, ASML, Astri, Aurotek, Autec, Azzurro, Bayer, Beijing Yuji, Bergquist, Bridgelux, Bruker, Canon, Cascade Microtech, China Electronics Technology Group Corporation (CETC), Chroma, Corial, Cree, Crystal Applied Technology (SAS), Crystal Optech, Crystalwise, Dai Nippon Kaken (DNK), Dai Nippon Screen Mfg, Daitron, Delphi Laser, Denka, Disco, Dow Corning, Dow Electronic Materials, Dynatex, Edison Opto, Epiluxy, Epistar, Eplustek, ESI, Eulitha, EV Group (EVG), Evatec, Everlight Electronics, Fittech, Formosa Epitaxy (Forepi), Four N4, Fraunhofer IZM, FSE Corporation (Fulintec), Galaxia, GE, GloAB, Hans Laser, Hansol Technics, Hauman, Heliodel, Hitachi Cable, Huga, Hybond, Iljin Display, IMEC, Intematix, InVacuo, Ismeca, JCT, JPSA, JT Corp, Jusung Engineering, K&S, KLA Tencor, Lattice Power, Laurier, Laytech, LG Innotek, Lightscape, Lightwave Photonic, Litec, Loomis, Luminus Devices, LWB, Maxis Co, Merk/Litec, Mitsubishi, Mitsuboshi Diamond Industrial, Molecular Imprint, Momentive, Monocrystal, MPI, Nanoco, Nanometrics, Nanosys, Nichia, Nihon Gartner, Nikon, NN Crystal, North Microelectronics, Novellus, NTT, Nusil, Obducat, Oerlikon Systems, OP System, Optest, Opto Supply Ltd, Orbotech, Osram, Oxfrod Instrument Plasma Technology, Palomar Technology, Panasonic, Philips Lumileds, Phosphortech, Plasma-Therm, Procrystal, Proway, Puji Optical, QD Vision, QMC, Quatek, Rigidtek, Rose Street Lab, Rubicon, Rudolph, Samco, Samsung, Sanken, Semileds, Seoul Semiconductors, Sharp, Shibuya, Sino American Silicon (SAS), Sino Kristals Optoelectronics, Sino Nitride, Sky Technology, SNTEK, SPTS, Stararc, Sumitomo Chemical, Suss Microtech, Synova, Tainics, Taiyo Nippon Senso, Tamarack, Tecdia, Technology & Science Enabler (TSE), Tekcore, Temescal, TeraXtal, Toyoda Gosei, Transluscent, TSMC, Ultratech, Ulvac, Uni Via Technology, Ushio, Varian, Veeco, Verticle, Wacker, Waferworks, Wellypower, Wentworth Laboratories, Withlight, YCChem, Ying Lyu, Zeon Chemical.

Dr Eric Virey, holds a Ph.D in Optoelectronics from the National Polytechnic Institute of Grenoble. In the last 12 years, he’s held various R&D, engineering, manufacturing and marketing position with Saint-Gobain Crystals.

Tom Pearsall started the European Photonics Industry Consortium (EPIC). Before EPIC, he works among others for Bell Laboratories, Thomson/CSF and Corning. He is a Fellow of the American Physical Society, EPIC, and the IEEE.

Yole Développement provides market research, technology analysis, strategy consulting, media, and finance services. For more information, visit www.yole.fr.

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In a webcast scheduled for June 27th at 1:00 Eastern, 11:00 Pacific, David McCann of GLOBALFOUNDRIES will provide a status report on advanced packaging and 3D integration. McCann is responsible for Packaging R&D and back-end strategy and implementation at GLOBALFOUNDRIES. He will address what has recently changed, technology challenges, technology solutions, the “new” supply chain, and design for yield. He will describe the increasingly important role that foundries have played as the industry has evolved from wire bond and flip chip connections to Pb-free bumping and wafer level packaging and now to through silicon vias and interposers.

 “Previously, companies in incremental steps of the supply chain could develop products relatively independently,” he notes. “Now they must work together to create solutions, or fail their common customers.  Although the shortest path to market may be for the foundry to do everything in-house, the path to the best solutions that will enable competitive costs and high volume adaption will be flexible supply chains with collaborative partnering, flexibility, and transparency.”

Prior to GLOBALFOUNDRIES, David worked at Amkor Technology for 11 years, most recently leading the BGA, Flip Chip and MEMS product groups.  He was responsible for extensions of package technology, bump, applications, and business performance.  Prior to this, Dave was responsible for the fcBGA and fcCSP business group at Amkor.  He led cross-functional teams in various areas including networking product strategy, mobile product development, large die/lead free flip chip development, and wafer level product strategy.  David worked closely with Amkor factories in Asia.

Prior to Amkor, David worked at Biotronik, GmbH in Portland, OR.  Biotronik is a developer and manufacturer of implanted medical devices including defibrillators and pacemakers.  David worked at Biotronik for 9 years and had various roles in Production, Process Engineering, Product Engineering, and Flip Chip implementation.  His last role at Biotronik was leading the assembly, interconnect, and product transition from wire bond to flip chip.

David has supported the Electronic Component and Technology Conference for more than 10 years.  This year he is Conference General Chair.

Read McCann’s comments on ECTC is our report, ECTC: Focus on 3D integration and TSVs.

Register now for the free webcast: 3D and 2.5D Integration: A Status Report.

Driven by the volume consumer business, the maturing MEMS sector starts to look at ways to reduce costs and speed time to market by coming together on things like easing integration, common test methods, and tool replacement parts. Fast-moving high-volume markets may also drive MEMS makers toward paring down the vast diversity of  processes and packages used, and into more collaboration on a mature ecosystem.

June 19, 2012 — The micro electro mechanical systems (MEMS) sector is poised for a multiyear period of steady double digit growth, with 20% average annual increases in unit demand, as systems makers find ever more uses for low cost, easy-to-integrate silicon sensors and actuators, reports Jean Christophe Eloy, founder and CEO of Yole Développement.  That means that even with steady price declines, the MEMS market will double, to reach $21 billion by 2017.  Volume consumer markets are driving much of this growth, as consumer applications accounted for more than 50% of total MEMS industry revenue in 2011.  “But growth will depend in part on how well MEMS makers manage to make these devices easier to use,” he notes. “A strong collective push will be needed to create a MEMS ecosystem to simplify the integration of MEMS into larger modules and systems, enabling non-specialists to use them without a steep learning curve.”

Measuring the same things in the same way

In another sign of the growing maturity of the MEMS industry, there’s been some real progress on agreement on measuring the same things in the same ways, to be able to compare results and agree on dimensional and property specifications. 

The US National Institute of Standards and Technology (NIST) is working with the MEMS community towards standard measurement methods for eight key parameters, to allow validation of in-house measurements, and enable meaningful comparisons of parameters measured by different tools, different labs, or different companies, to ease characterizing and trouble-shooting processes, calibrating instruments, and communicating among partners.

NIST will start to offer MEMS test chips with cantilevers, fixed-fixed beams, and structures for measuring step height, in-plane length and thickness, with reference data for parameters such as Young’s modulus, residual strain, strain gradient, step height and in-plane length and thickness measured on these structures by NIST, using SEMI and ASTM standard test methods, the consensus best practices developed by industry committees at these organizations.  Companies can then validate their own measurements on these chips against those made by NIST, supported by a user guide, the data analysis sheets for each measurement, a MEMS parameter calculator and additional information accessible online via the NIST Data Gateway (http://srdata.nist.gov/gateway/) with the keyword “MEMS Calculator”. 

At least one inspection and metrology equipment supplier is considering supplying the test chips and including software to automate running of the standard tests with its tools.

“We want to work with the MEMS community to facilitate widespread adoption and consistent usage of these standard test methods, and to make the reference materials available to as many people as possible,” says Janet Cassard, electronics engineer in NIST’s Semiconductor and Dimensional Metrology Division, who will explain these tools at the MEMS session at SEMICON West. “Developing the best practices and reference materials are typically prohibitively expensive for a single company to invest in on its own.”

The reference materials measure Young’s modulus, residual stress and stress gradient using the method in SEMI MS4, step height and thickness with SEMI MS2, residual strain with ASTM E 2245, strain gradient with ASTM E 2246, and in-plane length with ASTM E 2244. One test chip covers  material and dimensional properties for a composite oxide layer fabricated in a multi-user 1.5 µm CMOS process followed by a bulk-micromachining etch.  The other uses a polysilicon layer fabricated in a polysilicon multi-user surface-micromachining MEMS process with a backside etch. 

Maturing industry may move towards more commonality

Consumer markets, with their fast product iterations and price pressures, may be driving MEMS makers towards more common platforms and consistent package families to speed time to market and reduce costs.  “The high cost of packaging and test is a big challenge for the industry,” notes Micralyne director of strategic technology Peter Hrudey. “So we, as a MEMS community, should be starting the discussion about ways to increase commonality.”  He suggests the best near term possibility could be cooperative co-funding of research for base technology for emerging market needs. Could something like the model employed for the ARM common platform, licensed at reasonable rates for wide use and then further individually enhanced by users be a model for MEMS?   Or perhaps a combination of equipment makers and product designers can drive a move toward process commonality.  As product designers better understand the process characteristics they can design for manufacture more effectively, while the equipment manufacturers may tend toward increasing commonality through a desire to meet the needs of the biggest MEMS manufacturers.  “In a maturing industry the base technology becomes more common. No one player can drive the entire market forward on their own,” he notes.

Keeping legacy tools up and running by identifying common needs

Volume manufacture also means the MEMS industry will need start to think more about keeping its legacy equipment up and running.  While most parts can be relatively easily replaced with something similar, replacing the obsolete printed circuit boards that fail is more of a problem, especially for the more complex boards in 200mm tools that can no longer be fixed in house.  “The aftermarket of scavenged boards of unknown quality, unknown software version, and unknown availability is not a functional supply chain,” says SEMATECH ISMI obsolescent equipment program manager Bill Ross. “Plus chopping it up for parts takes a 200mm tool out of the available inventory forever.”

To help keep the 200mm tool base viable for the wider semiconductor industry, ISMI aims to facilitate the re-manufacture of critical boards, by identifying the key parts needs, then bringing together the original tool makers who have the IP but no longer support the parts, and potential re-manufacturers who could then make the needed quantities of the boards, if they had license to the IP and a market of potential users.  The organization is also setting up an online exchange for its members to speed the search for needed legacy parts.  Ross and others will be discussing this and other legacy tool issues in the Secondary Market session Wednesday afternoon, July 11 at SEMICON West.

These speakers from Yole, NIST and Micralyne join those from Hanking Electronics, IDT, Teledyne DALSA, Coventor, Applied Materials, Nikon and Scannano to talk about solutions for growing the MEMS sector to the next level at SEMICON West, July 10-12 in San Francisco. See http://semiconwest.org/Segments/MEMS for the complete agenda, and http://semiconwest.org/Participate/RegisterNow to register.

More on SEMICON West:

SEMICON West 2012 exhibits preview: Wafer processing and handling

SEMICON West preview: Conference keynotes and "Extreme Electronics"

Visit the MEMS Channel of Solid State Technology, and subscribe to our MEMS Direct e-newsletter!

June 18, 2012 — Following are some of the new and flagship wafer fab products and supporting facility products, like vacuum valves, that will be on the show floor at SEMICON West, from ion implant to MOCVD traps and gas blenders.

High-current ion implant

The Applied Varian VIISta Trident single-wafer, high-current ion implant system embeds dopant atoms on 20nm wafers at high yields. The VIISta Trident precisely tailors dopant concentration and depth profile to optimizing dopant activation and suppress defects in the extension, source/drain junction and contact regions at 20nm. The tool has a proprietary dual-magnet ribbon beam architecture for enhanced performance at low energy. The system’s Energy Purity Module virtually eliminates high-energy species that can "smear" the transistor channel. Integrated cryogenic technology enables production implants as low as -100°C. Applied Materials Inc., South Hall, Booths 407, 552, 847, 1135, 2051, 2219.

 

Ion beam system

MicroSystems’ new IonSys 800 precision ion beam tool provides structuring and finishing processes down to a sub-nanometer scale. It features proprietary ion beam sources and is fully compatible with reactive ion beam processing based on fluorine and chlorine gas chemistry. The IonSys 800 system suits industrial ion beam etching and deposition processes with high quality and productivity requirements. Its automatic handling robot features a cassette load-look and can be configured in cluster layouts. MicroSystems, South Hall, Booth 1924.

 

Fluid dispenser

GPD Global will give live demonstrations of the new Island 3S benchtop manufacturing solution for LED manufacturing. The dispense system features a large work area of 12" x 16", an easy-to-use touchscreen interface and will be configured with a PCD dispense pump. GPD will have a display of dispense pumps to cover a wide range of dispensing applications. The Hyflow dispense pump suits heavy fluids such as thermal grease, the MicroDot valve will be on display for precision small volume dispensing such as conductive adhesives and solder pastes. Additionally, the Syringe mixing system format enables homogeneity of fluids such as silicone with phosphor. GPD Global, North Hall, Booth 6085.

 

MOCVD trap

Nor-Cal Products provides MOCVD device manufacturers increased up time with their new three-stage trap. Features include a removable water coil assembly and particle filter with 50% greater capacity. The trap proffers lower initial cost, lower cost of ownership, high capacity for extended PM, and ease of cleaning in GaN MOCVD reactors; AsP MOCVD reactors; and Aixtron G3, G4 and G5 systems. Nor-Cal Products, South Hall, Booth 2441.

Manual wafer handling tool

Virtual Industries Inc.’s new WV-9000 WAFER-VAC System handles wafers and solar cells without requiring in-house air plumbing. The compact, general-purpose wafer vacuum handling tool plugs directly into 110 Volt 50/60 Hz, and is ESD safe and Class-100 cleanroom compatible. Its diaphragm vacuum pump generates up to 10” of mercury with an open air flow of 2.3 lpm. The WV-9000 comes with a push-button wafer tip pen VWP-500-2.5mm, and a 6 foot clear coiled vacuum hose (VCH-2.5mm-6). Virtual Industries, South Hall, Booth 2427.

 

Aluminum transfer valves

HVA’s new high-performance aluminum slit valve range offer a slim profile and low vibration/particle levels, with reportedly light weight and high strength. Each valve component meets the throughput requirements of coating systems with up to 3 million cycles before maintenance. The valves are available in a range of sizes up to 2000mm as well as standard MESC 200/300/450mm sizes. HVA, South Hall, Booth 2625.

 

Gas blending system

Blixer from SEMI-GAS Systems is a custom gas blender that provides a continuous flow of precisely blended gases. It can blend two component-forming gas mixtures or mix three, four or more gas components into uniform, controlled mixtures. Blixer gas blenders meet application-specific requirements for flow, pressure, mixture percentage and blending accuracy. The gas mixture percentages can be adjusted by the operator during use via the onboard touchscreen interface. Blixer can support fluctuating usage and variable flow rates from multiple points, each with independent duty cycles. It uses mass flow controllers and offers an optional gas analyzer. Blending routines are completely automated. Blixer continuously monitors system performance and safety conditions with auto shutdown or notifications on alarms. SEMI-GAS Systems, a division of Applied Energy Systems Inc., South Hall, Booth 810.

Integrated vertical and rotation stage

Newport Corporation’s ZVR specialized Integrated Vertical and Rotation Stage, the ZVR-PP with a stepper motor or the ZVR-PC with a servo-driven DC motor, is used for semiconductor wafer positioning, metrology, inspection, and repair, it is also useful in LED production and applications such as 3D scanning, digitizing models, and validation. Newport’s ZVR features a compact and rigid design with improved cantilevered load capacity. With significantly lower cross-talk than earlier designs, the new stage delivers higher dynamic system performance in a low-profile footprint. The low mass, along with a high natural frequency, accommodates a variety of rapid step-and-settle positioning applications. The ZVR vertical platform has a wide, 3-point base with a stepper-motor-driven 10mm Z-stage. The integrated stainless steel rotation stage features smooth operation with stainless steel ball bearings. The rotation stages provide continuous 360° rotation for angular travel. An optional linear encoder for the Z-stage, or the Z-stage without the rotation stage, are also available. The three-point bottom interface permits mounting to any XY stage or other platform. A large, clear aperture through the center of the stage simplifies electrical cable and vacuum-chuck cable/hose management. All electrical and vacuum chuck utility connections are located together. Newport Corporation, South Hall, Booth 1507.

Transfer valves for 200-450mm semiconductor wafers and LED wafers

VAT Vakuumventile AG launched a transfer valve designed for semiconductor applications handling 200mm, 300mm and 450mm wafers and HB-LED applications. VAT REAL L-MOTION valves handle corrosive process environments in etch and CVD tools. The actuator has integrated, mechanically triggered sequence control with a fully protected bellows feedthrough. VAT REAL L-MOTION valves allow for easy access gate exchange through the top cover; no adjustment is required after service. Uniform sealing compression is achieved due to Real L-motion movement and an adjustable closing force (depending on elastomer), minimizing particle generation from the seal. The valve is pneumatically operated and locked in closed and open position. VAT offers standard and customized valves. VAT, South Hall, Booth 919.

 

FKM+PTFE seal for vacuums

VICTRA-ER from VALQUA is an advanced “hybrid” FKM+PTFE seal, combining semiconductor-grade FKM (fluoroelastomer) for high-vacuum sealing with a PTFE “liner” for radical resistance. VICTRA-ER suits harsh RF and microwave-based plasma environments, with the vacuum seal maintained by the high-performance FKM material, and plasma radicals resisted by high-purity PTFE that won’t introduce particles or metallic elements into the process. VICTRA-ER withstands operating temperatures up to 200°C. It can be used in semiconductor applications: plasma etching (metal, poly, oxide), CVD (PECVD, HDP-CVD), PVD, plasma ashers/strippers, and other plasma-based IC manufacturing processes. VICTRA-ER seals are available in AS568A-, KF-, and NW-standard sizes or special sizes upon request. VALQUA offers seal designs based on specific groove designs, counterface materials, and location within the chamber (e.g. lid area, wafer chuck, gas injector, showerhead, foreline/exhaust line, etc.). VALQUA, Booth 1430.

Vacuum pumps and abatement systems

Edwards will showcase dry vacuum pumps at SEMICON West that use less energy and need less maintenance than oil-sealed pumps. Edwards’ abatement systems also reduce operating expenses and maintenance requirements while maintaining a minimal environmental footprint, the company says. Edwards will feature the STP-iXR1606 series of magnetically-levitated turbomolecular pumps (TMP), which offer 40% improvement in throughput and an increase of nearly 90% in maximum gas flow, compared to existing products. Also highlighted in the booth are the GXS 450 and 750 series of dry vacuum pumps that meet high-throughput solar lamination process needs. Edwards, Booth 5351.

SiC tool components

Bridgestone is launching high-performance silicon carbide (SiC): PureBeta for peripheral semiconductor processing equipment components. The precision-machined components are made of ultra-high-purity sintered SiC with high thermal conductivity, high electrical conductivity, and durability in chemicals. Products include wafer process components such as wafer-holder plate for SiC-Epi/MOCVD, dummy wafers, disc plates, rings and heater filaments etc. 450mm parts are now available. Bridgestone, South Hall, Booth 447.

Ultra-high-purity gas analyzer

The newest addition to Tiger’s HALO family line, the HALO KA, provides a compact, ultra-high-purity gas analyzer. Its modular construction features ease-of-use with freedom from calibration, consumables, and routine maintenance costs. The laser-based HALO KA offers sensitivity, stability and low detection levels for ultra-high-purity analysis. Various gases can be detected in the most complex matrices, including hydrides, fluorides and corrosive gases. The new ALOHA+ H2O trace moisture analyzer for ultra-high-purity gases offers HB-LEDs manufacturers extreme sensitivity to moisture in ammonia. Tiger Optics, Booth 1201.

Low-cost plasma etching system

Plasma Etch Inc.’s low-cost benchtop plasma cleaning system, the PE-50, for semiconductor and similar applications is now available in an expanded chamber version with high rate etching capabilities, the PE50XL-HF. The PE-50XL-HF uses a new expanded 8" x 8" x 4" aluminum vacuum chamber for accommodating substrates/wafers up to 6" diameter. The system incorporates a 100W 13.56 MHz RF power supply with automatic RF tuning. The PE-50XL-HF also includes 2 gas meters for independent gas flow control or gas mixing introduction into the vacuum chamber. A 5 CFM vacuum pump charged with Krytox oil for Oxygen compatibility is included, with a dry pump optional. Plasma Etch Systems uses PLC control systems for automatic process sequencing. A keypad is used for operator entry and one complete process recipe can be displayed and stored in memory for reliable operation and repeatable results. Applications include photoresist ashing, etching of Si/Oxides/Nitrides and polymer etching. The plasma process also increases surface energy enabling a hydrophilic surface improving bond strength. Plasma Etch Inc., Booth 6566.

 

Springless diaphragm valves

The Swagelok DE series ultra-high-purity springless diaphragm valves features a formed aluminum housing on a 1.125 in. footprint. The valve is designed for modular gas systems. Swagelok eliminated the threads that typically connect the actuator components and attach the actuator to the valve body, allowing larger-diameter pistons in the same standard footprint. The center cylinder of the actuator design provides an additional active piston to increase the force output of the actuator. The formed actuator also reduces the valve height. A smaller body in the design efficiently uses 316L VIM-VAR material. A fully contained seat design minimizes chemical and thermal swelling. Swagelok provides corner chamfers on the outlet side of the body to indicate flow direction (top view) and match actuator orientation for installation. The DE series has a high-integrity all-welded seal to atmosphere. After undergoing SC-01 ultrahigh-purity cleaning, the diaphragm is hermetically sealed in the clean room environment. Stresses are reduced on the welded seal at high flow rates. A proprietary weld isolation ring protects the weld from the cyclic actuation load of the valve.  Available with pneumatic or manual actuators, the DE series can be ordered in two- or three-port configurations. The pneumatic actuator is permanently attached to the body assembly. Normally closed and normally open models have a color-coded indicator button. The manual actuator offers one-quarter turn window handle for quick actuation. The handle orientation to body is fixed for ease of installation. The valve is available in both C-seal and W-seal designs. The W-seal features a specially designed bolt retention ring that rolls down on the cylinder to keep bolts in place during assembly and reassembly. Swagelok, South Hall, Booth 1431.

Upcoming SEMICON West previews: Metrology, inspection and test products, packaging products, lithography tools, and more.

If you want to quickly find and fix the source of a process excursion, you have to be able to capture the right defects, and review and classify them efficiently. Electron-beam review is always the rate-limiting step in this process; thus it’s worth investing effort in improving the odds of identifying defects that are going to lead to discovery of the source of the excursion. Even at the blinding speed of up to12,000 defects per hour (the state of the art for an e-beam review tool), most fabs can’t justify the time to review every defect on every wafer. How do you make sure you’re reviewing the yield killing defects and not wasting time reviewing nuisance events?

On critical layers, optical wafer inspection has to be run very “hot,” that is, with very high sensitivity settings, in order to capture the smallest, lowest-contrast defects that may affect yield. The problem is that hot inspections frequently capture not only defects of interest (DOI), but also nuisance events, such as line-edge roughness or defects on dummy pattern.  Unfortunately, nuisance events tend to strongly dominate the defect count in a hot inspection. When it comes time to review the defects to determine their source, choosing a random, unbiased sample may lead to reviewing a very small number of DOI—perhaps too small to represent the DOI population accurately.  You might not even be lucky enough to sample all DOI defect types, if nuisance defects represent a large fraction of the defects captured. The result is a misleading defect pareto—which can result in a delay in getting a new process to yield, or even a delay in getting a new chip to market.

There are two main approaches to skew the defect pareto away from nuisance events and toward DOI: (1) reduce the percent nuisance capture on the inspection system and (2) identify nuisance events after inspection and remove them from the review sample. A third approach would be to identify nuisance defects during e-beam review, but that strategy would be the least efficient. Nuisance capture on the inspection system can be reduced by selecting an appropriate combination of inspection wavelengths, apertures and polarizations that preferentially captures DOI over nuisance. Having an inspection system that offers the flexibility to manipulate defect type capture can be very effective at reducing nuisance capture during inspection. This sort of approach has been used for many device generations and over many generations of inspection systems for nuisance reduction.

What’s new is the ability to use design information to either skip “nuisance areas” of the die during inspection—or, after inspection, to remove defects residing in nuisance areas from the review sample. The former strategy is called micro-care area inspection; the latter is called design-aware nuisance filtering.

One of our technology-leading customers recently used micro-care area inspection to focus a high sensitivity inspection on patterns comprised of dense, thin lines. An automatic “care area” generator was used to search through the design file of the die, to draw hundreds of thousands of small care areas wherever dense, thin lines occurred (Figure 1). Only these care areas would be inspected. Together the care areas represented less than 5% of the die area normally inspected—but defects occurring in these areas had a high probability of being yield killers. Severely restricting the inspected areas dramatically increased capture of the yield-killing bridge defects and reduced the nuisance defect population to nominal levels.

 

Design-aware nuisance filtering was used to help two prominent foundries reduce nuisance defects on a silicon-germanium (SiGe) layer. SiGe is used in some high K metal gate processes to improve device performance. The problematic nuisance defect on the SiGe layer represented a small change in shape to the edge of the polygon—a variation that had no apparent effect on the device. After the defect team optimized the wavelength/aperture/polarization combination for best capture of DOI, traditional nuisance filtering, based on the attributes of the defect signal during inspection, was able to reduce the nuisance defect count by an order of magnitude. However, nuisance events still dominated the captured defect population, at a rate of 90%. At this point, design-aware nuisance filtering was used to associate the locations of the nuisance defects to a small number of pattern types. When all inspection events associated with these pattern types were eliminated, the DOI contribution to the defect pareto advanced from 10% to 85%.  Two SiGe nuisance areas are indicated in Figure 2 with solid yellow lines.

 

Strategically manipulating the defect sample reviewed by the e-beam review system so that it contains a high percentage of DOI has become necessary to creating a defect pareto that quickly and clearly directs defect engineers to the source of the excursion. Techniques like micro-care area inspection and design-aware nuisance filtering can be valuable tools for skewing the defect pareto toward yield-killing defects. For further information about creating an actionable defect pareto, please see last month’s Process Watch article, “The Dangerous Disappearing Defect.”

Rebecca Howland, Ph.D., is a senior director in the corporate group and Ellis Chang, Ph.D., is Nuisance Czar in the wafer inspection division at KLA-Tencor.

Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”