Tag Archives: Advanced Packaging

April 2, 2012 – PRNewswire — Terepac Corporation, developer of tiny digital electronics, has launched the TereTag miniaturized circuit design that is embedded in items to enable the "Internet of Things."

This tag enables the host object to identify, communicate, and operate with more security and efficiency, interacting with a cell phone for sharing via Twitter, Facebook and Google. The user can access details about the product and share information with friends through social networks, for example.

The design is a combination of miniaturizing electronics, and enabling networking with external electronic devices, said Terepac CEO Ric Asselstine. Terepac’s patent-protected process reportedly creates "unprecedented" miniaturized electronics. The company is producing apps and networking capability and data collection technologies to enable the object to become an app platform, mining, managing, and visualizing data, and sharing via social media.

The low-power, low-cost connectivity of the devices could enable new applications in environmental monitoring, branding, etc. "Every thing today has the potential to be transformed into a smart object," said Asselstine.

Also read: Terepac expands to Silicon Valley

Terepac Corporation has developed a breakthrough semiconductor packaging and assembly method to allow effective handling and packaging of the tiniest imaginable chips, objects and electronic components – at its limit to the nanometer scale. Sophisticated microelectronics can be printed on flexible substrates at a fraction of the size and cost of conventional methods. Entire structures with microprocessors, memory and sensors can be reduced to less than a millimeter square, thinner than paper, and flexible enough to bend around a pencil with no sacrifice in performance. For more information, visit www.terepac.com.

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April 2, 2012 – BUSINESS WIRE — Bruker Corporation (NASDAQ:BRKR) acquired all of the shares of SkyScan N.V., a scientific instruments company serving materials science and life sciences/pre-clinical imaging needs.

SkyScan makes advanced, high-resolution micro computed tomography (micro-CT) systems for 3D X-ray imaging, including 3D imaging of electronic components; synthetic materials, ceramics, and other materials; new devices such as microsensors and fuel cells; and medical and geological applications.

Financial details of the buy were not disclosed, but Bruker expects it to add approximately $13 million in revenue for the remainder of 2012. SkyScan will be renamed Bruker microCT NV, providing CT instruments under the SkyScan brand. It will operate at its Belgium facility under the same management, with founder and CEO Dr. Alexander Sasov taking on the title managing director and CEO. Bruker will invest in additional micro-CT applications and demo centers worldwide.

SkyScan micro-CT 3D X-ray imaging tools will now be sold through Bruker

March 30, 2012 – BUSINESS WIRE — Semiconductor packaging and test services (SATS) provider Amkor Technology Inc. (NASDAQ:AMKR) granted SHINKO ELECTRIC INDUSTRIES CO., LTD. (Tokyo:6967) a non-exclusive license to its proprietary Through Mold Via (TMV) semiconductor packaging technology.

Amkor will transfer its TMV process to SHINKO, which can manufacture packages based on the via technology under Amkor’s patents. SHINKO may also use the registered TMV trademark for sales and marketing activities. Amkor customers will have multiple sources for the TMV packaging service. Last year, Amkor surpassed 100 million units of its TMV products fabricated.

The technology provides SHINKO with a 3D package stacking process for package on package (PoP) components. With TMV, a blind via is created through the mold compound after package molding. This exposes PoP bond pads on the package substrate

March 30, 2012 — Semiconductor fab equipment supplier SUSS MicroTec has acquired Tamarack Scientific Co. Inc. in a share purchase of $9.34 million, plus an additional variable earn-out component which depends on the development of revenues for the next 3 financial years.

Tamarack makes ultraviolet (UV) projection lithography tools and laser micro-structuring systems for manufacturing 3D semiconductor packages, micro electro mechanical systems (MEMS), and light-emitting diodes (LEDs). Laser processing tools include excimer and solid state; photolithography tools include proximity and projection.

Tamarack products are installed from R&D facilities to high-volume manufacturing plants. The company in based in the US, with an applications lab, cleanroom, and short-run manufacturing support in addition to its capital equipment offering.

The acquired intellectual property (IP) complements SUSS’s exposure technology portfolio with projection lithography. The additional core technology and product line for back-end semiconductor lithography gives SUSS a range of price/performance offerings for customers, said Frank P. Averdung, president and CEO of S

March 27, 2012 — Cypress Semiconductor Corp. (Nasdaq:CY) transferred 7 back-end semiconductor package assembly lines from its Philippines facility to Chinese packaging subcontractor Jiangsu Changjiang Electronics Technology Co. (JCET, SSE: 600584).

The production will now take place at JCET’s C3 factory in Jiangyin City, China. The lines were qualified by Cypress’ automotive end-customers. The conventional package assembly line transfer was successful from Cypress’ standpoint and that of its automotive customers, said Shahin Sharifzadeh, EVP, WW Wafer Fabs and Technology and President, China Operations of Cypress.

Cypress delivers high-performance, mixed-signal, programmable semiconductors. Cypress trades on the Nasdaq Global Select Market under the ticker symbol CY. Visit Cypress online at www.cypress.com.

JCET (Jiangsu Changjiang Electronics Technology Co., Ltd.) is a Chinese packaging subcontractor, providing full turnkey packaging assembly and test services with a package portfolio of BGA, flip chip, wafer-level, leadframe IC and discrete packages. JCET is listed on the Shanghai Stock Exchange under the stock ticker of 600584. Please visit www.cj-elec.com for more information.

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March 27, 2012 – PRNewswire — Texas Instruments Incorporated (TI, NASDAQ:TXN) now offers bare die in quantities as low as 10 pieces for initial prototyping, and larger quantities (full waffle trays) for production volumes.

Bare die are an option for customers looking to integrate multiple functions into smaller form factors, designing multi-chip modules (MCM) or systems-in-package (SiPs). Bare die can also improve the weight, reliability, and power dissipation specifications of a chip in space-constrained applications. Target applications include mobile RFID readers, consumer smart cards, and medical, industrial, security and high-reliability electronics.

Bare die packaging is available for specific devices in TI’s Analog, Power Management, DSP, and MCU portfolios. Further releases can be evaluated/requested via TI’s HiRel product group. Bare die select devices are available through TI’s standard distribution partners, or at www.ti.com.  

Also read: Texas Instruments (TI) embedded die package teardown report

Texas Instruments provides semiconductor innovations through chip design, manufacturing, and packaging. Learn more about TI’s bare die portfolio at www.ti.com/baredie-pr.

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March 26, 2012 — Camtek Ltd. (NASDAQ and TASE:CAMT) sold $3.5 million of Falcon inspection tools to a leading global outsourced semiconductor assembly and test (OSAT) provider, for various applications in the backend semiconductor assembly process.

The OSAT installing Falcon tools operates multiple package fabrication facilities throughout the world. Deliveries will take place during the current and next two quarters.

Camtek’s Falcon line of automated wafer inspection systems are used by semiconductor manufacturers, bumping houses, and packaging foundries for defect detection and metrology. Falcon systems were introduced in 2003, and Samsung is among the line’s users. They offer 2D and 3D inspection and metrology capabilities for wafers before or after test, along the bumping process or after dicing. They are designed to handle the special inspection needs of MEMS structures.

Camtek Ltd. provides automated and technologically advanced imaging, image processing, adaptive ion milling (AIM) and digital material deposition (DMD) products for semiconductor, printed circuit board (PCB) and IC substrate industries. Learn more at www.camtek.co.il.

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March 26, 2012 – PRNewswire — Semiconductor design/manufacturing software supplier Synopsys Inc. (Nasdaq:SNPS) is combining several products into a 3D-IC initiative for semiconductor designers moving to stacked-die silicon systems in 3D packaging. The 3D-IC initiative will bring in leading IC design and manufacturing companies to work with Synopsys on a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.

The 3D-IC technology initiative will focus on design requirements of multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Thermal mismatch can lead to silicon deformation and hurt transistor performance. Through-silicon vias (TSV), microbumps and other solder bumps produce a permanent stress in their silicon zone. Synopsys’ Sentaurus Interconnect TCAD tool analyzes these effects and models the TSVs in the die stacks. Semiconductor companies, such as foundries, then use modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.

Synopsys’ EDA offering in the 3D-IC initiative includes DFTMAX design-for-test test automation; DesignWare STAR Memory System IP for integrated memory test, diagnosis and repair; IC Compiler for place-and-route support; StarRC Ultra parasitic extraction support for TSV, microbump, interposer RDL and signal routing metal; HSPICE and CustomSim circuit simulation; PrimeRail IR-drop and EM analysis; IC Validator for DRC for microbumps and TSVs and LVS connectivity checking between stacked die; Galaxy Custom Designer for custom edits to silicon interposer RDL, signal routing and power mesh; and Sentaurus Interconnect thermo-mechanical stress analysis.

The Synopsys 3D-IC solution is available now in beta and is expected to be in production in calendar Q2 of 2012. Synopsys’ 3D-IC solution will be highlighted at the Synopsys User Group (SNUG) Silicon Valley event on March 26-28, 2012.

Synopsys, Inc. (Nasdaq: SNPS) provides electronic design automation (EDA) for semiconductor design, verification and manufacturing. For more information on Synopsys’ 3D-IC solution, please visit: http://www.synopsys.com/3D-IC.

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March 23, 2012 — Research organization imec introduces important changes to its ultrathin chip packaging (UTCP) technology, increasing yields 15-20%. Used to package various chips, the technology now offers yields of up to 90%. Extremely miniaturized chip packages can be fabricated, enabling flexible integration to obtain conformable circuitry.

Target applications include wearable medical devices and other novel uses.