Tag Archives: Advanced Packaging

December 9, 2011 – BUSINESS WIRE — Kulicke & Soffa Industries Inc. (NASDAQ:KLIC or K&S) named Chin Hu Lim to its Board of Directors, also serving on KLIC’s Management Development & Compensation Committee. Lim is the managing partner of Stream Global Venture Catalyst Pte Ltd., a venture fund providing seed funding for start-up companies in the social media and interactive digital media space.

Lim has over 28 years of experience in the information and communication industries.
Previous experience:

  • CEO BT Frontline Pte Ltd., a subsidiary of British Telecom Group.
  • CEO of Frontline Pte Ltd., a Singapore exchange listed company with operations in Asia Pacific, South East Asia, China and India. 
  • Sales, marketing and management positions with Sun Microsystems and Hewlett-Packard.

Lim has served as a council member of the Singapore Infocomm Technology Federation, the IT Standards Committee and the National Infocomm Manpower Council. He was also a board member of the Infocomm Development Authority of Singapore. He is currently a board member for the Changi General Hospital and G-Able (Thailand) Ltd., a leading information technology services company in Thailand.

Lim holds a bachelor of electronics & computer science degree from La Trobe University, Melbourne, Australia and a degree in electrical and electronics engineering from Ngee Ann Polytechnic, Singapore.

MacDonell Roehm, Chairman of the K&S Board of Directors, welcomed Lim, praising his expertise in the information and communication industries, finance and Asian markets.

Kulicke & Soffa (KLIC) designs and manufactures semiconductor and LED assembly equipment. Learn more at www.kns.com.

December 7, 2011 — Arteris Inc., network-on-chip (NoC) interconnect IP company, will incorporate its FlexNoC NoC interconnect IP into an SoC die on silicon interposer test chip with Taiwan Semiconductor Manufacturing Company (TSMC). TSMC recently approved additional spending on advanced packaging tech.

"TSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges," said Suk Lee, director of design infrastructure marketing at TSMC.

Arteris’s FlexNoC NOC interconnect IP is physically implemented as a distributed network of small design elements within a SoC floorplan. FlexNoC addresses bandwidth, latency, and quality of service (QoS) requirements introduced with wide data paths.

Arteris is a TSMC Open Innovation Platform Partner and a participant in TSMC’s Reference Flows 11.0 and 12.0.

Arteris Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. More information can be found at www.arteris.com.

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December 6, 2011 – JCN Newswire — Singapore’s A*STAR Institute of Microelectronics (IME) and 3D IC developer Tezzaron Semiconductor signed a research collaboration agreement to develop and exploit advanced through silicon interposer (TSI) technology.

This includes improving and optimizing silicon interposers and creating standardized process, slows, and process design kits (PDKs). In the near term, the partners will look to develop TSI for MEMS and silicon photonics, based on the 3D IC experience.

Early production devices use IME’s TSI technology with 3D ICs from Tezzaron. The team will fabricate devices in IME’s state-of-the-art 300mm R&D fab.

Once a technology is established, IME will drive the TSI Consortium for further optimization and functional demonstrations, to be launched in early 2012. "To build momentum in customer adoption and technology, IME will launch a TSI Consortium in early 2012, to facilitate greater cooperation between foundry, outsourced semiconductor assembly and test providers (OSATs), equipment vendors and supply chain partners to expedite the integration of the supply chain," commented Professor Dim-Lee Kwong, executive director of IME.

Silicon interposers — often considered a bridge technology to true 3D IC — are a "vital component for heterogeneous system integration," asserts Robert Patti, CTO of Tezzaron.

Also read: 3D IC needed? Making a case for 2.5D with Xilinx FPGA launch

IME and Tezzaron have cooperated on research since 2001. Tezzaron used IME’s copper line technologies wafer stacking development. IME researches TSVs, 3D IC cooling, vertical interconnects and interposers; Tezzaron focuses on designing and building wafer-stacked 3D-ICs in its FaStack process.

Tezzaron Semiconductor specializes in 3D wafer stacking and TSV processes, cutting-edge memory products, and wide-ranging collaborations. Information about Tezzaron is available at http://www.tezzaron.com/.

The Institute of Microelectronics (IME) is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR). For more information, visit IME on the Internet: http://www.ime.a-star.edu.sg or go to A*STAR’s website: www.a-star.edu.sg.

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December 6, 2011 — Tokyo Electron Limited (TEL) launched a suite of 3D packaging tools: the Tactras FAVIAS through silicon via (TSV) deep-silicon etch system; the TELINDY PLUS VDP polyimide film formation production equipment that uses vapor deposition polymerization technology; and the wafer bonder/debonder Synapse Series.

The Tactras FAVIAS deep silicon etch system is designed to improve mask selectivity for steady etching. It raises plasma density, increasing the etch rate from 10 to 15

December 6, 2011 — Tokyo Electron Limited (TEL) has successfully demonstrated dynamicing — device switching/dynamic characteristic (AC) — of a power device at the wafer level, which previous only took place after semiconductor assembly and packaging.

TEL developed the dynamicing technique based on Tokyo Electron’s experience in wafer probe technology. By detecting defects at the wafer-level, TEL’s method ensures that known-good die (KGD) are used in multi-die power devices, which provide higher electrical efficiency and performance than traditional designs.

Until now, only staticing — device static characteristic (DC) — has been performed at the wafer level, TEL reports.

Tokyo Electron Limited (TEL) manufactures semiconductor and FPD production equipment, including plasma and ion etchers, and deposition systems. Learn more at www.tel.com.

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December 6, 2011 – Practitioners, students and other interested parties assembled in Atlanta at the recent Global Interposer Technology workshop (GIT) on the Georgia Tech campus to discuss where the technology stands and where it is going.

Xilinx, the first to reach HVM with their Vitrex-7 2000T FPGA, detailed various aspects of their 2.5D interposer product. Suresh Ramalingam, senior director of advanced package design, announced that their Virtex product, which uses a 21mm

December 5, 2011 – Marketwire — Technic Inc. is entering the last development phase on technologies to reduce gold consumption in electronics packaging and connector applications, a product group it will call "Goldeneye."

Goldeneye comprises equipment, electroplating chemistry, and ancillary process chemistries. Newly developed barrier layers enable improved component performance, while gold replacement technology and post-treatment processes further reduce gold consumption.

Technic expected to release the first Goldeneye products this month, with further releases occurring in early 2012.

"With gold at record valuations, the demand for gold conservation in the electronics industry is intense. With Technic’s Goldeneye Gold Reduction Technology, we are creating an integrated portfolio of technically advanced products that enable low-cost finishes for electronic devices without compromise to the integrity or quality of our customers’ products," summarized Rob Schetty, VP, Technic Advanced Technology Division.

Also read: Analyst says gold price surge helping Cu wire shipments

Technic Inc. supplies specialty chemicals, custom finishing equipment, engineered powders, and analytical control systems to the electronic component, printed circuit board, semiconductor, photovoltaic, industrial finishing and decorative industries. For information, go to www.technic.com.

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December 5, 2011 — SUSS MicroTec, equipment supplier for the semiconductor and related markets, launched the XBS300 temporary bonder for high-volume wafer manufacturing. The Bond Cluster is configured to temporarily bond 200mm and 300mm wafers for 3D integration applications as well as other processes that require thin wafer handling.

Key process steps include adhesive and release layer deposition, temporary bonding and curing and integrated metrology to determine the total thickness variation (TTV). Features include higher throughput and sophisticated process control, according to SUSS MicroTec.

Process configurations can be designed for very-low-force bonds such as the Thin Materials (TMAT) process or the 3M Wafer Support System (WSS), and higher-force thermo-compression bonds as used in the BrewerScience ZoneBOND process. SUSS today announced that ZoneBOND can be performed on its XBC300 wafer bonding platform as well.

The system supports all currently-available temporary bonding adhesives. Additionally, several materials manufacturers are developing new temporary bonding adhesives that are fully compatible with SUSS’ XBS300 equipment platform.

The XBS300 is based on SUSS’s ACS300 Gen2 cluster platform.

The first tool has been delivered to a world-leading IDM with the installation currently in progress.

SUSS MicroTec, listed on TecDAX of Deutsche Boerse AG, provides equipment and process solutions for microstructuring in the semiconductor industry and related markets. For more information, please visit http://www.suss.com.

Also read: Temporary wafer bonding market: More than 10 approaches today and Thin wafers win majority in electronics by 2016

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December 5, 2011 — Brewer Science Inc., materials and processes developer for thin wafer handling, will offer the ZoneBOND process on equipment supplier SUSS MicroTec’s XBC300 and XBS300 wafer bonding platforms, targeted for high volume bonding and debonding of 200/300mm wafers using silicon or glass carriers.

ZoneBOND is designed for total thickness variation control in wafer bonding processes, high-temperature stability, and low-stress wafer de-bonding. Brewer Science supports the ZoneBOND process with materials for carrier preparation, adhesives, removers, as well as small-scale debonding equipment.

Shortly after the ZoneBOND technology was commercialized, equipment supplier EV Group (EVG) launched ZoneBond-capable modules.

Brewer Science makes specialty materials, equipment, and process solutions for applications in semiconductors, advanced packaging/3-D ICs, MEMS, sensors, displays, LEDs, and printed electronics. For more information, please visit http://www.brewerscience.com/products/temporary-bonding-materials/zonebond

SUSS MicroTec (listed on TecDAX of Deutsche Boerse AG) provides equipment and process solutions for microstructuring in the semiconductor industry and related markets. For more information, please visit www.suss.com.

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December 2, 2011 — Using the advanced through-silicon via (TSV) fabrication process at IBM (NYSE:IBM), Micron Technology Inc. (NASDAQ:MU) will begin producing its Hybrid Memory Cube. The companies claim that this is the first CMOS design to go commercial with TSV interconnects.

HMC parts will be manufactured at IBM’s advanced semiconductor fab in East Fishkill, NY, using the company’s 32nm, high-K metal gate (HKMG) process technology. IBM will present the details of its TSV manufacturing breakthrough at the IEEE International Electron Devices Meeting (IEDM) on December 5 in Washington, DC. Check out an IEDM preview slideshow here.

Also read: IFTLE 74: The Micron Memory Cube consortium by Dr. Phil Garrou

"This is a milestone in the industry move to 3D semiconductor manufacturing," said Subu Iyer, IBM Fellow. "The manufacturing process we are rolling out will have applications beyond memory, enabling other industry segments as well. In the next few years, 3D chip technology will make its way into consumer products, and we can expect to see drastic improvements in battery life and functionality of devices."

Micron’s Hybrid Memory Cube (HMC) reportedly achieves speeds 15 times faster than today’s technology. It combines high-performance logic with Micron’s state-of-the-art DRAM using TSVs. HMC prototypes show bandwidth of 128 gigabytes per second (GB/s), using 70% less energy to transfer data, and boast a form factor that is 10% of the footprint of conventional memory. Applications include large-scale networking and high-performance computing, industrial automation and high-end consumer products.

"HMC is a game changer, finally giving architects a flexible memory solution that scales bandwidth while addressing power efficiency," said Robert Feurle, VP of DRAM marketing for Micron.

Micron Technology Inc. provides advanced semiconductor solutions: DRAM, NAND and NOR flash memory, as well as other innovative memory technologies, packaging solutions and semiconductor systems for use in leading-edge computing, consumer, networking, embedded and mobile products. Micron’s common stock is traded on the NASDAQ under the MU symbol. To learn more about Micron Technology, Inc., visit www.micron.com.

IBM is a leading semiconductor technology company. For more information about IBM’s advanced semiconductor products and manufacturing processes, visit www.ibm.com/chips.

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