November 17, 2011 – Marketwire — STATS ChipPAC Ltd. (SGX-ST:STATSChP), semiconductor test and advanced packaging service provider, completed the expansion of its 300mm wafer bump and wafer-level chipscale packaging (WLCSP) operation in Taiwan.
STATS ChipPAC invested more than $150 million in Taiwan, building up a full turnkey wafer bump and WLCSP offering. The expansion increased production capacity at STATS ChipPAC Taiwan Co. Ltd. to 420,000 bumped wafers/year and 60,000 WLCSP devices/year. STATS ChipPAC Taiwan’s advanced WLP technologies include low-temp cure polymers, copper for under bump metallization (UBM) and redistribution layers (RDL), and more.
Wafer-level, flip chip, and wafer bump packaging processes "cater to the most demanding needs of mobile and consumer devices," said Wan Choong Hoe, EVP and COO, STATS ChipPAC. STATS ChipPAC is growing this business to support advanced technology nodes and form factors. Benefits of WLCSP include virtually die-sized packages, better thermal performance, finer pitch board-level interconnects, and improved functionality.
"We have tripled our Class 100 cleanroom space to 3,478 square meters or 37,437 square feet and significantly increased both our 300mm bump and WLCSP capacity. We have been working to expand our technology processes to support bump pitches down to 40um," said Richard Weng, managing director, STATS ChipPAC Taiwan.
An official inauguration was held at STATS ChipPAC Taiwan with more than 80 honoured guests and company management participating.
STATS ChipPAC Ltd. performs semiconductor packaging design, assembly, test and distribution. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com.
November 16, 2011 – A host of companies are offering, or are in development with, fan-out wafer-level packaging (FO-WLP) for devices with large numbers of I/Os as an alternative to going finer-pitch (0.3-0.35mm) to keep using conventional fan-in technology, says TechSearch International, in an updated report.
Fan-out WLP offers the same low-profile advantage as conventional WLP: singulated die are placed into a "reconstituted wafer" with enough space around each chip to accommodate second-level connections. Among those offering or prepping FO-WLP options is the newly launched Deca Technologies; TechSearch cites Deca president/Tim Olson praising the "tremendous" promise of the technology to improve cost, inflexibility, and cycle times for tooling substrates, assuming the industry can overcome some "capital disadvantages and a few engineering challenges. "We are close to a tipping point," he says. Others offering FO-WLP include the usual SATS firms (Amkor, ASE, SPIL, STATS ChipPAC) plus a host of others including ADL, Freescale, Fujikura, Intel (via Infineon’s wireless division), King Dragon, Nanium, Nepes (via Freescale’s 300mm RCP line), Renesas, and Teramikros (n
The companies will focus on developing "new processes and solutions in the field of wafer-level packaging," said Frank P. Averdung, president and CEO, SUSS MicroTec AG, noting SVTC’s complementary skill set in research and innovation. The companies will jointly develop and characterize new lithography and wafer-bonding technologies.
SUSS MicroTec consigned alignment and bonding equipment to one of SVTC
November 14, 2011 — Microsemi SoC Products Group will use outsourced semiconductor assembly and test (OSAT) provider Amkor Philippines (ATP) for final electrical package test on nearly all its products.
Tester platforms at Amkor will be configured to the same set up as Microsemi SoC Products Group, to avoid any change to form, fit, function, test coverage, or quality of the product. Amkor
November 11, 2011 — Fujikura Ltd. and FlipChip International LLC (FCI) released ChipletT and ChipsetT embedded die packages for single die or multi-die semiconductor packaging applications.
ChipletT and ChipsetT package products are based on Fujikura’s flex-based laminate embedded die "WABE Technology." The roll-to-roll (R2R) flex fabrication process reportedly reduces costs and package profile (<250
November 11, 2011 — Backside-illuminated CMOS image sensors (BSI) capture light directly on the silicon light-sensitive layer. They have a higher sensitivity in a broader spectrum than the mainstream frontside-illuminated imagers (FSI). And in the field of high-end and specialty imagers, they have started to compete with established charged-coupled device (CCD) technology.
BSIs, however, are more difficult to fabricate than FSIs. They require advanced wafer thinning, surface passivation techniques to maximize sensitivity, and careful substrate engineering to minimize crosstalk. Using the possibilities of BSI technology, imager researchers are also looking at alternative architectures, producing pixels and readout electronics as separate dies and stacking those using high-density microbumps and TSVs.
Detecting and capturing light with image sensors: CCD versus CMOS
Silicon is an ideal material to make image capturing sensors, for use in digital cameras and other products. It absorbs that part of the electromagnetic spectrum that — through a lucky quirk of nature — matches the light that is visible with our eyes.
The first commercial sensor chips were CCDs, appearing around 1985. By the early 1990s, the CMOS process was well-established and CMOS imagers started to appear, first for low-end imaging applications or low-resolution high-end applications. Since then, the market has split into two segments. For low-cost, high-volume imagers, CMOS imagers have clearly overtaken CCDs. In high-performance, low-volume applications, CMOS and CCD imagers share the market, mainly because CCD technology still allows for a lower noise. In total, in 2010, the market share of CMOS imagers was 58% vs CCDs; this share is forecast to grow to 66% in 2015 [1].
When light strikes a CCD pixel sensor, it is stored as a small electrical charge. Next, these pixel charges are transported, one at a time, to the output stages. And only then, on a separate chip, are the voltages converted to the digital domain, to bits. A CMOS imaging chip, on the other hand, is an active pixel sensor: each pixel has its own circuitry. CMOS image sensors are fabricated using standard CMOS production processes, so they require less-specialized manufacturing facilities than CCDs. Also, they consume less energy, are faster, are better scalable, and allow integrating on-chip image processing electronics.
The roadmap in the image sensor industry is mostly concerned with decreasing price per pixel while increasing the number of pixels on a given chip surface — reducing the pixel pitch. Currently, high-volume sensor production capacity is moving from 200mm fabs to 300mm fabs, with minimum features reaching 65nm, and resolutions pushing beyond 16 megapixels [1].
But next to this, R&D centers such as imec are also concerned with improving the image quality. Not so much looking for smaller pixels, but for optimal performance. Capturing more photons (improving the quantum efficiency, QE), capturing them in the correct pixels (reducing or eliminating the crosstalk), and capturing a larger part of the light spectrum. Solutions are used in specialty imagers, e.g. for space applications (Figure 1).
Figure 1. 1 megapixel backside-illuminated hybrid imager consisting of a substrate with a passive photodiode array pixel-wise connected to a CMOS readout circuit using 22.5
November 10, 2011 — LED lighting maker Gem Hsin Electronics reduced the size of heatsinks in its LED products by drilling miniscule holes beneath LEDs. The holes allow heated air to escape the LED package.
The holes are drilled with laser-guided technology. The direct-air-release holes improve LED efficiency and lifespan, the company reports. It also wides the company’s lighting beam angles (up to 220). Gem Hsin also says that the finished LED products require 20% less energy than competing products and offer 30,000-hour LED life.
Gem Hsin has started incorporating this advance into its line of T5/T8 LED Tube Lights.
Gem Hsin Electronics is a Taiwan-based manufacturer of LED lamps and other products. To find out more about Gem Hsin and the company’s line of products, go to www.GemHsin.com.
November 10, 2011 — OSRAM Opto Semiconductors increased its IR Power Topled with lens (SFH 4258S/4259S) optical output by 80% over the standard version by integrating a thin-film chip. The infrared (IR) light emitting diode (LED) has the same surface area and drive current.
OSRAM Opto used Nanostack technology to create the thin-film chip with 2 p-n junctions grown one on top of the other. Because of the series circuit, the voltage is higher by approximately a factor of 2. The increased output in the same package footprint suits designs where real estate, even illumination, and cost are factors, said OSRAM’s representatives.
The IR Power Topled produces 80mW optical output power from an operating current of 70mA. The new LED emits at a wavelength of 850nm. It is available with beam angles of
Dig deeper into the new company’s technology in senior technical editor Debra Vogler’s blog from the unveiling event: Deca lands a 1-2 WLCSP punch
The company’s aim is to eliminate supply chain, cycle time, and integration problems with wafer-level packaging (WLP). Advanced interconnects will be formed using SunPower’s silicon solar cell wafer processing methods, which were themselves born out of Cypress’s semiconductor manufacturing technologies.
The new company is part of Cypress’s Emerging Technology Division, which acts similarly to venture capital companies in funding autonomous businesses. SunPower was spun out of Cypress in 2008 in a $2.6-billion tax-free shareholder distribution. Tim Olson is Deca president and CEO.
Moore’s Law is held back by an economic problem, noted Cypress president and CEO T.J. Rodgers, as semiconductor chips become too specialized to be integrated on one die. "The process for one type of chip, for example, a 0.35-micron RF chip, may cost $0.02 per square millimeter — making it horribly uneconomical to integrate an RF block onto a microprocessor wafer costing $0.10 per square millimeter." Deca will integrate dissimilar chips using silicon interconnect technologies at drastically lower costs, competitive with PCB-level interconnect.
Olson said, "We have met stringent reliability requirements and are now fully qualified for production with first revenue expected in early 2012. Given the high level of customer interest and engineering activity, we anticipate multiple additional customer qualifications in the next few quarters. With typical handset OEM PCN (Product Change Notice) acceptance windows averaging around one additional quarter, we are planning for our production ramp in late 2012."
Deca Technologies is an advanced electronic interconnect solutions provider that initially provides wafer level chip scale packaging (WLCSP) services to the semiconductor industry. Deca Technologies is a majority owned and fully independent subsidiary of Cypress. For more information, please visit www.decatechnologies.com.
November 8, 2011 — Invenios developed a 3D Direct Write laser patterning technology for microelectronics packaging that integrates optical, mechatronic, and housing functionalities into the package substrate. The new microchip manufacturing technology, a challenge to deep reactive ion etch (DRIE), produces high angle walls on channels with sub-3
