Date: Tuesday, January 29, 2019 at 1:00 pm EST

Free to attend

Length: Approximately one hour

In semiconductor manufacturing, traditional root cause analysis using FDC summary data is not always effective in solving complex issues, especially when the defect signals are too subtle to detect. Full trace analytics enables the discovery of these hidden signals.  This allows fab engineers to accurately pinpoint the root causes of yield-impacting issues. This webcast will discuss several use cases to showcase how advanced full trace analytics can help not only in provide accurate results, but can also simplify the root cause analysis process and reducing time-to-root-cause, resulting in better yields, lower production costs and increased engineering productivity.
In this LIVE webcast, BISTel’s Chief Product Management Officer, Gabe Villareal will discuss how BISTel is leading the industry with its new full trace analytics to simply root cause analysis, which enables fab engineers to pinpoint the issues than impact yield and productivity quicker than ever. Full trace analytics enables the comprehensive examination of process trace data to allow the detection of abnormalities and deviations to the finest details.

What You’ll Learn:

• Learn how to improve yield and reduce risk with new full trace analytics to simply root cause analysis.
• Hear why traditional root cause analysis using FDC summary data is not always effective in solving complex issues, especially when the defect signals are too subtle to detect.
• Understand how full trace analytics enables the comprehensive examination of process trace data to allow the detection of abnormalities and deviations to the finest details.
• Learn how these techniques can help not only provide accurate results, but can simplify the root cause analysis process and reduce time-to-root-cause. This results in better yields, lower production costs and increased engineering productivity.

About the Speaker:

Gabe Villareal, Vice President, Global Product Management Group, BISTel

As Vice President Global Product Management (GPM) at BISTel, Mr. Villareal leads the company’s product development programs. He is largely responsible for bridging BISTel’s semiconductor industry leading Equipment Engineering Systems (EES) and its new adaptive intelligence (AI) applications for smart manufacturing.  Together,  these intelligent manufacturing solutions detect, analyze and predict answers  to everyday manufacturing challenges quicker and more effectively than ever.  Gabe and his team focus on helping engineers improve quality, productivity, wafer yields, and overall manufacturing effectiveness. For more than 20 years, Gabe has led engineering and product development teams to develop winning Equipment Engineering System (EES) and analytical solutions for the global semiconductor and FPD manufacturing industries. With the meteoric rise of IIoT, Big Data, Edge and Cloud Computing, Gabe and his team are being called on more than ever to support the semiconductor engineering community as they navigate in the age of AI and industry.

Sponsored by:

BISTel is a leading provider of real-time, engineering and automation solutions for the global semiconductor, and electronics industries. Its Equipment Engineering Systems (EES) and adaptive intelligence (AI) solutions for smart manufacturing are shaping the factories of the future,  by connecting data driven manufacturing organizations to better detect, analyze, and predict real-time to changing manufacturing conditions. Consequently, manufacturers can realize major costs reductions, plant wide operational efficiencies, improved yields and unmatched engineering productivity.  BISTel manufacturing solutions collect and manage data, monitor the health of equipment, optimize process flows, analyze large data and quickly identify root cause failures to mitigate risk for engineers and manufacturers worldwide.  Founded in 2000, BISTel has more than 377 employees worldwide. The company is headquartered in South Korea, with offices in California, China, Singapore and Texas.  BISTel has a deep customer following in semiconductor, FPD, and rechargeable batteries, PCB/SMT manufacturing as well as automotive, and steel manufacturing. Its core solutions include:

• Fault detection & classification solutions that include equipment recipe management, advanced process control, equipment performance analysis and more.
• Powerful data mining, root cause analysis & pattern analysis, as well as a new Chamber Matching application to offer the industry its most comprehensive set of data analytics tools on the market.
• Innovative new predictive analytics, predictive maintenance, real-time product & facility monitoring identify issues before they happen.

For more more information contact [email protected] or [email protected]

Date: Thursday, December 13, 2018 at 10:00 AM Pacific / 1:00 PM Eastern

Free to attend

Length: Approximately one hour

As digital-centric scaling pursues solutions in 3D device architectures such as gate-all-around (GAA) transistors, most applications in new leading-edge growth markets such as Edge AI/ML, IoT, automotive and 5G mmWave demand post-bulk processing power and also next-generation analog and RF performance. This webinar is an overview of production-proven fully-depleted silicon-on-insulator (FD-SOI), the only post-bulk planar transistor technology. We will explain and demonstrate how FD-SOI delivers FinFET-like performance, excellent mismatch and noise characteristics and best-in-class Ft and Fmax required for energy-efficient mmWave applications.

What You’ll Learn:

• Learn how fully-depleted silicon-on-insulator (FD-SOI) delivers FinFET-like performance, excellent mismatch and noise characteristics and best-in-class Ft and Fmax required for energy-efficient mmWave applications.
• Hear why most applications in new leading-edge growth markets such as Edge AI/ML, IoT, automotive and 5G mmWave demand post-bulk processing power and also next-generation analog and RF performance.
• Understand why production-proven FD-SOI is the only post-bulk planar transistor technology.

Speakers:

Dr. Jamie Schaeffer – Jamie Schaeffer is Senior Director of Product Offering Management at GLOBALFOUNDRIES.  Schaeffer is currently responsible for the FDX^TM product offerings, including 22FDX® and 12FDX^TM, which enable differentiated solutions for mobile, wireless networking, Internet of Things and automotive markets. Prior to this, Schaeffer had an extensive career in technology development at GLOBALFOUNDRIES, Freescale Semiconductor, and its predecessor Motorola Semiconductor Products Sector.  Schaeffer helped lead the development and transfer into volume manufacturing of the 32nm and 28nm technologies and his earlier work in the semiconductor industry has been recognized with numerous invited talks and a Distinguished Innovator award for his contributions to technology innovation while at Freescale Semiconductor. Schaeffer holds a bachelor’s degree in materials science and engineering from Cornell University and a Ph.D. in materials science and engineering from The University of Texas at Austin.

Dr. Brian Chen – Brian Chen currently serves as Director of FDX^TM Offering Management at GLOBALFOUNDRIES.  Brian has worked in engineering, field, marketing, and operational roles at EDA, IDM, and foundry companies.  Previous products under his management include circuit simulation tools, Liberty library characterization product, device characterization and modeling software, and low-frequency noise measurement system.  Brian received his Ph.D and M.S. degrees in electrical and computer engineering from the Georgia Institute of Technology, U.S., and M.S. and B.S. degrees in engineering from Saint-Petersburg Electrotechnical University, Russia.

About Our Sponsor:

GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Investment Company.

Date: Tuesday, June 5, 2018 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

EUV lithography has steadily been gaining momentum in recent years and edges closer and closer to insertion in manufacturing.  While considerable progress has been made and the first uses of EUV appear imminent, there remain some difficulties that will challenge the rate and degree to which EUV can be employed.  This talk will aim to explore the patterning-related challenges that remain, summarize some of the ongoing efforts to tackle these challenges, and give an outlook towards the future.

What You’ll Learn:

• Understand how EUV lithography has steadily been gaining momentum in recent years and edges closer and closer to insertion in manufacturing.
• Hear about the difficulties that remain and how they will challenge the rate and degree to which EUV can be employed.
• Find out what’s being done to tackle these challenges, and what the outlook is towards the future.

Speaker: Greg McIntyre, Director of Advanced Patterning, imec

Greg McIntyre is Director of Advanced Patterning at imec and responsible for areas related to advanced lithography equipment and process development, metrology and patterning process control, computational lithography, and exploratory patterning materials. Prior to joining imec, he was the technical lead for various areas of advanced lithography, imaging and modeling within the IBM research alliance in Albany, New York. He has published over 80 papers, won 7 best paper awards, and has launched a successful startup in the field. Prior to becoming a lithographer, Greg served as a Captain in the US Army. He holds a Ph.D. and M.S. in electrical engineering from the University of California, Berkeley, and a B.S. from the United States Military Academy at West Point.

Sponsored by LouwersHanique

Featured Products: 3D components in glass and fused silica using “Selective Laser-induced Etching” (SLE) Technologies and Modular Ultra-High Vacuum electrical and optical feedthroughs

LouwersHanique has been a leading specialist in the manufacturing of technical glass and ceramic components as well as assembly technologies for a wide variety of high-tech industries for over 60 years. We are specialized in thermal forming of glass and in the mechanical and laser processing of technical glass and technical ceramics. Our state of the art equipment and clean room facilities allow the precision manufacturing of parts and assemblies with tolerances into the (sub) micron region.

Date: April 24, 2018 at 1:00 pm ET

Free to attend

Length: Approximately one hour

Since 2006, many of new 3D NAND Flash cells have been proposed and commercialized on the market. Already, we have seen 3D NAND cell structure up to 64L/72L with single or multi-stack NAND string architecture. The memory density on Micron/Intel’s 64L 3D NAND 256 Gb/die reached 4.40 Gb/mm² (256 Gb/die). In this session, we’ll overview 3D NAND Flash roadmap, products, cell design, structure, materials and process integration. The 3D NAND cell architecture from major NAND manufacturers including Samsung TCAT V-NAND, Toshiba/Western Digital BiCS, SK Hynix P-BiCS and Micron/Intel FG CuA will be reviewed and compared. Current and future technology challenges on 3D NAND will be discussed as well.

Speaker:

Dr. Jeongdong Choe, Senior Technical Fellow, TechInsights

Jeongdong Choe is a Senior Technical Fellow for TechInsights. He has a Ph.D. in electronic engineering and over 26 years’ experience including 100+ filed/issued patents in semiconductor process integration for DRAM, (V) NAND, SRAM and logic devices. Prior to joining TechInsights in 2011, he worked as a Team Lead in R&D for SK-Hynix and Samsung where he optimized process and device architectures with state-of-the-art technologies for mass production. Jeongdong has been a member of the ‘Future Technology Roadmap’ and ‘Patent Examination’ committees at Samsung, and has led a Process Consulting Group for advanced/emerging NVM devices such as STT-MRAM, ReRAM, and PCRAM and SOI/FinFET/HKMG device for 2x/1x nm future logic and memory devices. He has also written many articles including DRAM Makers Turn to New Process for Sub 2x/1x nm Cells, and Comparing Leading-Edge 2x/1x nm NAND Flash Memories. Jeongdong annually produces a widely distributed roadmaps for Memory Technology.  At Samsung, as Team Lead of NAND FLASH Process Architecture, he advanced next-generation devices, including 42 nm, 35 nm, 27 nm, 21 nm and 19 nm process nodes with optimized DPT (double patterning technology) for 3x and 2x devices and TPT (triple patterning technology) for 1x devices, as well as for sub-20 nm terabit generation for 3D-NAND, including TCAT and VG-NAND architecture.

Sponsored by Tech Insights:

For over 25 years TechInsights has been a trusted patent and technology partner to the world’s largest and most successful companies including 37 of the top 50 U.S. patent holders. By revealing the innovation others can’t inside the broadest range of advanced technology products, we prove patent value and enable business leaders to make the best, fact-based IP and technology investment decisions.

Date: October 3, 2017 at 1 p.m. ET

Free to attend

Length: Approximately one hour

Conventional planar flash memory technology is approaching critical scaling limitations that are driving the transition to 3D solutions. 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will find ways of placing these strings closer to each other through more aggressive lithography.

Join the analysts from TechInsights as they explore 3D NAND flash technology from a process, circuit and systems perspective.

Process

With the boom in 3D NAND technology over the last couple of years, all the major NAND manufacturers such as Samsung, Toshiba, Western Digital (SanDisk), Micron, Intel and SK Hynix have already released their cutting-edge 3D NAND commercial products with 64L. Compared to their previous 32L (or 36L) and 48L, memory density per unit cell array area reached up to 3.4 Gb/mm2 which is 2.7 times higher than 15 nm 2D NAND TLC. This year, the new QLC products were introduced, which further scaled development down to n+1 (96L) and n+2 (128L). Every NAND manufacturer keeps their own 3D NAND architecture, and we’ll explore them in more detail and discuss future 3D NAND technology trends and expectations.

Circuit

With the exception of the memory cell array layout, most 3D NAND flash manufacturers have similar on die peripheral circuit block arrangements, as seen in their previous planar NAND flash products, with the exception of Micron’s latest 32L flash product. In this portion of the presentation, we will look at 3D NAND die photographs and compare die cross sections to identify some of the major differences in circuit implementation and layout arrangements. Challenges in 3D NAND circuit extractions including metal line access for internal signal probing (waveform analysis), memory addressing and programming algorithms will also be discussed.

Systems

There are many similarities between implementations of SSDs, but it is their differences with the use of latest NAND flash devices (especially 3D NAND), that have become of great interest for systems analysis, and will be the topic for discussion in this segment. One of the latest systems analyzed by TechInsights showed many interesting new features and differences in operation, on even simple de-facto standard methods of operation, such as addressing a NAND flash device, as well as read-retry situations.

Speakers

Mohammad Ahmad, Architect

Mohammad Ahmad is an Engineering Solutions Architect in the IP Services group at TechInsights. He has extensive experience with the latest non-volatile semiconductor memory devices, and provides technical support and patent analysis to help global clients maximize the return on their intellectual property investments. Mohammad is responsible for leading, executing and managing large patent portfolio assessments to identify patents for assertion and divestiture and for determining and executing the required reverse engineering in support of the patent portfolios.

He specializes in reverse engineering including circuit extraction, functional testing and internal waveform probing of various semiconductor memories (NAND and NOR Flash, embedded and system memories, DRAM and SRAM). Patent claims analysis, evidence-of-use detection, claim chart documentation, prior art searches and patent/portfolio evaluation and mining.

Dr. Jeongdong Choe, Senior Technical Fellow

Jeongdong Choe is a Senior Technical Fellow for TechInsights. He has a Ph.D. in electronic engineering and over 26 years’ experience including 100+ filed/issued patents in semiconductor process integration for DRAM, (V) NAND, SRAM and logic devices. Prior to joining TechInsights in 2011, he worked as a Team Lead in R&D for SK-Hynix and Samsung where he optimized process and device architectures with state-of-the-art technologies for mass production.

Jeongdong has been a member of the ‘Future Technology Roadmap’ and ‘Patent Examination’ committees at Samsung, and has led a Process Consulting Group for advanced/emerging NVM devices such as STT-MRAM, ReRAM, and PCRAM and SOI/FinFET/HKMG device for 2x/1x nm future logic and memory devices. He has also written many articles including DRAM Makers Turn to New Process for Sub 2x/1x nm Cells, and Comparing Leading-Edge 2x/1x nm NAND Flash Memories. Jeongdong annually produces a widely distributed roadmaps for Memory Technology.

At Samsung, as Team Lead of NAND FLASH Process Architecture, he advanced next-generation devices, including 42 nm, 35 nm, 27 nm, 21 nm and 19 nm process nodes with optimized DPT (double patterning technology) for 3x and 2x devices and TPT (triple patterning technology) for 1x devices, as well as for sub-20 nm terabit generation for 3D-NAND, including TCAT and VG-NAND architecture.

Tarek Alhajj

Tarek Alhajj is an Engineering Solutions Architect in the Intellectual Property and Technical Services group at TechInsights where he creates solutions for complex technical and intellectual property problems, especially those involving memory systems.

In his previous role with the company, Tarek was an Engineering Analyst in the systems and software analysis group, where he performed in depth analysis of various circuits and systems, mostly within downstream products, through a combination of circuit extraction, electrical functional testing and literature research. He has analyzed and tested numerous commercial electronic devices for the purposes of intellectual property support, technical intelligence and research and development. His contributions to the development of reverse engineering and testing techniques, particularly for memories and memory systems such as NAND flash and SSDs, greatly enabled detailed analysis of complex systems. Tarek then moved on to Team Lead in the systems and software analysis group to lead and manage a team of engineers.

Prior to TechInsights, he worked for MOSAID Technologies as a Patent Licensing Engineer where he lead the portfolio management, including the due diligence, licensing and litigation of all flash memory and flash memory systems patent portfolios.

Tarek received a B.Eng. degree in Electrical Engineering from Carleton University, Ottawa, Canada, and an M.A.Sc. degree in Electrical Engineering from McGill University, Montreal, Canada. His studies and research focused mainly on characterization and system level behavioral modeling of complex mixed-signal circuits and systems.

Sponsored by TechInsights

For over 25 years, TechInsights has been a trusted patent and technology partner to the world’s largest and most successful companies including 37 of the top 50 U.S. patent holders. By revealing the innovation others can’t inside the broadest range of advanced technology products, we prove patent value and enable business leaders to make the best, fact-based IP and technology investment decisions. Learn more at http://www.techinsights.com.

Sponsored By:

Date: Wednesday, August 9, 2017 at 1 p.m. ET

Free to attend

Length: Approximately one hour

The slowing down of Moore’s Law even at leading CMOS Fabs due to approaching Physics limits, while at the same time the explosion in demand for chips and systems across a wide range of market segments (compact wearable / portable consumer systems, the transfer and processing of data to and from the cloud, at the high performance end specialized architectures e,g for AI) has revived interest in Dense Off Chip Integration (DOCI ), first used in MCMs (Multi Chip Modules) for mainframes some 3 decades ago.

DOCI can be a lower cost alternative to integration of many functions on a single large chip that is often associated with low fab yields at immature nodes. In the consumer end DOCI is an enabler of compactness and power efficiency. To be accepted in the high performance end DOCI must deliver electrical performance not too inferior to single chips or provide efficient package level integration of heterogeneous designs and Fab technologies e,g. Processor and Memory, that are not easily manufactured on a single wafer. In all cases dense and compact package level interconnects with low parasitics using current and emerging Advanced Packaging (AP) technologies are key to wide adoption of DOCI.

Using metrics like electrical performance, density and cost of package level interconnects we will assess various AP technologies ranging from package substrates/interposers, packages like FO WLPS, flip chip, 2.5d modules, 3d stacks such as PoP, and those using TSVs. Recent commercial examples of integrating processor to memory by different approaches to DOCI will be compared.

Lastly emerging AP technologies (substrates cheaper than dual damascene interposers and TSVs) to reduce the cost of DOCI will be compared and opportunities for further development and implementation identified.

Speakers: 

Dr. Dev Gupta, CTO, APSTL llc, Scottsdale, AZ, USA

While at Motorola and Intel, Dr. Dev Gupta invented many of the Advanced Packaging technologies ( electroplated solder bump flip chip, robotic assembly, organic substrates w/ and w/o core, pillar flip chip, integrated passives, .. ) that have become industry standards today. The micro pillar and thermocompression flip chip technology he invented at Motorola nearly 25 years ago for Gallium Arsenide PAs is now used for building 3d Memory Stacks. He pioneered and managed the transfer of these AP technologies to high volume manufacturing in both the US and Japan. At APSTL he is responsible for identifying technology gaps, developing new technologies to address them, licensing, turn key engineering of Fabs for Advanced Packaging. He also takes an active role in mentoring and training Customer Engineers. Dr. Gupta has many Patents and Publications and often teaches at Conferences the theoretical aspects of Package Level Interconnects, Advanced Packaging and Systems Optimization. The current emphases at APSTL is to lower the cost Adv. Packaging by replacing TSVs, process innovations in die stacking etc. and license them.

• Why there is such renewed interest in DOCI, first used in Multi-Chip Modules for mainframes some 3 decades ago.
• Hear why and how DOCI can be a lower cost alternative to integration of many functions on a single large chip that is often associated with low fab yields at immature nodes.
• Learn how to assess various Advanced Packaging technologies using metrics such as electrical performance, density and cost of package level interconnects.

Silicon Wafer Integrated Fan-out Technology (SWIFT®) Packaging

Curtis Zwenger, VP Adv. Package & Technology Integration

Curtis joined Amkor in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via, and MEMS packaging technologies. He is currently responsible for the development and commercialization of Amkor’s Advanced Wafer Level Fan-Out package technologies, including WLFO and SWIFT®. Prior to joining Amkor, Curtis worked for Motorola. He holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix.

Curtis will discuss:

• The development of SWIFT® technology and its extension into unique 3D structures.
• The advantages of SWIFT® designs as compared to current competing packaging technologies.
• How the SWIFT® process is poised to provide robust, reliable, and low-cost 3D packaging solutions for advanced mobile and networking products.

Sponsored by Amkor Technology

Amkor Technology, Inc. is one of the world’s largest providers of state-of-the-art packaging design, assembly and test services. As a strategic partner to leading semiconductor companies and electronics OEMs, operations include over 10M ft² of volume production, development, sales and support services in Asia, Europe and the United States. Our solutions enable customers to focus on semiconductor design and wafer fabrication while utilizing Amkor as their turnkey provider and packaging technology innovator. Additional information at: www.amkor.com.

Date: Thursday, May 17, 2018 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

The increased use of artificial intelligence (AI) and machine learning (ML) techniques such as deep learning is creating a myriad of both challenges and opportunities for enhancements in manufacturing in terms of improved capacity, quality, and efficiency. The semiconductor industry poses somewhat unique challenges arising from its complex, high precision and highly dynamic production environment. One key way that these challenges are being addressed in semiconductor is by using an approach called “computational process control” or “CPC” in which AI and ML are combined with subject matter expertise to provide higher quality analytical solutions. This webcast will look at the AI/ML explosion, what it means to the semiconductor industry, and how CPC is being used to enhance the benefits of these analytical techniques.

What You’ll Learn:

• Learn how AI and machine learning can help semiconductor manufacturers improve capacity, quality, and efficiency.

• Find out why the semiconductor industry poses somewhat unique challenges arising from its complex, high precision and highly dynamic production environment.

• Hear about how new computational process control (CPC) techniques, which combine AI, ML and subject matter expertise, provide higher quality analytical solutions.

Speaker: 

Dr. James Moyne is a consultant for standards and technology in the Applied Global Services group at Applied Materials. He received his Ph.D. degree from the University of Michigan, where he is currently an associate research scientist in the Department of Mechanical Engineering. James has been involved with machine learning solutions for the semiconductor industry since the early 90s starting with his founding of MiTeX Solutions, Inc. in 1995, which provided the first 3rd party advanced process control solutions for semiconductor manufacturing. He has experience in advanced process control, prediction technology (predictive maintenance, virtual metrology, and yield prediction), and big data technology (focusing on machine learning and data quality); and is the author of a number of refereed publications and patents in these areas. James is currently chair of the Factory Integration Technical Working Group of the International Roadmap for Devices and Systems, and is technical chair of the annual Advanced Process Control conference for the microelectronics industry (www.apcconference.com).

Sponsored by XtremeEDA: 

Founded in 2002, XtremeEDA is a preferred North American based provider of front-end design and verification services for the semiconductor industry.  Our team is unparalleled – with employees averaging 20+ years of semiconductor industry experience and expertise that spans most major sectors.

Our business approach emphasizes enduring and transformational relationships to employ creative solutions that enable extraordinary results for all stakeholders. For more information, visit us at: www.xtreme-eda.com.

Date: Wednesday, April 26, 2017 at 2 p.m. ET

Free to attend

Length: Approximately one hour

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and characterization. In this webcast, hear from leading metrology expert Alain Diebold, who will discuss new challenges and opportunities in the field of semiconductor metrology, focusing on new transistor structures, nanoscale films and structures and how to use plasmonics with scatterometry to increase sensitivity to metal linewidth.

Speaker: 

Alain Diebold, Interim Dean, College of Nanoscale Sciences

Alain Diebold is Interim Dean at the Colleges of Nanoscale Science and Engineering (CNSE) SUNY Polytechnic Institute. He is also the Empire Innovation Professor of Nanoscale Science; Executive Director, Center for Nanoscale Metrology; and Executive Director, NC3. He is a fellow of the American Vacuum Society and SPIE as well as a senior member of the IEEE. He is an associate editor for IEEE’s Transactions on Semiconductor Manufacturing. Before moving to Albany, Alain was a Senior Fellow at SEMATECH.  Prior to moving to Austin, He was a senior chemist at Allied Signal in Morristown, NJ. Alain received his PhD from Purdue University in 1979.

Sponsored by National Instruments and Particle Measuring Systems, Inc.

National Instruments provides powerful, flexible technology solutions that accelerate productivity and drive rapid innovation. From daily tasks to grand challenges, NI helps engineers and scientists overcome complexity to exceed even their own expectations. Customers in nearly every industry—from healthcare and automotive to consumer electronics and particle physics—use NI’s integrated hardware and software platform to improve our world. To learn more, click here.

Particle Measuring Systems Inc. (PMS), a subsidiary of Spectris plc, is a global technology leader in contamination monitoring, the inventor of laser particle counting, and now is the leading provider of solutions for monitoring and controlling many forms of contamination that impact companies that manufacture in ultra-clean environments. Learn more at pmeasuring.com.

Date: Friday, April 7, 2017 at 1pm ET

Free to attend

Length: Approximately one hour

The landscape of microelectronics manufacturing is changing rapidly as the amount of data being generated in the factory grows exponentially along with the capabilities for managing and analyzing that data. Additionally the move to smart manufacturing is adding key capabilities such as connectivity up and down the supply chain and simulation mechanisms to support cyber-physical system concepts. In light of these capabilities we are seeing an explosion in opportunities in Advanced Process Control (APC) and its family of solutions; these solutions include model-based process control, Fault Detection and Classification (FDC), and predictive capabilities such as Predictive Maintenance (PdM), Virtual Metrology (VP), yield prediction, and big data and data analytics approaches. This opportunity explosion is associated with key technology trends such as more service-based cooperative solutions, and increased incorporation of processes and equipment knowledge in solution approaches (often termed Computational Process Control or CPC). The APC Conference is the key conference in the microelectronics industry for exploration of APC challenges and solutions (www.apcconference.com). The 29^th Annual APC Conference will be held this October 9-12 in Austin Texas, and will provide insight into the aforementioned APC and related advancements, as well as the important role that APC will play in microelectronics smart manufacturing.

Speakers: 

Dr. James Moyne is a Consultant for Standards and Technology to the Applied Global Services group at Applied Materials. He received his Ph.D. degree from the University of Michigan, where he is currently an Associate Research Scientist in the Department of Mechanical Engineering. James has been involved in APC since the early 90’s starting with his founding of MiTeX Solutions, Inc. in 1995, which provided the first 3rd party advanced process control solutions for semiconductor manufacturing. Dr. Moyne has experience in advanced process control, prediction technology (predictive maintenance, virtual metrology, and yield prediction), and big data technology (focusing on analytics, network performance and data quality); he is the author of a number of refereed publications and patents in these areas. James is currently chair of the Factory Integration Technical Working Group of the International Roadmap for Devices and Systems, and is co-chair of this year’s APC Conference.

Dr. Bradley Van Eck is Vice President of the Integrated Measurement Association (IMA) and Co-Chair of the Advanced Process Control Conference. He received his Ph.D. degree from Michigan State University. Bradley has chaired or co-chaired the APC Conference since 1998. He was instrumental in establishing APC conferences in Europe and Asia (Taiwan, Japan). Dr. Van Eck was a founding member of the Integrated Measurement Association in 1999.   Bradley has worked in various capacities for SEMATECH and ISMI from 1990 – 2011. These include, AEC/APC Conference Chair, sensor integration for APC, SEMI Standards, e-Manufacturing, and contributions to the ITRS Factory Integration Technical Working Group.

Sponsored by Epicor

Epicor Software Corporation is a global leader delivering inspired business software solutions to the manufacturing, distribution, retail and services industries. With over 40 years of experience serving small, midmarket and larger enterprises, Epicor enterprise resource planning (ERP), production control software (MES), and supply chain management (SCM), enable companies to drive increased efficiency and improve profitability. With a history of innovation, industry expertise and passion for excellence, Epicor provides the single point of accountability that local, regional and global businesses demand. www.epicor.com/electronics

Date: Tuesday, March 28, 2017 at 1pm ET

Free to attend

Length: Approximately one hour

The rise of Internet of Things (IoT) and the cloud and their associated technologies and platforms are slowly but surely fueling the emergence of new market segments that are shaping and transforming our way of life. Learn how the IoT applications and use-cases that span clients/devices, networks, and data centers are driving new requirements for semiconductors including ultra-low power, ultra-low leakage, smaller and denser packaging, and cost effectiveness. And find out exactly how this IoT trend represents a growth opportunity for the semiconductor industry that has not been seen since the early days of the Internet.

Speaker:

Nitin Kulkarni, Principal Staff Advertising Marketing Manager, GLOBALFOUNDRIES

Nitin is responsible for product and technical marketing of GLOBALFOUNDRIES’ CMOS product portfolio, with a focus on IoT and Industry 4.0 market segments.  Prior to joining GLOBALFOUNDRIES, he was Divisional Marketing Manager at Cypress Semiconductor (formerly Spansion, Inc.) where he was instrumental in launching and leading marketing activities for the company’s Serial Flash (SPI) product line.

Nitin has over 20 years’ experience in engineering, product management and marketing of semiconductor products including x86 microprocessors, communications/networking and flash memory. He holds a Master of Science degree in Electrical Engineering (MSEE) from the University of North Carolina, Charlotte, and a Bachelor of Engineering (BE) in Electrical Engineering from the College of Engineering, University of Pune, India.

Ashvini Patil, Product Management of Embedded Memory at GLOBALFOUNDRIES

Ashvini is responsible for product management and marketing of GLOBALFOUNDRIES’ embedded memory product offerings, across all market segments.  Prior to joining GLOBALFOUNDRIES, she worked as a Product Marketing Engineer at Cypress Semiconductor (formerly Spansion, Inc.) where she was managing and marketing various NOR flash memory products.

She holds a Master of Science degree in Electrical Engineering (MSEE) from the Northwestern Polytechnic University, CA, and a Bachelor of Engineering (BE) in Electrical Engineering from North Maharashtra University, India.

Sponsored by Epicor

Epicor Software Corporation is a global leader delivering inspired business software solutions to the manufacturing, distribution, retail and services industries. With over 40 years of experience serving small, midmarket and larger enterprises, Epicor enterprise resource planning (ERP), production control software (MES), and supply chain management (SCM), enable companies to drive increased efficiency and improve profitability. With a history of innovation, industry expertise and passion for excellence, Epicor provides the single point of accountability that local, regional and global businesses demand. www.epicor.com/electronics