Date: December 15, 2016 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

The smartphone market is expected to reach 1.5B units in 2016 consuming nearly 1/3 of the IC market as smartphones become the mini mobile computers in capabilities and the central hub/gateway for the Internet of Things (IoT) devices including wearables and home monitoring devices. Since 2011 the high end smartphone application processor (AP) has advanced a logic technology node every year using 45nm technology in 2011 for the Apple A5 AP in the iPhone 4s to the introduction of 14/16nm FinFET technology in 2015 for the iPhone 6s/6s+ A9 and also the Samsung Galaxy S6. This year (2016) the Galaxy S7 still uses 14nm FinFET and the iPhone 7/7+ A10 uses 16nm FinFET, but with the announcements from both Samsung and TSMC in Oct 2016 of their production start of 10nm FinFETs, smartphone APs using 10nm FinFET technology will appear in 2017 starting with the Samsung Galaxy S8 in March and then iPhone 7s in September.  At the 2016 VLSI Symposium in June both Samsung and TSMC papers mentioned their key improvements in 10nm technology over 14/16nm technology were in channel mobility enhancement, S/D-epi doping and contact resistance (Rc) reduction with a complete session #7 dedicated to papers on Rc. In 2018/19 smartphone AP using 7nm FinFET with single or dual high mobility strained-channel material replacing raised S/D-epi stressors to further boost device performance and improved Rc will appear. At the Oct 2016 ECS PRiME conference there were several papers describing options and issues for relaxed and strained high mobility SiGe and Ge channel materials reported in the “Symposium on High Purity and High Mobility Semiconductor 14” and “Symposium on SiGe, Ge and Related Materials”.  Then by 2020/21 5nm FinFET, lateral-GAA (gate-all-around) Si or Ge nanowire or Monolithic 3-D vertical stacked transistors using thin wafer bonding like LETI’s CoolCube are options for More Moore scaling.  More than Moore 3-D stacked devices are also being driven by the smartphone market to achieve small compact packaging.  Sony introduced the first stacked backside CMOS image sensor with the pixel array on top of the logic circuit using TSV (through silicon via) and this was incorporated into the Apple iPhone 5 in 2012 as an 8Mpixel rear facing camera. This year Sony’s 3rd generation stacked 3-D 12Mpixel rear camera that uses wafer to wafer bonding called Hybrid DBI (direct bond interconnect) was introduced into the Samsung Galaxy S7 smartphone. The first 3-D NAND Flash memory was introduced in the Apple iPhone7/7+ by Toshiba as a 256Gb 48-layer 3-D NAND while the optional 128Gb Flash is a 2-D NAND using 15nm technology from Toshiba or SK Hynix. Therefore, this will give an update to the previous April 30, 2015 Webinar on Smartphone as the technology driver.

Speaker: John Borland, J.O.B. Technologies

John Ogawa Borland received his B.S. and M.S. degrees for MIT. He completed his BS thesis on InP liquid phase epitaxial growth at Hughes Malibu Research Labs in 1980 and his MS thesis on InP molecular beam epitaxial growth at Nippon Telephone and Telegraph (NTT) Labs in Musashino, Tokyo, Japan in 1981. He is a senior member of IEEE, the IEEE Hawaii section chair (2014-present), the chair for the Hawaii joint EDS/SSCS chapter and on the advisory committee for the IEEE International Workshop on Junction Technology (2008-2016). He is also a member of the Electrochemical Society (ECS) and was co-organizer for various ECS technical conferences/symposium including the “Symposium on ULSI Process Integration” (2001, 2003 & 2005), “Semiconductor Silicon” (1994 & 1998) and “Chemical Vapor Deposition” (1987, 1989, & 1991). He has published over 140 technical and invited papers around the world in the areas of advanced semiconductor device manufacturing techniques and high efficiency c-Si solar cells and has been awarded 6 patents. Currently he is President of J.O.B. Technologies a strategic technical marketing consulting company he founded in June 2003 providing service to the semiconductor device manufacturing, equipment and metrology companies in the area of advanced front end of line process technology with the current focus on 7nm and 5nm technology. This includes localized high mobility compressive and tensile strain channel material formation (SiGe, SiC, SiGeSn, Ge, GeSn, GeSi and GeC) and high dopant activation using advanced annealing and metrology techniques. He was Director of Operations of APIC’s subsidiary Advanced Integrated Photonics a silicon photonics development Fab in Honolulu, Hawaii from April 2013 to its shutdown in August 2014 with focus on Ge technology for Ge photo detector dark current leakage reduction by 300x and Si-waveguide performance improvements. From July 1998 to May 2003 he was Director of Advanced Business Development at Varian Semiconductor Equipment Associates pioneering Ultra Shallow Junction by beam-line and plasma implantation with high dopant activation and low junction leakage. From Nov. 1992 to July 1998 he was Vice President of Strategic Technology at Genus pioneering high energy ion implantation for CMOS twin-well, triple-well and epi replacement on the implant side and on the CVD side integrated CVD polycide and selective HF vapor cleaning. From Sept. 1983 to Nov. 1992 he was at Applied Materials pioneering CMOS-epi latch-up immunity, epi-gettering, selective epi growth (SEG/ELO) for device isolation and low temperature low pressure single wafer epi and poly system development (Centura-epi and Centura-poly). From Aug. 1981 to Sept. 1983 he was at National Semiconductor Corp. developing the 1.25um VHSIC-CMOS front end processing including intrinsic gettering to improve gate oxide integrity and improved CMOS latch-up immunity through retrograde well, buried layer and epilayer engineering.

Sponsored by Versum Materials 

Versum Materials has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  https://www.versummaterials.com

November 17, 2016 at 1:00 pm ET

Free to attend

Length: Approximately one hour

Moore’s Law scaling can no longer maintain the pace of progress just when we need it most. Data, logic and applications are migrating to the cloud, consumerization of data and the rise of the Internet of Things are placing new demands and they are all occurring at the same time. Difficult challenges in power, performance, latency, bandwidth density, security and cost threaten our ability to maintain the progress that has enabled the growth of information technology. Meeting these challenges will require reduction in power and cost per function by a factor of 10⁴ over the next 15 years while improving performance and decreasing latency. Only a revolution in packaging through Complex 3D-SiP can provide a solution. This will require new tools for design and simulation, test, new packaging architectures, production processes, materials, and equipment. The difficult challenges and potential solutions will be discussed, including critical test issues.

Speaker: 

Bill Bottoms, Chairman & CEO, 3MT Solutions

Dr. W. R. “Bill” Bottoms, the holder of a Ph.D. from Tulane University, has an extensive background in academia, venture funding, and in the commercial semiconductor equipment sector. Since founding 3MTS in 1999, Bill Bottoms has provided strategic leadership and vision in keeping with the promise of the 3MTS business model. Dr. Bottom has also served on a number of important government and industry committees and advisory positions. Key posts include chairmanship of the subcommittee of the Technical Advisory Committee of the United States Commerce Department’s Export Control Commission for Semiconductor Equipment and Materials.

Sponsored by Astronics

November 15, 2016 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

Directed self-assembly (DSA) patterning is one of the primary methods being pursued for future advanced patterning nodes. Since DSA’s initial introduction in the early 2000s, great progress has been made. However, many challenges remain for achieving manufacturing readiness. Key improvements in the areas of materials, defectivity, and process integration are still needed. This webcast will cover published progress to date, review key improvements needed, and discuss new advances in DSA technology. Results from CEA-LETI’s 300-mm lab-to-fab for validation of DSA’s manufacturing readiness will be discussed.

Speakers: 

James Lamb is a 33-year veteran of the semiconductor and electronics industry in both technology development and commercialization. He currently serves as Corporate Technical Fellow at Brewer Science. Previously, he served as Director of the Carbon Electronics Center and Printed Electronics Center from 2010-2014. From 2008-2010, Jim served as Managing Director of Product Management, and from 2001 through 2008, he served as Director of Corporate Business Development and the New Business Group. Earlier responsibilities at Brewer Science include Product Reliability Manager, Customer Technical Service Manager, and ARC® materials Quality Control Manager. Before joining Brewer Science in 1984, he worked as a Process Engineer at IBM East Fishkill. He graduated from the University of Missouri-Rolla in 1982 with a B.S. in Chemical Engineering. During his career, he has contributed as an inventor on 19 patents and as a coauthor of 28 technical publications. 

Raluca Tiron joined Leti’s lithography group in 2004, working on e-beam lithography. In 2005, she integrates Leti’s Resist Expertise Center, where she worked on advanced lithography process development, resist characterization and mechanisms comprehension in 193 nm lithography. Starting in 2008, her research interest focused on directed self-assembly (DSA) of block copolymers, and she currently leads this activity at Leti. Dr. Tiron has been Leti project leader in several projects, including the national project MAGNIPHICO and the European project PLACYD. She is currently also in charge of an industrial collaboration around the DSA. She has authored and coauthored more than 60 papers in international reviews and holds more than 15 patents. Dr. Tiron received her PhD degree in molecular magnetism from Joseph Fourier University France in 2004.

October 26, 2016 at 1 p.m. ET

Free to attend

Length: Approximately one hour

With the change in the traditional IC scaling cadence, the expansive growth of “Big data,” and the pervasive nature of computing, rises a paradigm shift in integrated circuit scaling and microelectronic devices. The pervasive nature of computing drives a need for connecting billions of people and tens of billions of devices/things via cloud computing. Such connectivity effect will generate tremendous amount of data and would require a revolutionary change in the technology infrastructures being used to transmit, store and analyze data. The exponential impact of connectivity represents a data-centric future and drive an accelerated transformation throughout the network fabrics. Additionally, the users’ expectations and demand of emerging applications, such as autonomous driving, would not tolerate today’s level of latency and computing capacity. All aspects of the computing continuum – silicon, software and computing capacity that are staggered at different levels in the network- would need to be transformed and advanced performance would need to be pushed to lower levels of the network delivering an increased speed, capacity and an immediate access. This fundamental shift manifests itself through different device (s) requirements and is driving a third wave of technologies with a larger semiconductor footprint. With that comes an increased reliance on microelectronics packaging to deliver far more integrated, complex and advanced solutions at different levels of the network- from handheld and client interface devices to the data center, the cloud and devices at the edge. With accelerated and extended product life-cycle expectations, wearable electronics, and a large assortment of IoT devices, next-generation electronics will require several new packaging solutions.  Smaller form factors, lower power consumption, flexible designs, increased memory performance, and-more than ever­­­-a closely managed silicon package, co-optimization and architectural innovations.  Heterogeneous integration through package with technologies such as system in package (SIP), on package integration (OPI) and fan-out (WLFO and PLFO) are poised to change the packaging industry and play a disruptive role in enabling next generation devices.

The above mentioned move to cloud computing, the transformation of the network and the growth of data analysis are the fundamental growth drivers for the integrated circuit (IC) scaling moving forward. In turn, they represent a tremendous opportunity for microelectronics packaging to deliver, grow and transform into an increasingly influential and enabling role.

Speaker: 

Dr. Islam Salama, Intel Corporation

Dr. Islam Salama is with Intel Corporation responsible for packaging substrate Pathfinding of the high density interconnect across all Intel products. In this capacity, Islam manages a global team of technologists and manufacturing team responsible for delivering next generation packaging technologies. His team focuses on packaging substrate architectures, process and materials technology building blocks, intellectual property management, and manufacturing ecosystem development.

Islam has a Ph.D. in laser materials processing from the College of Optics and Photonics (CREOL), UCF and has been with Intel since 2003. Islam authored over 35 technical papers, was awarded more than 50 international patents in the fields of HDI substrate technology, laser technology, materials processing and semiconductor fabrication. Islam is an elected member of the board of directors for the Laser Institute of America (LIA), a member of the steering committee with the international technology manufacturing initiative (iNEMI), and a board member of Applicote Associates LLC-a photonics and manufacturing technology start-up.

Sponsored by Air Products 

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

September 27, 2016 at 1 p.m. ET

Free to attend

Length: Approximately one hour

An industrial revolution is in the making, equivalent some say to the introduction of steam power at the tail end of the 18th century. Known as smart manufacturing, Industry 4.0 (after the German initiative Industrie 4.0), the industrial internet of things (IIoT), or simply the fourth industrial revolution, the movement will radically change how manufacturing is done. Greater connectivity and information sharing — enabled by new capabilities in data analytics, remote monitoring and mobility — will lead to increased efficiency and reduced costs. There will be a paradigm shift from “centralized” to “decentralized” production. Semiconductor manufacturing has long been thought of as the most advanced manufacturing process in the world, but it’s not clear if long-held beliefs about how proprietary data, such as process recipes, are managed. Industry experts will examine the potential for the semiconductor factory of the future, and discuss potential roadblocks.

Speaker:

Tom Sonderman, Vice President and General Manager, Software Business Unit 

Thomas Sonderman is vice president and general manager of Rudolph’s Integrated Solutions Group. He previously served as vice president of manufacturing technology at GLOBALFOUNDRIES. Prior to GLOBALFOUNDRIES he spent more than 20 years with AMD, where he held numerous executive management and engineering positions. Sonderman is the author of over 45 patents and has published numerous articles in the area of manufacturing technology. He received a BS in Chemical Engineering from the Missouri University of Science and Technology and an MBA in electrical engineering from National Technological University.

Alan Weber, Vice President, New Product Innovations, Cimetrix

Alan Weber is currently the Vice President, New Product Innovations for Cimetrix Incorporated. Previously he served on the Board of Directors for eight years before joining the company as a full-time employee in 2011. Alan has been a part of the semiconductor and manufacturing automation industries for over 40 years. He holds bachelor’s and master’s degrees in Electrical Engineering from Rice University.

Sponsored by Epicor

Epicor Software Corporation is a global leader delivering inspired business software solutions to the manufacturing, distribution, retail and services industries. With over 40 years of experience serving small, midmarket and larger enterprises, Epicor enterprise resource planning (ERP), production control software (MES), and supply chain management (SCM), enable companies to drive increased efficiency and improve profitability. With a history of innovation, industry expertise and passion for excellence, Epicor provides the single point of accountability that local, regional and global businesses demand. www.epicor.com/electronics

September 22, 2016 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

The semiconductor industry’s response to perfluorinated compounds PFCs started in 1994 when DuPont, the supplier of the primary gas used in CVD chamber cleans, C2F6, issued a sales policy restricting sales after 12/31/96 “…only to those applications that contain and either recover or destroy” C2F6 subsequent to use. The sales policy started an industry effort to understand potential impacts of all fluorinated greenhouse gases used in semiconductor manufacturing and to develop methods to estimate and reduce emissions. The industry has worked on a global basis via the World Semiconductor Council to develop common PFC metrics, measurement methodologies and approaches to reduce emissions. Preferring a pollution prevention approach, the industry and its suppliers have evaluated and implemented when feasible process optimization, gas substitution, capture/recycle and abatement. The WSC also set a goal to reduce absolute PFC emissions by 10% from baseline levels by 2010. The WSC exceeded the 2010 goal, achieving a 32% reduction, largely by replacing carbon based PFC chamber cleaning gases with NF3 in new process equipment, optimizing processes to reduce gas consumption, and using alternative chemistries and installing abatement where feasible. The new WSC2020 target calls for the implementation of best practices to further reduce normalized emissions in 2020 by 30% from the 2010 aggregated baseline. How do the semiconductor industry’s greenhouse gas emissions compare to other sectors, what data uncertainties exist, and what can be done to cost effectively achieve further emissions reductions?

Speakers: 

Debbie Ottinger, USEPA

Deborah Ottinger has worked on the U.S. Environmental Protection Agency’s (EPA’s) programs to protect climate and stratospheric ozone since 1991. She currently plays a key role in the implementation of EPA’s Greenhouse Gas Reporting Program (GHGRP), which requires large emitters and suppliers of greenhouse gases (GHGs) to monitor and report their emissions and supplies to EPA. She also manages the U.S. Emissions Inventory Program for fluorinated GHGs emitted from industrial processes.

Dr. Michael Czerniak, Environmental Solutions Business Development Manager, Edwards

Starting his professional career with Philips, initially in their UK R&D labs and subsequently in the fab in Nijmegen, Holland, Mike has worked in the semiconductor business since gaining his PhD in 1982. He had subsequent marketing roles at UK-based OEMs Cambridge Instruments, VSW and VG Semicon before joining Edwards 19 years ago. He has held various technical and marketing roles before starting his current role earlier this year.

David Speed, Distinguished Member of the Technical Staff, GLOBAL FOUNDRIES

David Speed is a Distinguished Member of the Technical Staff at GLOBALFOUNDRIES. He works in the corporate EHS group and represents GLOBALFOUNDRIES on a wide variety of environmental, health, and safety issues. He has a PhD in Environmental Engineering from UCONN, with BS and MS degrees from URI and RPI.

Sponsored by Edwards

Edwards is a leading developer and manufacturer of sophisticated vacuum system products, abatement solutions and related value-added services. Our products are integral to manufacturing processes for semiconductors, flat panel displays, LEDs and solar cells; are used within an increasingly diverse range of industrial processes including power, glass and other coating applications, steel and other metallurgy, pharmaceutical and chemical; and for both scientific instruments and a wide range of R&D applications.

Date: September 14, 2016 at 1 p.m. ET

Free to attend

Length: Approximately one hour

For a semiconductor technology node, the BEOL definition must support minimal parasitic impact to technology, sufficient reliability, required dimensional scaling from previous nodes for standard cell and custom logic requirements, and high yielding/low cost integration schemes. This webcast will discuss the key BEOL elements and innovations in these areas for the 7nm nodes and beyond. The individual elements are often in conflict with each other, but must be considered in unison to determine the overall best definition.

Speaker:

Larry Clevenger, Ph.D., Senior Technical Staff Member , 5nm, 7nm, 10nm and 14nm BEOL Architect, IBM Research

Dr. Larry Clevenger is an internationally recognized leader in semiconductor technology – taking new products from innovation to definition to early production. Since 2000 he has defined new semiconductor technologies for IBM as a chip hardware lead architect. His area of excellence is optimizing the on-chip interconnect from silicon devices to semiconductor packaging substrates for performance, yield, and cost. He is a member of the IBM Academy of Technology and he is a life time IBM Master Inventor, with over 230 issued patents. Dr. Clevenger received a B.S. in Material Engineering from UCLA and a Ph.D. in Electronic Materials from MIT.

Sponsored by Air Products

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

Date: August 9, 2016 at 1 PM ET

Free to attend

Length: Approximately one hour

In this high-pressure environment, leading semiconductor companies are swapping out older manufacturing executions systems (MES) for modern MES. Surprised? True, the perceived risk of changing out MES in a semiconductor facility is high. Yet companies have done it with great success and enormous business benefits.

Fairchild Semiconductor’s positive experiences as it strives for quality, on-time delivery, new product introduction success, improved productivity and quality are indicative. In just one year, Fairchild switched out aging systems for a new MES at a plant in China – and the following month, they got it up at a second plant. Learn what they did to ensure the change happened quickly and without a hitch.

In addition to this case study, you’ll hear from a leading industry analyst who has interviewed dozens of people from semiconductor companies that have succeeded with the move to modern MES.

Join this free 1-hour session from your desk to learn:

• What’s modern MES? The radically different face of today’s MES
• Benefits to make the case: How modern MES addresses business challenges
• How to change: Options for an MES changeover project
• Succeed with speed: The 1-year MES change at Fairchild
• Lessons Learned: What Fairchild and others did to ensure success

Speakers:

Harold Caldwell, Manufacturing Systems IT Director, Fairchild Semiconductor

Harold Caldwell is the IT Director of Global Manufacturing Systems at Fairchild Semiconductor. He has over 30 years of semiconductor manufacturing experience, including solutions for WIP tracking, quality systems, equipment automation, yield analysis, factory planning, and analytics. Harold’s career has focused on enabling increased operational efficiency as well as product quality and yield improvements through effective deployment of information technology.

Julie Fraser, Principal and President, Iyno Advisors

Julie Fraser is Founder and Principal of Iyno Advisors Inc., where she fosters understanding between buyers and sellers of solutions for production, design, supply chain and analytics. She has researched and written hundreds of reports, papers, articles, and blog posts including the MES Fundamentals chapter of McGraw-Hills Semiconductor Manufacturing Handbook, due out in autumn of 2016.

Sponsored by Siemens

Siemens PLM Software, a business unit of the Siemens Digital Factory Division, is a leading global provider of product lifecycle management (PLM) and manufacturing operations management (MOM) software, systems and services. Camstar Semiconductor Suite in the Siemens MOM portfolio is a global-ready, growth-ready enterprise manufacturing execution system (MES) that enables semiconductor companies to keep pace with the huge advances in innovation and customer expectations. For more information, visit: www.siemens.com/mom/camstar.

Date: July 28, 2016 at 10 AM MT

Free to attend

Length: Approximately one hour

Decreasing the time to detect, contain and mitigate very low levels of Airborne Molecular Contamination (AMC) is critical for high tech manufacturers. Costs associated with AMC-related quality issues and yield losses are well understood, and adequate reduction of AMC is critical for clean manufacturers to stay competitive.

Technical personnel need the flexibility to efficiently collect AMC data with good temporal-spatial resolution anywhere in the clean environment for both sustaining sample plans, as well as to collect site-specific data to converge on AMC sources during troubleshooting events. A brief overview of AMC will be presented along with the latest technology for efficiently identifying AMC sources in the cleanroom.

Speaker: 

Dan Rodier, Ph.D., Technology Development Manager, Electronics Division, Particle Measuring Systems

Dr. Dan Rodier has a Ph.D. in analytical chemistry from the University of Colorado and has over 25 years of experience developing and implementing technologies and strategies to measure airborne molecular species and particulate contamination. He has worked with customers across Asia, Europe, and North America to implement monitoring programs in the semiconductor, disk drive, and display industries.

Sponsored by Particle Measuring Systems Inc. 

Particle Measuring Systems Inc. (PMS), a subsidiary of Spectris plc, is a global technology leader in contamination monitoring, the inventor of laser particle counting, and now is the leading provider of solutions for monitoring and controlling many forms of contamination that impact companies that manufacture in ultra-clean environments. Learn more at pmeasuring.com.

Date: May 26, 2016 at 1 PM ET

Free to attend

Length: Approximately one hour

Wafer level packaging (WLP) using fan-out technology is a disruptive technology for achieving low-cost, low-profile package solutions for a wide range of applications, including mobile, MEMs, tablets, and automotive. Fan out technology provides cost-effective, high-density interconnects in a small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.

Speaker: 

Bernard Adams, Deputy Director, Product Technology Marketing, STATS ChipPAC

Bernard Adams is Deputy Director, Product Technology Marketing at STATS ChipPAC where he is responsible for marketing and business development of the Company’s wafer level packaging technology.  He has been with STATS ChipPAC since 2013 and has a diverse background in sales, strategic marketing, finance and product development experience in flip chip technology, backend packaging and front end semiconductor expertise. Prior to joining STATS ChipPAC, Bernard was with Cleanpart US LLC where he was the Micron-Intel Global Account Manager and the Western Regional Manager, responsible for supporting the top 35 integrated Device Manufacturers with semiconductor engineering and tools services. He has also held sales leadership positions at Quantumclean, Leica Microsystems, Electroglas and Flip Chip Technologies. Bernard has a Bachelor of Science in Electrical Engineering from Purdue University and a Masters of Business Administration in International Finance from the University of Pittsburgh.

Sponsored by Zeta Instruments

Zeta Instruments designs and manufactures Multi-Mode non-contact optical profilers and defect inspection systems for multiple high-technology industries, including: advanced semiconductor packaging, high-brightness LEDs, advanced glass manufacturing, solar, microfluidics and data storage.

Zeta’s growth has been driven by rapid technology progress combined with strong focus on customer requirements.  As a result, Zeta has installed production and R&D related equipment in 23 different countries. The rapid adoption of Zeta’s products is a testament to the company’s differentiated technology and a turn-key solution based approach towards designing the tools.  The advanced Zeta-580 Optical Profiler has been adopted by the leading OSATs for WLCSP and FOWLP related metrology and inspection.

Our locations include our headquarters in San Jose, CA, a regional office in Shanghai, China, and sales and service representatives worldwide. www.zeta-inst.com