Tag Archives: letter-ap-tech

Light and electrons interact in a complex dance within fiber optic devices. A new study by University of Illinois engineers found that in the transistor laser, a device for next-generation high-speed computing, the light and electrons spur one another on to faster switching speeds than any devices available.

Milton Feng, the Nick Holonyak Jr. Emeritus Chair in electrical and computer engineering, found the speed-stimulating effects with graduate students Junyi Qiu and Curtis Wang and Holonyak, the Bardeen Emeritus Chair in electrical and computer engineering and physics. The team published its results in the Journal of Applied Physics.

As big data become bigger and cloud computing becomes more commonplace, the infrastructure for transferring the ever-increasing amounts of data needs to speed up, Feng said. Traditional technologies used for fiber optic cables and high-speed data transmission, such as diode lasers, are reaching the upper end of their switching speeds, Feng said.

“You can compute all you want in a data center. However, you need to take that data in and out of the system for the user to use,” Feng said. “You need to transfer the information for it to be useful, and that goes through these fiber optic interconnects. But there is a fundamental switching limitation of the diode laser used. This technology, the transistor laser, is the next-generation technology, and could be a hundred times faster.”

Diode lasers have two ports: an electrical input and a light output. By contrast, the transistor laser has three ports: an electrical input, and both electrical and light outputs.

The three-port design allows the researchers to harness the intricate physics between electrons and light. For example, the fastest way for current to switch in a semiconductor material is for the electrons to jump between bands in the material in a process called tunneling. Light photons help shuttle the electrons across, a process called photon-assisted tunneling, making the device much faster.

In the latest study, Feng’s group found that not only does photon-assisted tunneling occur in the transistor laser, but that it in turn stimulates the photon absorption process within the laser cavity, making the optical switching in the device even faster and allowing for ultra-high-speed signal modulation.

“The collector can absorb the photon from the laser for very quick tunneling, so that becomes a direct-voltage-modulation scheme, much faster than using current modulation,” Feng said. “We also proved that the stimulated photon-assisted tunneling process is much faster than regular photon-assisted tunneling. Previous engineers could not find this because they did not have the transistor laser. With just a diode laser, you cannot discover this.

“This is not only proving the scientific point, but it’s very useful for high-speed device modulation. We can directly modulate the laser into the femtosecond range. That allows a tremendous amount of energy-efficient data transfer,” Feng said.

The researchers plan to continue to develop the transistor laser and explore its unique physics while also forming industry partnerships to commercialize the technology for energy-efficient big data transfer.

Mentor Graphics Corp. ushered in a new era of emulation by announcing new applications for the Veloce emulation platform. The new Veloce Apps—Veloce Deterministic ICE, Veloce DFT and Veloce FastPath—overcome critical system-level verification challenges in complex SoC and system designs. They run on an upgraded Veloce OS3 operating system that significantly accelerates design compile cycles, gate-level flows, and the time it takes to review results (“time to visibility”). The combination of Veloce Apps on Veloce OS3 puts more capabilities into the hands of more engineers more quickly than hardware-centric strategies.

Each of the new Veloce Apps addresses a specific verification issue:

  • Veloce Deterministic ICE overcomes unpredictability in In-circuit Emulation (ICE) environments by adding 100% visibility and repeatability for debug, and provides access to other ‘virtual-based’ use models;
  • Veloce DFT accelerates Design for Test (DFT) verification prior to tape-out to
    minimize the risk of catastrophic failure, and significantly reduces run times when verifying designs after DFT insertion; and
  • Veloce FastPath optimizes emulation performance when verifying large multi- clock SoC designs by enabling faster model execution speed.

These new Veloce Apps join Veloce Power, Veloce Enterprise Server and other apps in an expanding arsenal of software innovations for the Veloce emulation platform. Mentor will continue to expand the library of Veloce Apps to introduce new ways to ensure designs meet their functional and performance specifications on schedule.

The new Veloce Deterministic ICE, Veloce DFT and Veloce FastPath applications expand the Veloce Apps library to put more emulation capabilities the hands of more engineers.

The new Veloce Deterministic ICE, Veloce DFT and Veloce FastPath applications expand the Veloce Apps library to put more emulation capabilities the hands of more engineers.

The Veloce OS operating system adds software programmability and resource management to the Veloce platform, making it easier to add new use models that increase the ROI of the emulator. The recent upgrade of Veloce OS3 covers several innovations:

  • Integration of new High Performance Computing platforms cuts compile time by 50%.
  • A faster gate-level flow operates as “plug-and-play”—able to accept flat or hierarchical designs. This flow reduces the amount of memory needed for compilation, which improves performance. By making it easier to load and verify gate-level designs, the new flow improves confidence in silicon fidelity.
  • The combination of software and hardware improvements spanning the run time and debug cycles achieves 200% faster time-to-visibility.

These new Veloce emulation capabilities demonstrate how innovative software, running on powerful, qualified hardware and an extensible operating system, can target design risks faster than hardware-centric strategies. As emulation enters its fourth decade and expands across mainstream markets, the Veloce emulation platform has become a powerful resource across a range of hardware, software and system verification flows.

“Mentor continues to demonstrate its technology leadership through its application-based strategy for the Veloce emulation platform,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “These latest innovations accelerate overall verification throughput performance for our customers. The focus on software apps for specific SoC and system-level challenges is driving the future of emulation.”

About the Veloce emulation platform

The Veloce emulation platform is a core technology in the Mentor Enterprise Verification Platform (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform.

Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system- level prototyping, low-power verification and power estimation and performance characterization.

SEMI today announced the “Call for Papers” for technical sessions and presentations for SEMICON Europa 2016 which takes place 25-27 October in Grenoble, France.

SEMICON Europa 2016 will feature more than 100 hours of technical sessions and presentations focused on critical industry topics that are shaping the design and manufacturing of semiconductors, MEMS, printed and flexible electronics, and other related technologies.  Abstracts for presentations are now being accepted for:

  • Advanced Packaging Conference: “The Balancing Act between Consumer and Harsh Environment Packaging”
  • Power Electronics Conference: “The Power Awakens”
  • 2016FLEX Europe: “Silicon Electronics + Flexible Systems Enabling New Markets”

The SEMICON Europa 2016 abstract submission deadline is 29 April.  Prospective presenters are invited to submit abstracts (1,000-2,000 characters). Material must be original, non-commercial and non-published. Abstracts must clearly detail the nature, scope, content, organization, key points, and significance of the proposed presentation.  Visit www.semiconeuropa.org or contact Christina Fritsch, SEMI Europe, at Tel: +49 30 303080770 or email [email protected].

Co-located and leveraging SEMICON Europa 2016, 2016FLEX Europe(formerly known as PE Europe)will also take place in Grenoble from 25-27 October.

SEMICON Europa and 2016FLEX Europe (now powered by SEMI’s Strategic Association Partner FlexTech) will attract over 5,500 attendees involved in the microelectronics supply chain, from equipment and material suppliers, IC manufacturers, system integrators to end users. Special programs this year focus on advanced and smart manufacturing (Industry 4.0), power electronics, imaging, electronics and materials for the medical and automotive applications, creating an opportunity to explore applications and manufacturing solutions for flexible, printed and hybrid electronics.

Cadence Design Systems, Inc. today announced that the Cadence Innovus Implementation System has been qualified for Samsung Foundry’s latest 10-nanometer (10nm) process. The Innovus Implementation System is a next-generation physical implementation tool with integrated signoff engines that have been validated for Samsung designs, providing customers with the fastest path to implementation and closure and optimal power, performance and area (PPA).

The Innovus Implementation System offers customers key technologies for using the Samsung 10nm process including the GigaPlace solver-based placement technology, a slack-driven, pin access-aware placer that improves electrical and physical design convergence at advanced nodes. The tool also offers integration with the Cadence Quantus QRC Extraction Solution, the Tempus Timing Signoff Solution, the Voltus Power Integrity Solution and the Physical Verification System, all of which enable design convergence for faster design closure. The Innovus Implementation System incorporates a massively parallel architecture that increases capacity and drives better turnaround time without compromising PPA.

“We have collaborated with Samsung to enable customers to deploy production flows on 10nm FinFET designs in order to achieve the best PPA and overcome design complexity to meet aggressive time-to-market demands,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “We are actively working with customers on new designs on the Samsung 10nm process using the Innovus Implementation System, and we are seeing early successes that can enable these designers to stay in front of the competition.”

Engineering material magic


February 15, 2016

University of Utah engineers have discovered a new kind of 2D semiconducting material for electronics that opens the door for much speedier computers and smartphones that also consume a lot less power.

The semiconductor, made of the elements tin and oxygen, or tin monoxide (SnO), is a layer of 2D material only one atom thick, allowing electrical charges to move through it much faster than conventional 3D materials such as silicon. This material could be used in transistors, the lifeblood of all electronic devices such as computer processors and graphics processors in desktop computers and mobile devices. The material was discovered by a team led by University of Utah materials science and engineering associate professor Ashutosh Tiwari. A paper describing the research was published online Monday, Feb. 15, 2016 in the journal, Advanced Electronic Materials. The paper, which also will be the cover story on the printed version of the journal, was co-authored by University of Utah materials science and engineering doctoral students K. J. Saji and Kun Tian, and Michael Snure of the Wright-Patterson Air Force Research Lab near Dayton, Ohio.

University of Utah materials science and engineering associate professor Ashutosh Tiwari holds up a substrate layered with a newly discovered 2-D material made of tin and oxygen. Tiwari and his team have discovered this new material, tin monoxide, which allows electrical charges to move through it much faster than common 3-D material such as silicon. This breakthrough in semiconductor material could lead to much faster computers and mobile devices such as smartphones that also run on less power and with less heat. Credit: Dan Hixson/University of Utah College of Engineering

University of Utah materials science and engineering associate professor Ashutosh Tiwari holds up a substrate layered with a newly discovered 2-D material made of tin and oxygen. Tiwari and his team have discovered this new material, tin monoxide, which allows electrical charges to move through it much faster than common 3-D material such as silicon. This breakthrough in semiconductor material could lead to much faster computers and mobile devices such as smartphones that also run on less power and with less heat. Credit: Dan Hixson/University of Utah College of Engineering

Transistors and other components used in electronic devices are currently made of 3D materials such as silicon and consist of multiple layers on a glass substrate. But the downside to 3D materials is that electrons bounce around inside the layers in all directions.

The benefit of 2D materials, which is an exciting new research field that has opened up only about five years ago, is that the material is made of one layer the thickness of just one or two atoms. Consequently, the electrons “can only move in one layer so it’s much faster,” says Tiwari.

While researchers in this field have recently discovered new types of 2D material such as graphene, molybdenun disulfide and borophene, they have been materials that only allow the movement of N-type, or negative, electrons. In order to create an electronic device, however, you need semiconductor material that allows the movement of both negative electrons and positive charges known as “holes.” The tin monoxide material discovered by Tiwari and his team is the first stable P-type 2D semiconductor material ever in existence.

“Now we have everything — we have P-type 2D semiconductors and N-type 2D semiconductors,” he says. “Now things will move forward much more quickly.”

Now that Tiwari and his team have discovered this new 2D material, it can lead to the manufacturing of transistors that are even smaller and faster than those in use today. A computer processor is comprised of billions of transistors, and the more transistors packed into a single chip, the more powerful the processor can become.

Transistors made with Tiwari’s semiconducting material could lead to computers and smartphones that are more than 100 times faster than regular devices. And because the electrons move through one layer instead of bouncing around in a 3D material, there will be less friction, meaning the processors will not get as hot as normal computer chips. They also will require much less power to run, a boon for mobile electronics that have to run on battery power. Tiwari says this could be especially important for medical devices such as electronic implants that will run longer on a single battery charge.

“The field is very hot right now, and people are very interested in it,” Tiwari says. “So in two or three years we should see at least some prototype device.”

Human and animal movements generate slight neural signals from their brain cells. These signals obtained using a neural interface are essential for realizing brain-machine interfaces (BMI). Such neural recording systems using wires to connect the implanted device to an external device can cause infections through the opening in the skull. One method of solving this issue is to develop a wireless neural interface that is fully implantable on the brain.

However, the neural interface implanted on the brain surface should be of small size and minimally invasive. Furthermore, it requires the integration of a power source, antenna for wireless communication, and many functional circuits.

Now, a research team at the Department of Electrical and Electronic Information Engineering at Toyohashi University of Technology has developed a wafer-level packaging technique to integrate a silicon large-scale integration (LSI) chip in a very thin film of a thickness 10 μm. The approach is realized using flip-chip bonding. The researchers have fabricated a wireless power transmission (WPT) device including a flexible antenna and rectifier chip by using the proposed method.

The first author PhD candidate Kenji Okabe said, “We have investigated how to integrate flexible antenna and high-performance circuits and tried this fabrication method with process conditions obtained through experiments.” Assistant Professor Ippei Akita, who is leading the project, said, “Using flexible device technology is a good solution to implement bio-compatible passive devices such as antennas or sensor electrodes. On the other hand, silicon-based integrated circuit technology, which has long history, is suitable for ultra-low-power systems with many functionalities. So, we believe that combining these technologies is essential to establish such minimum invasive implantable devices.”

The fabricated device is of size 27 mm × 5 mm, and 97% of the device area is composed of a flexible film as the silicon chip has a small area. Therefore, it has sufficient flexibility to fit the shape of the brain surface. In addition, the researchers achieved WPT to the device immersed in saline.

This WPT device can supply electricity to other circuits included in the neural interface. The researchers are trying to integrate more functions (e.g., amplifiers, analog-to-digital converters, signal processors, and radio frequency circuits) to an LSI chip. This study may contribute to the development of safer BMI systems.

Making tiny switches do enormous jobs in a more efficient way than current technology allows is one of the goals of a research team led by Cornell engineering professor Huili (Grace) Xing.

Xing and her group – which includes her husband, Debdeep Jena, also an engineering professor at Cornell – have created gallium nitride (GaN) power diodes capable of serving as the building blocks for future GaN power switches. The group built a GaN power-switching device, approximately one-fifth the width of a human hair, that could support 2,000 volts of electricity.

With silicon-based semiconductors rapidly approaching their performance limits in electronics, GaN is seen as the next generation in power control and conversion. Applications span nearly all electronics products and electricity distribution infrastructure.

“With some of these new materials, it’s actually conceivable now to shrink medium-scale power-distribution systems onto a chip,” Jena said. “Looking into the future, this is one of the goals, and it’s not a moonshot. It’s possible, but the materials have to be right, the design has to be right.”

The team’s work was published Dec. 15 in the journal Applied Physics Letters, a publication of the American Institute of Physics. The group includes researchers from Cornell, the University of Notre Dame – from where Xing and Jena arrived at Cornell last year – and the semiconductor company IQE.

Xing said the key to her team’s discovery was building the device on a GaN base layer that contained relatively few energy-sapping defects, in comparison to traditional silicon-based substrates.

“We’re going to take the defects, some of them anyway, out of the equation,” said Xing, the Richard Lundquist Sesquicentennial Professor of Electrical and Computer Engineering and a professor of materials science and engineering. “Nothing can be 100 percent [free of defects], but we’re talking about improvements along an order of magnitude of up to 10,000 times.”

The team used a couple of indicators to determine the defect level in the GaN diode, including “diode ideality factor” as measured by the Shockley-Read-Hall recombination lifetime. The SRH lifetime is the average time it takes positively and negatively charged particles to move around before recombining at defects, which creates inefficiency.

The team’s work yielded near-ideal performance in all aspects, spawning hope for the future of GaN power diodes.

“Our results are an important step toward understanding the intrinsic properties and the true potential of GaN,” said Zongyang Hu, a Cornell postdoctoral associate and the paper’s co-lead author.

While much of energy-related research and development is focused on alternative energy sources, such as wind and solar, the Xing team’s efforts in power transmission are just as important, Jena said.

“Power generation gets a lot of press, and it should,” he said. “But once the power is generated, the amount of power that is lost because of inefficiencies is mind-bogglingly large. This problem is about conservation rather than generating power, which is really the same thing.

“And the scale of losses today actually far surpasses the total of renewable energies combined,” he said. “And it’s a clear and present solution; it’s not like we have to discover something fundamental.”

The team’s work is supported in part by the U.S. Department of Energy’s Advanced Research Projects Agency-Energy (ARPA-E) “SWITCHES” program. SWITCHES stands for Strategies for Wide Bandgap, Inexpensive Transistors for Controlling High-Efficiency Systems.

“Leading one of these projects, we at Cornell – in collaboration with our industrial partners – have established an integrated plan to develop three terminal GaN power transistors, package them, and insert them into circuits and products,” Xing said.

The team’s paper is titled “Near unity ideality factor and Shockley-Read-Hall lifetime in GaN-on-GaN p-n diodes with avalanche breakdown.” Cornell collaborators included Kazuki Nomoto and Vladimir Protasenko, research associates in the School of Electrical and Computer Engineering, and graduate students Bo Song and Mingda Zhu. The team also included Jena’s Ph.D. student Meng Qi at the University of Notre Dame, and engineers Ming Pan and Xiang Gao of IQE.

Cypress Semiconductor Corp., today announced the addition of wafer products to its industry-leading nonvolatile random access memory (NVRAM) portfolio. Cypress’s NVRAM portfolio, which includes Ferroelectric-RAM (F-RAM) and nonvolatile static RAM (nvSRAM) devices, offers reliable protection of critical data during a power failure. Many mission-critical applications that require the unique benefits of F-RAM and nvSRAM also require bare die for small or unique packaging options.

Cypress F-RAM is the most energy-efficient NVRAM technology in the industry with a virtually unlimited 100 trillion write cycle endurance. The ferroelectric material in F-RAM memory cells is highly resistant to data corruption caused by radiation or magnetic field exposure, providing soft error rate immunity for medical, aerospace and defense applications. Cypress nvSRAM is the fastest NVRAM technology in the industry, with access times as low as 20 ns. It provides nonvolatile data retention without the need for additional batteries and also provides unlimited endurance.

“Enabling wafer sales for our NVRAM portfolio allows us to address a wider range of customer needs,” says Sonal Chandrasekharan, Senior Business Unit Director of the Nonvolatile Products Business Unit at Cypress. “Customers can now take advantage of the high performance of nvSRAM or energy efficiency of F-RAM in the exact form factor they require for a specific application.”

By Arnaud Furnemont, Department Director Memory at imec

Research in memory is really exciting these days: in parallel you have the scaling of classical memories (SRAM, DRAM, Flash) and the emergence of new memories capable of enabling new applications or even new system hierarchies. At imec, we mostly focus on three concepts which all come with different challenges.

First is Flash, and specifically 3D NAND. Here it’s the integration challenge that is keeping us all busy. Before, the focus was on device scaling, but now it’s all about stacking more layers. Last year, we explored new materials for the channel (e.g. III-V channel in 3D NAND) and for the trapping layer (YAlO instead of SiN), in parallel with device reliability characterization and modelling.

Another important memory type is STT-MRAM where a complex magnetic stack makes the scene. Focus here is on choosing the right material combination and developing the perfect stack (with perfect interfaces!). Over the last years, imec made a lot of progress to build a good stack. But even more challenging is the patterning of this multi-layers structure without affecting the magnetic properties of the device. Very recently we were able to demonstrate 45nm devices with good performance. Tool suppliers are improving the etch platforms and I expect STT-MRAM as embedded memory in the foundries by 2017 and as standalone memory by 2020. In the latter case, more scaling is necessary and this implies more etch issues which will have to be solved.

Thirdly, we explore resistive RAM. The challenge for this type of memory is picking the right combination out of the numerous kinds of stacks and materials. And to do this, you need a fundamental understanding of what happens inside each stack. Imec has developed in depth characterization and modelling on OxRAM and CBRAM memories, expected to be used in embedded applications. Globally, RRAM suffers from a trade-off between write energy and stability. VMCO is another RRAM variant developed at imec to break this trade-off. To be competitive in standalone applications, RRAM will also need to be combined with a selector, which requires again material selection and benchmarking. This is a role that imec is willing to take on for its partners.

Finally, there is also a high-level challenge that the memory researchers and developers are facing. It’s the changing landscape in which emerging memories have more and more impact on the system architecture. Before, the system hierarchy was built with the memory technologies that were available. In the future it might be the other way around: the system architects will tell us what to develop. A closer collaboration between the device team and system architects is therefore indispensable. Imec’s memory ‘insite’ activity will tackle this challenge. 

After a master in electro-mechanics, Arnaud Furnémont completed his PhD at IMEC, focusing on characterization of nitride-based memory such as NROM and TANOS. In 2008, he joined Intel in Boise (Idaho) and became responsible for 20nm planar Flash reliability, and later for an emerging memory concept. In 2013 he joined IMEC as memory characterization and integration teams manager. Since end of 2014, Arnaud serves as memory department director, MRAM and Flash program director at imec.

The IEEE Photonics Society will hold the fifth annual Optical Interconnects Conference on 9 – 11 May 2016 at the Hyatt Regency Mission Bay Spa & Marina in San Diego, CA.

Established as the Workshop on Interconnections within High Speed Digital Systems more than 25 years ago, the conference is designed to facilitate collaboration between the optical industry’s leading engineers and researchers to bring new optical interconnect architectures and technologies from research lab concepts to commercial realities, covering the complete spectrum of high performance interconnect technologies, from on-chip interconnects to enterprise-wide communications networks.

The conference program will cover the latest innovations in a wide range of interconnect challenges, including network systems, subsystems, architectures, applications and devices, delivered in more than 80 technical presentations that combine invited talks with refereed papers and poster sessions. A special evening panel session will be held on Monday evening to enable attendees to engage with expert panelists from industry and academia to exchange ideas about the future for optical interconnect technology.

“Optical interconnect strategies can only be fully realized when optimized at the system level,” said Lukas Chrostowski, University of British Columbia and Samuel Palermo, Texas A&M University, OI Conference 2016 General Co-Chairs. “This year’s Optical Interconnects Conference promises to be an important step in the exploration of the interconnect potential for future petascale and exascale platforms in supercomputers and datacenters.”

Papers will be accepted immediately, and the paper submission deadline is 24 January 2016. Authors will be notified in March of their paper status. Accepted papers are published on the IEEE Xplore digital library shortly after the conference, providing worldwide exposure for all authors.  The complete Call for Papers can be found at http://www.oi-ieee.org/call-for-papers.