Tag Archives: letter-ap-tech

By Ed Korczynski

As the commercial IC fabrication industry continues to shrink field-effect transistor (FET) sizes, 2D planar structures evolved into 3D fins which are now evolving into 3D stacks of 2D nano-sheets. While some researchers continue to work on integrating non-silicon “alternate channel” materials into finFETs for next generation logic ICs, published results from labs around the world now show that nano-wires or nano-sheets of silicon will likely follow silicon finFETs in high-volume manufacturing (HVM) fabs. 

Today’s finFETs are formed using self-aligned multi-patterning (SAMP) process flows with argon-fluoride immersion (ArFi) deep ultra-violet (DUV) steppers to provide arrays of equal-width lines. A block-mask can then pattern sets of lines into different numbers of fins per transistor to allow for different maximum current flows across the chip. When considering the next CMOS device structure to replace finFETs in commercial HVM we must anticipate the need to retain different current flows (ION) across the IC.

Gate-all-around (GAA) FETs can provide outstanding ION/IOFFratios, and future logic ICs could be built using either horizontal or vertical GAA devices. While vertical-GAA transistors have been explored for memory chips, their manufacturing process flows are significantly different from  those used to form finFETs. In contrast, horizontal-GAA FETs processing can be seen as a logical extension of flows already developed and refined for fin structuring.

“With a number of scaling boosters, the industry will be able to extend finFET technology to the 7 or even 5nm node,” said An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the finFET process steps.”

The figure shows simplified cross-sections of a finFET with fin height (FH) of 50 nm along with two different stacks of lateral nano-sheets (LNS, also known as horizontal nano-sheets or HNS), where the current flows would be normal to the cross-section. HNS are variations of horizontal nano-wires (HNW) with the wires widened, shown as 11nm and 21nm in the figure. The HNS are epitaxial-silicon grown separated by sacrificial sacrificial silicon-germanium (SiGe) spacer layers.

Cross-sectional schematics of idealized (left) 50nm high finFET, (center) 5nm high by 11nm wide lateral-nano-sheets at 12-18nm vertical pitch, and (right) lateral-nano-sheets 21nm wide. (Source: imec)

In an exclusive interview with Solid State Technology, Steegen discussed a few details of the process extensions needed to convert finFETs into HNS-FETs. The same work-function ALD metals can be used to tune threshold voltages such that one epi-stack process can grow silicon for both n-type and p-type FETs. Happily, no new epitaxial reactors nor precursor materials are needed. Isotropic etch of the SiGe vertical spacers, and then filling the spaces with a dielectric deposition may be the only new unit-processes needed.

Alternate channel wires and sheets

At the 2018 Symposia on VLSI Technology and Circuits, imec presented two papers on germanium as an alternate channel material for nanowire pFET devices. In the first paper they studied the electrical properties of strained germanium nanowire pFETs as high-end analog and high-performance digital solutions. The second paper demonstrated vertically-stacked GAA highly-strained germanium nanowire pFETs.

The commercial IC fab industry has considered use of alternate channels for planar devices and for finFETs, yet so far has found extensions of silicon to work well-enough for pFETs. Likewise, the first generation of HNS will likely use silicon channels for both nFETs and pFETs. Germanium GAA pFETs thus represent the ability to shrink HNS devices for future nodes.

Toshiba Electronic Devices & Storage Corporation (“Toshiba”) announces the launch of a new analog output IC photocoupler that enables high-speed communications in automotive applications – especially electric vehicles (EV) and hybrid electric vehicles (HEV).

The new TLX9309 consists of a high-output GaAlAs light emitting diode (LED) that is optically coupled to a high-speed detector. The detector consists of a photodiode and a transistor integrated onto a single chip. A Faraday shield has been integrated onto the photodetector chip to provide enhanced levels of common-mode transient immunity – typically up to 15kV/μs, an important parameter in electrically noisy automotive environments.

By separating the photodiode and amplification transistor, the collector capacitance is reduced, reducing propagation delays and making the open-collector TLX9309 faster than transistor output devices. In fact, propagation delay times are guaranteed to be between 0.1μs and 1.0μs, with the difference between high to low and low to high transition (|tpLH-tpHL|) being no more than 0.7μs, making the device suitable for high-speed communications such as inverter control or as an interface to intelligent power modules (IPM).

Electrically, the device offers 3750Vrms of isolation with 5.0mm of creepage and clearance for safety isolation. It operates from a supply in the range -0.5 to 30V DC and can drive up to 25mA at output voltages up to 20V. The current transfer ratio is in the range 15-300%.

The TLX9309 is packaged in a 3.7mm x 7.0mm x 2.2mm RoHS compliant 5-pin SO6 package and operates over the temperature range -40°C to +125°C. The device is AEC-Q101 qualified for use in automotive applications.

The TLX9309 is now in mass production.

ROHM today announced the availability of a CMOS op-amp featuring the lowest noise in the industry optimized for industrial applications requiring high-accuracy sensing, such as accelerometers used in sonar systems, and optical sensors that handle ultra-small signals.

In recent years, in addition to IoT devices, sensors are being adopted in a variety of applications from portables and vehicle systems to industrial equipment, to improve functionality and provide advanced control. Used to detect and convert various environmental and physical changes into signals, sensors demand high accuracy, but at the same time peripheral sensor circuitry is trending towards lower voltages to achieve greater power savings.

Op-amps are configured at the rear stage to amplify the analog sensor output, but because sensor signals are so weak it is necessary to implement noise countermeasures to ensure high-accuracy transmission. In response, ROHM developed a high noise tolerant op-amp for the automotive market utilizing a vertically integrated production system that leverages original analog design technologies and processes. ROHM has introduced an op-amp that delivers the industry’s best performance against external noise optimized for consumer devices and industrial equipment.

The LMR1802G-LB, developed utilizing ROHM’s analog technology covering circuit design, processes, and layout, reduces input equivalent noise voltage density by half (2.9nV/√Hz at 1kHz, 7.8nV/√Hz at 10Hz) compared to conventional products, significantly improving the detection performance of sensor signals. In addition, best-in-class phase margin (68°) and capacitive load tolerance (500pF) provide excellent stability (difficult to oscillate, easy to handle). This enables accurate amplification of voltages in the order of µV, ensuring support for industrial and consumer applications requiring high-precision sensing.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the new SmartView® NT3 aligner, which is available on the company’s industry benchmark GEMINI® FB XT integrated fusion bonding system for high-volume manufacturing (HVM) applications. Developed specifically for fusion and hybrid wafer bonding, the SmartView NT3 aligner provides sub-50-nm wafer-to-wafer alignment accuracy — a 2-3X improvement — as well as significantly higher throughput (up to 20 wafers per hour) compared to the previous-generation platform.

With the new SmartView NT3 aligner, the GEMINI FB XT provides integrated device manufacturers, foundries and outsourced semiconductor assembly and test providers (OSATs) with wafer bonding performance that is unmatched in the industry and can meet their future 3D-IC packaging requirements. Applications enabled by the enhanced GEMINI FB XT include memory stacking, 3D systems on chip (SoC), backside illuminated CMOS image sensor stacking, and die partitioning.

The new SmartView® NT3 aligner on EV Group’s GEMINI® FB XT fusion bonder enables a 2-3X improvement in wafer-to-wafer alignment accuracy over EVG’s previous-generation aligner.

Wafer Bonding an Enabling Process for 3D Device Stacking

Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices. The constant reduction in pitches that are needed to support component roadmaps is fueling tighter wafer-to-wafer bonding specifications with each new product generation.

“At imec, we believe in the power of 3D technology to create new opportunities and possibilities for the semiconductor industry, and we are devoting a great deal of energy into improving it,” stated Eric Beyne, imec fellow and program director 3D system integration. “One area of particular focus is wafer-to-wafer bonding, where we are achieving excellent results in part through our work with industry partners such as EV Group. Last year, we succeeded in reducing the distance between the chip connections, or pitch, in hybrid wafer-to-wafer bonding to 1.4 microns, which is four times smaller than the current standard pitch in the industry. This year we are working to reduce the pitch by at least half again.”

“EVG’s GEMINI FB XT fusion bonding system has consistently led the industry in not only meeting but exceeding performance requirements for advanced packaging applications, with key overlay accuracy milestones achieved with several industry partners within the last year alone,” stated Paul Lindner, executive technology director, EV Group. “With the new SmartView NT3 aligner specifically engineered for the direct bonding market and added to our widely adopted GEMINI FB XT fusion bonder, EVG once again redefines what is possible in wafer bonding — helping the industry to continue to push the envelope in enabling stacked devices with increasing density and performance, lower power consumption and smaller footprint.”

The GEMINI FB XT fusion bonder with new SmartView NT3 aligner is available for customer demonstrations and testing. More information on the product can be found on EVG’s website at https://www.evgroup.com/en/products/bonding/integrated_bonding/geminifb/.

EVG will showcase the GEMINI FB XT with new SmartView NT3 aligner, along with its complete suite of wafer bonding, lithography and resist processing solutions for advanced packaging applications, at SEMICON West, to be held July 10-12 at the Moscone Convention Center in San Francisco, Calif. Attendees interested in learning more can visit EVG at Booth #623 in the South Hall.

In addition, Dr. Thomas Uhrmann, director of business development at EV Group, will highlight the GEMINI FB XT and other developments in wafer bonding in his presentation “Collective Bonding for Heterogeneous Integration in Advanced Packaging” at the Meet the Experts Theater Smart Manufacturing Pavilion at SEMICON West on Thursday, July 12 from 3:00-3:30 p.m. in the South Hall.

Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung Electronics Co., Ltd. has certified the Synopsys Custom Design Platform for Samsung Foundry’s 7-nanometer (nm) Low Power Plus (LPP) process Samsung Foundry’s 7LPP is its first semiconductor process technology to use extreme ultraviolet (EUV) lithography, a process technology that greatly reduces complexity and offers significantly better yield and fast turnaround time when compared to its 10-nanometer (10nm) FinFET predecessors. Synopsys custom design tools have been updated to support Samsung Foundry’s 7LPP requirements. In addition, a Synopsys-ready process design kit (PDK) and custom design reference flow are available from Samsung Foundry.

The Synopsys Custom Design Platform has been certified for Samsung Foundry’s 7LPP process technology. The platform is centered around the Custom Compiler custom design and layout environment, and includes HSPICE, FineSim SPICE and CustomSim FastSPICE circuit simulation, StarRC parasitic extraction, and IC Validator physical verification. To support efficient 7LPP custom design, Synopsys and Samsung Foundry have collaborated to develop a reference flow that includes a set of tutorials illustrating key requirements of 7-nm design and layout. These tutorials include sample design data and step-by-step instructions for performing typical design and layout tasks. Topics covered include electrical rule checking, circuit simulation, mixed-signal simulation, Monte Carlo analysis, layout, parasitic analysis, and electromigration.

To achieve certification from Samsung Foundry, Synopsys tools have been optimized to support the demanding requirements of 7-nm design, including:

  • Accurate FinFET device modeling with device aging effect
  • Advanced Monte Carlo simulation features to enable efficient analysis
  • High-performance transient noise simulation for analog and RF designs
  • High-performance post-layout simulation to enable parasitic-aware design and simulation
  • Dynamic circuit ERC for device voltage checks
  • High-performance transistor-level EM/IR analysis to minimize over-design
  • Efficient symbolic editing of FinFET device arrays
  • EUV support
  • Coverage-based via resistance extraction

“Our custom design collaboration with Synopsys has expanded substantially over the past two years,” said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. “With this latest effort, we have added Synopsys Custom Design Platform support for our 7LPP process, including a custom design reference flow based on Synopsys tools.”

“We’ve been collaborating closely with Samsung Foundry to simplify custom design using FinFET process technology,” said Bijan Kiani, vice president of product marketing at Synopsys. “Together we have delivered certified tools, a reference flow, a PDK, simulation models, and runsets to enable Samsung customers to achieve robust custom designs on the 7LPP process.”

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology, will present a process flow for a complementary FET (CFET) device for nodes beyond N3. The proposed CFET can eventually outperform FinFETs and meet the N3 requirements for power and performance. It offers a potential area scaling of both standard cells (SDC) and memory SRAM cells by 50%.

The CFET is a further evolution of the vertically stacked gate all around nanowire transistor. Instead of stacking either n-type or p-type devices, it stacks both on top of each other. Imec’s proposed flow consists of stacking an n-type vertical sheet on a p-type fin. This choice exploits the FinFET process flow and benefits from the potential for strain engineering in the bottom pFET. Based on TCAD analysis, the proposed CFET can meet the N3 targets for power and performance, where it will outperform FinFETs. However, the dominant parasitic resistance of the deep vias needs to be reduced. This can be achieved by introducing advanced Middle of Line (MOL) contacts using e.g. ruthenium.

A design-technology co-optimization (DTCO) analysis reveals that the CFET device used in either an SDC or SRAM cell has the potential of 50% area reduction. The SDC area is mostly driven by accessing the transistor terminals. Consequently, the area gain using CFETs will not lie in the reduction of the active footprint, but rather in the considerable simplification of the transistor terminal access. By fully benefiting from the CFET architecture, it is possible to reduce the SDC to three routing tracks whereas the most advanced FinFET libraries today need six. For SRAM cells, the same area reduction is possible thanks to a new cross-coupling scheme that allows us to scale the cell height from T6 to T4.

“Given its excellent characteristics and scaling potential, the CFET device is an excellent contender for the new device architecture we need for nodes beyond N3, pushing the horizon for Moore’s Law farther out,” stated Julien Ryckaert, distinguished member of the technical staff at imec.”

These results will be presented on June 21 at the VLSI Technology Symposium, in session T13: FET performance and scaling. This research is performed in cooperation with equipment companies TEL Coventor and Lam Research and with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology presented considerable progress in enabling germanium nanowire pFET devices as a practical solution to extend scaling beyond the 5nm node. In a first paper, the research center unveiled an in-depth study of the electrical properties of strained germanium nanowire pFETs. A second paper presents the first demonstration of vertically-stacked gate-all-around highly-strained germanium nanowire pFETs.

“With a number of scaling boosters, the industry will be able to extend FinFET technology to the 7- or even 5nm node,” says An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the FinFET process steps. But one important challenge of using lateral nanowires is the significant decrease of the channel cross-section compared to conventional FinFETs. To improve the drive per footprint, several nanowires have to be stacked, but this comes with a serious penalty of increased parasitic capacitance and resistance. A solution is to replace the silicon nanowires by a high-mobility channel material such as germanium (Ge), providing the necessary current boost per footprint”, adds Steegen, “These new studies show that solution is indeed feasible, reaching the cost, area and performance requirements for nodes beyond 5nm.”

The first study of high-performing strained Ge nanowire pFETs gives insight in the device performance these new devices may offer for high-end analog and high-performance digital solutions. One conclusion is that dedicated optimizations of key process steps make these devices a serious contender for the GAA technology. The second paper reports on Ge GAA FETs with single nanowires, achieving a performance that matches state-of-the-art SiGe and Ge FinFETs. Moreover, for the first time, strained p-type Ge GAA FETs with stacked nanowires were demonstrated on a 14/16nm platform. The GAA nanowire technology appears as a promising high-performance solution for future nodes, provided that the junctions are further optimized.

“These complimentary studies establish germanium GAA nanowire technology as a valid contender for the sustained scaling that will be required to fulfill the requirements for the data-driven IoT-era requiring huge computational power,” concludes Steegen.

These results will be presented on June 20 at the VLSI Technology Symposium, in session T8: Advanced FinFET and GAA. This research is performed in cooperation with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

FormFactor, Inc. (NASDAQ:FORM), a electrical test and measurement supplier to the semiconductor industry, has extended its Contact Intelligence technology. With Contact Intelligence, FormFactor’s advanced probe systems automatically and autonomously adapt in real time to changes in the testing environment, enabling customers to collect large amounts of RF data faster. As the race to bring 5G devices to market heats up, this addresses the need for higher productivity, to reduce time to market.

FormFactor’s Contact Intelligence technology combines smart hardware design and innovative software algorithms to provide accurate probe-to-pad alignment and electronic recalibrations in engineering labs and many production applications. With the introduction of its new RF solution, FormFactor now has specialized Contact Intelligence applications for RF, DC and Silicon Photonics (SiPh) testing.

FormFactor is best known for it’s probe card business, but with its acquisition of Cascade Microtech in 2016, it became more involved in the design and characterization side of chip-making, including RF and silicon photonic devices (probe cards are primarily used at the end of wafer manufacturing, testing the devices before they are packaged).

Mike Slessor, CEO of FormFactor, said with upcoming infrastructure changes — such as 5G, more mobile communications and IoT — RF is an important place to be. “The Cascade Microtech acquisition gave us an engineering systems business. These are pieces of customized capital equipment that help people very early on in their development and R&D — even early pathfinding — to figure out how their next device is going to perform, to characterize it and to improve its yield,” he said. That systems business grew saw a double digit growth rate last year.

Slessor said the new Contact Intelligence technology is designed to help customers in the systems business get a lot of data faster. He said the push to improve yield, along with new materials and new devices, is driving a tremendous amount of data collection. “What Contact Intelligence really is positioned to do is to help people easily and efficiently collect that data. You can think of it as bringing almost production automation to the engineering lab. We’re helping people do it autonomously over wide ranges of temperatures,” he said. He said it enables engineering tools to be upgraded. Customers can “set it up, push a button and walk away for 48 hours, 96 hours even more and come back and have a hundreds of thousands of individual characterization data points.”

New high frequency ICs, such as 5G (with multiple high frequency bands from sub-6 to more than 70 GHz) and automotive communication devices, need the highest quality process design kits (PDK’s) to ensure working devices at first iteration.

Traditional systems and methods require engineers to invest significant time for recalibration when the system invariably drifts, or to reposition probes with intentional changes in test temperatures. At higher frequencies, calibrations and measurements are more sensitive to probe placement errors and there is more calibration drift, so recalibration is required more often.Over time and temperature, Contact Intelligence automatically makes these adjustments with no operator intervention, resulting in more devices tested in less time, for more accurate PDK’s and faster time to market.

Slessor says the push to 5G brings many design and test challenges due to the significant increase in carrier frequencies – 10 times higher than 4G. “Although there are different bands and the carriers and the countries are still ironing out where they’re going to operate, there are bands as high as 72 gigahertz,” Slessor said. “Electrical signal propagation gets much, much more challenging as you go up in frequency. All kinds of new engineering and physics challenges emerge because you’ve got things that are radiating a good deal of power and there’s a whole bunch of cross talk on the chip. There are all kinds of interesting phenomena that appear that make the designers and the test engineer’s job much more difficult just because of these higher frequencies.”

In an RF front end, instead of modems or radios communicating, a wide variety of a BAW and SAW  filters are used to do the frequency band management and make sure that only the individual bands that are supposed to be used or being effectively used.

In addition to RF, Contact Intelligence is also designed for use in autonomous DC testing and for silicon phototonics.

In DC applications, Contact Intelligence automatically senses preset temperatures, and responds by waiting the correct amount of time until the system is stabilized. This allows lengthy test routines to be conducted over multiple temperatures without an operator present. Contact Intelligence also provides dynamic probe-to-pad alignment, even on pads as small as 25 µm, employing a combination of smart software, probe tip recognition algorithms and advanced programmable positioners.

FormFactor’s integrated SiPh solution allows sub-micron manipulation of optical fibers positioned above the wafer, automatically optimizing fiber coupling position.  Contact Intelligence uses machine vision technology to automate Theta X, Y and Z axis calibrations and alignments enabling measurements out of the box, reducing what used to take days or weeks to a matter of minutes.When combined with autonomous DC and RF, measurement options expand from Optical-Optical to include Photo-Diodes, Optical Modulators and more.

For more information, visit http://www.formfactor.com/contactintelligence.

pSemi™ Corporation (formerly known as Peregrine Semiconductor), a Murata company focused on semiconductor integration, announces the availability of the PE29101 gallium nitride (GaN) field-effect transistor (FET) driver for solid-state light detection and ranging (LiDAR) systems. The PE29101 boasts the industry’s fastest rise times and a low minimum pulse width. This high-speed driver enables design engineers to extract the full performance and switching speed advantages from GaN transistors. In solid-state LiDAR systems, faster switching translates into improved resolution and accuracy in the LiDAR image.

“As GaN is proving its relevance in applications like solid-state LiDAR, design engineers are using pSemi high-speed drivers to maximize the fast switching benefits of GaN,” says Jim Cable, chief technology officer of pSemi. “Because of its rise and fall speed, the PE29101 enables the highest possible resolution imagery—something the industry needs for LiDAR to reach its fullest potential.”

LiDAR operates on the same principles as radar but instead uses pulsed lasers to precisely map surrounding areas. Traditionally used in high-resolution mapping, LiDAR is now used in advanced-driver assistance programs (ADAS) and is widely seen as an enabling technology to fully autonomous vehicles. Furthermore, solid-state LiDAR has emerged as the future leader in the commercialization of LiDAR systems, largely due to its affordability, reliability and compact size compared to mechanical sensors.

In LiDAR systems, the pulse laser’s switching speed and rise time directly impacts the measurement’s accuracy. To improve resolution, the current must switch as quickly as possible through the laser diode. GaN technology offers LiDAR systems superior resolution and a faster response time because of its very low input capacitance and its ability to switch significantly faster than metal-oxide semiconductor field-effect transistors (MOSFETs).

GaN FETs must be controlled by a very fast driver to maximize their fast-switching potential. Increasing the switching speed requires a driver with fast rise times and a low minimum output pulse width. The PE29101 offers these key performance specifications, enabling GaN technology to improve LiDAR resolution.

Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys’ IC Validator has been certified by Samsung Foundry for signoff of all designs using its 7-nanometer (nm) Low Power Plus (LPP) process with Extreme Ultraviolet (EUV) lithography technology. The signoff-certified runsets, including design rule checking (DRC), layout-versus-schematic (LVS) and metal fill technology files, are available immediately from Samsung Foundry. Samsung Foundry 7LPP customers can now use IC Validator’s modern distributed processing in conjunction with runsets from Samsung Foundry to achieve faster physical verification turnaround time with the highest level of accuracy.

“We are building a customer-friendly design enablement ecosystem for 7LPP, our first EUV-based process technology,” said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. “Synopsys’ IC Validator is a great solution for our mutual customers to make the next generation of SoCs, which will lead the fourth industrial revolution with maximized power and performance benefit based on 7LPP process technology.”

IC Validator, a key component of the Synopsys Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (PERC), fill, and DFM enhancement capabilities. IC Validator is architected for high performance and scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than a thousand CPUs.

“Our partnership with Samsung Foundry has been focused on delivering high-quality and high-performance physical signoff solutions for today’s leading-edge designs,” said Christen Decoin, senior director of business development, Design Group at Synopsys. “This certification brings the proven benefits of IC Validator physical verification to Samsung Foundry 7LPP customers.”