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Today KLA-Tencor Corporation (NASDAQ : KLAC ) announced two new defect inspection products designed to address a wide variety of integrated circuit (IC) packaging challenges. The Kronos™ 1080 system offers production-worthy, high sensitivity wafer inspection for advanced packaging, providing key information for process control and material disposition. The ICOS™ F160 system examines packages after wafers have been diced, delivering fast, accurate die sort based on detection of key defect types—including sidewall cracks, a new defect type affecting the yield of high-end packages. The two new inspection systems join KLA-Tencor’s portfolio of defect inspection, metrology and data analysis systems that help accelerate packaging yield and increase die sort accuracy.

KLA-Tencor’s new Kronos™ 1080 wafer inspection system and ICOS™ F160 die sorting and inspection system are designed to address a wide variety of IC packaging challenges.

“As chip scaling has slowed, advances in chip packaging technology have become instrumental in driving device performance,” said Oreste Donzella, Senior Vice President and Chief Marketing Officer at KLA-Tencor. “Packaged chips need to achieve simultaneous targets for device performance, power consumption, form factor and cost for a variety of device applications. As a result, packaging design has become more diverse and complex, featuring a range of 2D and 3D structures that are more densely packed and shrinking in size with every generation. At the same time, the value of the packaged chip has grown substantially, along with electronics manufacturers’ expectations for quality and reliability. To meet these expectations, packaging manufacturers, whether in the back end of a chip manufacturing fab or in an outsourced assembly and test (OSAT) facility, have demanded more sensitive, cost-effective inspection, metrology and data analysis—and more accurate identification of bad parts. Our engineering teams have developed the new Kronos 1080 and ICOS F160 systems to serve the electronics industry’s growing needs for production-worthy defect detection for a wide variety of packaging types.”

The Kronos 1080 system is designed to inspect advanced wafer-level packaging process steps, providing information on the full range of defect types for inline process control. Advanced packaging technology necessarily includes ever-smaller features, higher-density metal patterns, and multi-layer redistribution layers—all of which have increasing inspection requirements that demand innovative solutions. The Kronos system achieves its industry-leading performance through multi-mode optics and sensors and advanced defect detection algorithms. The Kronos system also introduces FlexPoint™, an advanced technology derived from KLA-Tencor’s leading inspection solutions for IC chip manufacturing. FlexPoint focuses the inspection system on key areas within the die where defects would have highest impact. Flexible wafer handling enables the inspection of high-warp wafers, frequently encountered in a package type called fan-out wafer-level packaging—an established type for mobile applications and an emerging technology for networking and high-performance computing.

After wafer-level packages are tested and diced, the ICOS F160 performs inspection and die sorting. Manufacturers of high-end packages, such as those used for mobile applications, will benefit from new capability to detect laser-groove, hairline and sidewall cracks. These cracks result from a change in the materials used to insulate the dense on-chip metal routing to facilitate increased speed and reduced power consumption. The new material is brittle, making it susceptible to cracks during wafer dicing. Sidewall cracks are notoriously difficult to detect, as they lie perpendicular to the top of the die and are not detectable using traditional visual inspection. Another major advantage of the ICOS F160 system, beneficial to many packaging types, is its flexibility: input and output modes can be wafer, tray or tape. The system is easily changed from one configuration to another. Its automatic calibrations and precision die pickup facilitate increased tool utilization in high volume manufacturing environments.

The Kronos 1080 and ICOS F160 systems are part of KLA-Tencor’s portfolio of packaging solutions designed to address inspection, metrology, data analysis and die sorting needs for a variety of IC packaging types.

Rudolph Technologies, Inc. (NYSE: RTEC) today announced its new Dragonfly™ G2 platform, which incorporates many of the benefits of the Firefly™ system onto the Dragonfly platform, including higher sensitivity and throughput and the proprietary Clearfind™ Technology. The new system increases the options for advanced packaging customers to meet their wafer-based application challenges on a single platform. To date, customer evaluations have reported throughput increases greater than 50 percent over the first-generation Dragonfly system. The new Dragonfly G2 systems are scheduled to begin shipment in the latter part of the fourth quarter and will be highlighted at the SEMICON® Taiwan trade show September 5-7 in Rudolph’s booth N686-4F.

The Dragonfly G2 system achieves significant throughput and productivity increases using proprietary camera technology combined with stage speed and accuracy. Additionally, its modular architecture permits plug-and-play configurability of Rudolph’s technologies such as Truebump™ Technology, for more accurate bump height measurement, and Clearfind Technology, for non-visual residue detection. Streamlined software algorithms contribute to the faster throughput and enable the system to handle increasing bump counts, which have already exceeded 80 million bumps per wafer.

“Advanced packaging processes are evolving rapidly, with larger packages, shrinking features, and higher counts of smaller bumps on every wafer, and the Dragonfly G2 system is designed to meet these new challenges,” said Tim Kryman, senior director of corporate marketing at Rudolph Technologies. “At the same time, its increased throughput reduces cost-of-ownership and its configurable modular design lets one system do the work of two. Based on the positive feedback from customers’ beta testing we are expecting strong demand for this latest evolution of our technology. We expect the Dragonfly G2 system to meet our customers’ future inspection needs as increasing demands for higher quality products are driving more data with greater integrity and faster throughput to meet the growing volumes of consumer and auto electronics products.”

“An important driver for Rudolph Technologies is to increase our pace of innovation to ensure we are anticipating our customers’ roadmaps,” added Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “We were very pleased to be able to demonstrate that commitment with the release of this Dragonfly G2 system. Not only have we significantly improved throughput and imaging capability, but we have also provided the powerful Clearfind Technology to make a compelling, no compromise, advanced packaging process control system.”

The Dragonfly G2 system can be ordered now with shipments expected to begin in Q4. First-generation Dragonfly systems can be retrofitted on-site with a second-generation upgrade kit.

MRSI Systems (Mycronic Group), is expanding its high speed MRSI-HVM3 die bonder platform with the launch of the MRSI-HVM3P to offer configurations for active optical cable (AOC), gold-box packaging, and other applications in addition to chip-on-carrier (CoC).

This expansion is in response to our customer’s request to take advantage of the field-proven performance of the flexible high speed MRSI-HVM3 platform, for their other essential packaging applications in photonics manufacturing which are high volume and high mix by nature.

The new MRSI-HVM3P is the first major extension to the HVM3 family, equipped with inline conveyor for single fixture or multiple cassette inputs that can automatically transport large forms of carriers of the dies. This configuration is targeted at AOC or similar die-to-printed circuit board (PCB) applications, gold-box packaging, and CoC in fixture. The processes include eutectic, epoxy stamping, UV epoxy dispensing, and in-situ UV curing.

“With these extensions to our successful HVM3 platform, MRSI Systems is now able to offer flexible high volume die bonding solutions, not just for CoC, but also for PCB and box levels of packaging to our customers in photonics, sensors and other advanced technology fields,” said Dr. Yi Qian, Vice President of Product Management of MRSI Systems. “This is another demonstration of MRSI’s commitment to provide critical solutions promptly in response to our customers’ needs,” concluded Mr. Michael Chalsen, President of MRSI Systems.

Both MRSI-HVM3 and MRSI-HVM3P now carry the following options inherited from our long proven MRSI-M3 family:  localized heating, flip-chip bonding, and co-planarity bonding. These options are increasingly critical for new applications such as 400G transceivers and silicon photonics.

The MRSI-HVM3 product family delivers industry-leading speed, future-proof high precision (<3mm), and superior flexibility for true multi-process, multi-chip, high-volume production.

The launch of the MRSI-HVM3P builds on the success of our first configuration launched last year, the MRSI-HVM3 for CoC, Chip-on-Submount (CoS), and Chip-on-Baseplate (CoB) assembly using eutectic and/or epoxy stamping die bonding, which has proved to be the best-in-class die bonder with the leading speed, zero-time tool change between dies, and <3mm accuracy. The superior performance was enabled by dual head, dual stage, integrated “on-the-fly” tool changer, ultrafast eutectic stage, and multi-levels of parallel processing optimizations (see product launch press release August 14, 2017).

MRSI Systems is exhibiting at China International Optoelectronic Expo (CIOE) with our partner CYCAD Century Science and Technology (Booth #1C66) in Shenzhen, September 5-8, 2018 and ECOC (Booth #577) in Rome, Italy, September 24-26, 2018.

Toshiba Electronic Devices & Storage Corporation (“Toshiba”) has launched a new series of next-generation 650V power MOSFETs that are intended for use in server power supplies in data centers, solar (PV) power conditioners, uninterruptible power systems (UPS) and other industrial applications.

The first device in the DTMOS VI series is the TK040N65Z, a 650V device that supports continuous drain currents (ID) up to 57A and 228A when pulsed (IDP). The new device offers an ultra-low drain-source on-resistance RDS(ON) of 0.04Ω (0.033Ω typ.) which reduces losses in power applications. The enhancement mode device is ideal for use in modern high-speed power supplies, due to the reduced capacitance in the design.

Power supply efficiency is improved as a result of reductions in the key performance index / figure-of-merit (FoM) – RDS(ON) x Qgd. The TK040N65Z shows a 40% improvement in this important metric over the previous DTMOS IV-H device, which represents a significant gain in power supply efficiency in the region of 0.36%[1] – as measured in a 2.5kW PFC circuit.

The new device is housed in an industry-standard TO-247 package, ensuring compatibility with legacy designs as well as suitability for new projects.

Toshiba will continue to expand their product lineup to meet market trends and help improve the efficiency of power supplies and systems.

The new device enters mass production today and shipments begin immediately.

pSemi Corporation (formerly Peregrine Semiconductor), a Murata company focused on semiconductor integration, introduces the world’s first monolithic, silicon-on-insulator (SOI) Wi-Fi front-end module (FEM)—the PE561221. Ideal for Wi-Fi home gateways, routers and set-top boxes, this high-performance module uses a smart bias circuit to deliver a high linearity signal and excellent long-packet error vector magnitude (EVM) performance. The PE561221 combines the intelligent integration capabilities of pSemi’s SOI technology and Murata’s expertise in Wi-Fi connectivity solutions and advanced packaging. This 2.4 GHz Wi-Fi FEM integrates a low-noise amplifier (LNA), a power amplifier (PA) and two RF switches (SP4T, SP3T). The monolithic die uses a compact 16-pin, 2 x 2 mm LGA package ideal for either stand-alone use or in 4 x 4 MIMO and 8 x 8 MIMO modules.

“The new IEEE 802.11ax standard is utilizing high-order modulation schemes (1024 QAM) with demanding EVM requirements,” says Colin Hunt, vice president of worldwide sales at pSemi. “Traditional process technologies struggle to keep up with both performance and integration requirements, and only SOI can offer the ideal combination of integration and high performance. This new monolithic Wi-Fi module is a great example of the types of technology and product advancements pSemi and Murata can accomplish together.”

The 2.4 GHz Wi-Fi FEM is based on pSemi’s UltraCMOS® technology platform—a patented, advanced form of SOI. With its outstanding RF and microwave properties, SOI is an ideal substrate for integration. When paired with high-volume CMOS manufacturing—the most widely used semiconductor technology—the result is a reliable, repeatable technology platform that offers superior performance compared to other mixed-signal processes. UltraCMOS technology also enables intelligent integration—the unique design ability to integrate RF, digital and analog components on a single die.

Features, Packaging and Availability 

The PE561221 leverages the intelligent integration capabilities of UltraCMOS technology to deliver exceptional performance, low power consumption and high reliability with 2 kV HBM ESD rating. Through advanced analog and digital design techniques, the Wi-Fi FEM delivers excellent long-packet EVM performance with less than 0.1 dB of gain droop while operating across the entire -40°C to 85°C temperature range. At -40 dB EVM (MCS9), the output power is +19 dBm with less than 0.05 dBm droop in power output after a 4 milliseconds packet. The IC delivers best-in-class dynamic error vector magnitude (DEVM) and current consumption without requiring digital pre-distortion (DPD), and it has excellent MCS11 performance for 802.11ax applications.

Volume-production parts and samples of the PE561221 are available from pSemi. For sales information, please contact [email protected].

The PE561221 is the first product in the pSemi Wi-Fi FEM portfolio; the product roadmap includes 5 GHz Wi-Fi FEM solutions.

TDK Corporation (TSE:6762) has developed the new MPZ0603-H series of multilayer chip beads for power lines in an IEC 0603 package (EIA 0201) that feature twice the rated current and about half the DC resistance of the existing MPZ0603-C series. Thanks to a newly developed technology for the internal electrodes, TDK was able to reduce the DC resistance to as low as 36 mΩ, thus increasing the rated current to as high as 1900 mA. The MPZ0603-H series offers high impedance values ranging from 22 Ω to 120 Ω at 100 MHz. The new chip beads measure in with a miniature footprint of 0.6 mm x 0.3 mm and a low insertion height of just 0.3 mm. With their compact dimensions and excellent electrical specifications the ferrite beads are very well suited for a wide spectrum of noise suppression measures in the IC power supply lines of smartphones, audio players, PCs, and other devices. Mass production of the new series began in August 2018.

As the multifunctionality of portable devices such as smartphones continues to grow, high current ratings are becoming an increasingly important factor for components in the IC power supply lines. Thanks to their low DC resistance the MPZ0603-H chip beads not only offer a high rated current, but they also help lower the power consumption of devices.

Main applications

  • Noise suppression in the IC power supply lines in smartphones, audio players, PCs, and other devices

Main features and benefits

  • DC resistance as low as 36 mΩ approximately half that of existing products
  • Rated current as high as 1900 mA approximately twice that of existing products

In August, Toshiba Electronic Devices & Storage Corporation (“Toshiba”) will start mass production and shipments of “TPWR7904PB” and “TPW1R104PB”, 40V N-channel power MOSFETs for automotive applications. They are housed in the DSOP Advance(WF) packages that deliver double-sided cooling, low resistance, and small size.

The new products secure high heat dissipation and low On-resistance characteristics by mounting a U-MOS IX-H series chip, a MOSFET with the latest trench structure, into a DSOP Advance(WF) package. Heat generated by conduction loss is effectively dissipated, improving the flexibility of thermal design.

The U-MOS IX-H series also delivers lower switching noise than Toshiba’s previous U-MOS IV series, contributing to lower EMI[1].
The DSOP Advance(WF) package has a wettable flank terminal structure[2].

Applications
– Electric power steering
– Load switches
– Electric pumps

Features
– Qualified for AEC-Q101, suitable for automotive applications
– Double-sided cooling package with top plate[3] and drain
– Improved AOI visibility due to wettable flank structure
– U-MOS IX-H series featuring low On-resistance and low noise characteristics

Main Specifications

　(@Ta=25 ℃)

Part
number

Absolute
maximum ratings

Drain-source
On-resistance
RDS(ON) max (mΩ)

Built-in
Zener Diode
between
Gate-Source

 Series Package

Drain-
source
voltage
VDSS
(V)

Drain
current
(DC)
ID
(A)
@VGS＝6 V @VGS=10 V
TPWR7904PB 40 150 1.3 0.79 No U-MOSⅨ-H

DSOP
Advance(WF)L
TPW1R104PB 120 1.96 1.14

DSOP
Advance(WF)M

Notes:
[1] EMI (Electromagnetic interference)
[2] Wettable flank terminal structure: A terminal structure that allows AOI (Automated Optical Inspection) of installation on boards.
[3] Be aware that the top plate has the same electric potential as the sources; however, not intended for an electrode.

Toshiba Memory Corporation today announced that it has developed a prototype sample of 96-layer BiCS FLASH, its proprietary 3D flash memory, with 4-bit-per-cell (quad level cell, QLC) technology that boosts single-chip memory capacity to the highest level yet achieved.

Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September, and expects to start mass production in 2019.

The advantage of QLC technology is pushing the bit count for data per memory cell from three to four and significantly expanding capacity. The new product achieves the industry’s maximum capacity [1] of 1.33 terabits for a single chip which was jointly developed with Western Digital Corporation.

This also realizes an unparalleled capacity of 2.66 terabytes with a 16-chip stacked architecture in one package. The huge volumes of data generated by mobile terminals and the like continue to increase with the spread of SNS and progress in IoT, and the need to analyze and utilize that data in real time is expected to increase dramatically. That will require even faster than HDD, larger capacity storage and QLC products using the 96-layer process will contribute a solution.

A packaged prototype of the new device will be exhibited at the 2018 Flash Memory Summit in Santa Clara, California, USA from August 6th to 9th.

Looking to the future, Toshiba Memory will continue to improve memory capacity and performance and to develop 3D flash memories that meet diverse market needs, including the fast expanding data center storage market.

Amkor Technology, Inc. (Nasdaq: AMKR), a provider of outsourced semiconductor packaging and test (OSAT) services, today announced it has partnered with Mentor to release Amkor’s SmartPackage™ Package Assembly Design Kit (PADK), the first in the industry to support Mentor’s High-Density Advanced Packaging (HDAP) design process and tools. Amkor’s award-winning High-Density Fan Out (HDFO) process can now be used in conjunction with Mentor’s software to deliver early, rapid and accurate verification results of advanced packages required for Internet-of-Things, automotive, high-speed communications, computing and artificial intelligence applications.

“Amkor leads the way in HDFO technology for OSAT companies, and with the rise of complex ICs with multi-die packages, we prioritized the creation of Mentor-based PADKs to significantly reduce cycle time,” said Ron Huemoeller, corporate vice president, Research & Development, Amkor Technology. “Since the Mentor flow includes Calibre, the golden sign-off tool for the fabless ecosystem, our customers can easily close any physical verification issued for their entire solution.”

The complex and compact design of devices for today’s smart applications is driving the need for sophisticated packaging techniques such as heterogeneous integration and Advanced System-in-Package. These solutions combine one or more ICs of different functionality with increased I/O and circuit density in 2.5D (side-by-side) and 3D constructions. With Amkor’s SmartPackage PADK and Mentor’s proven HDAP tool flow, mutual customers of Amkor and Mentor have the ability to create and review multiple assemblies and LVS (layout vs. schematic), connectivity, geometry and component spacing scenarios using Amkor’s HDFO process. The graphic environment features robust data and is straightforward to use before and during the implementation of physical design, resulting in faster sign-off and fewer verification cycles.

“Amkor was the first OSAT company to join the Mentor OSAT Alliance program, and now the first to build and make available a PADK for its customers,” said AJ Incorvaia, vice president and general manager of Mentor’s BSD division. “By providing a fully validated PADK for Amkor’s HDFO process for Mentor’s proven HDAP tool flow, customers can more easily transition from classic chip design to 2.5 and 3D solutions.”

The OSAT Alliance program helps promote the adoption, implementation and growth of HDAP throughout the semiconductor ecosystem and design chain, enabling system and fabless semiconductor companies to have a friction-free path for emerging packaging technologies.

Australian scientists have achieved a new milestone in their approach to creating a quantum computer chip in silicon, demonstrating the ability to tune the control frequency of a qubit by engineering its atomic configuration. The work has been published in Science Advances.

A team of researchers from the Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) at UNSW Sydney have successfully implemented an atomic engineering strategy for individually addressing closely spaced spin qubits in silicon.

The frequency spectrum of an engineered molecule. The three peaks represent three different configurations of spins within the atomic nuclei, and the distance between the peaks depends on the exact distance between atoms forming the molecule. Credit: Dr. Sam Hile

The researchers built two qubits – one an engineered molecule consisting of two phosphorus atoms with a single electron, and the other a single phosphorus atom with a single electron – and placed them just 16 nanometres apart in a silicon chip.

By patterning a microwave antenna above the qubits with precision alignment, the qubits were exposed to frequencies of around 40GHz. The results showed that when changing the frequency of the signal used to control the electron spin, the single atom had a dramatically different control frequency compared to the electron spin in the molecule of two phosphorus atoms.

The UNSW researchers collaborated closely with experts at Purdue University, who used powerful computational tools to model the atomic interactions and understand how the position of the atoms impacted the control frequencies of each electron even by shifting the atoms by as little as one nanometre.

“Individually addressing each qubit when they are so close is challenging,” says UNSW Scientia Professor Michelle Simmons, Director CQC2T and co-author of the paper.

“The research confirms the ability to tune neighbouring qubits into resonance without impacting each other.”

Creating engineered phosphorus molecules with different separations between the atoms within the molecule allows for families of qubits with different control frequencies. Each molecule can be operated individually by selecting the frequency that controls its electron spin.

“We can tune into this or that molecule – a bit like tuning in to different radio stations,” says Sam Hile, lead co-author of the paper and Research Fellow at UNSW.

“It creates a built-in address which will provide significant benefits for building a silicon quantum computer.”

Tuning in and individually controlling qubits within a 2 qubit system is a precursor to demonstrating the entangled states that are necessary for a quantum computer to function and carry out complex calculations.

These results show how the team – led by Professor Simmons – have further built on their unique Australian approach of creating quantum bits from precisely positioned individual atoms in silicon.

By engineering the atomic placement of the atoms within the qubits in the silicon chip, the molecules can be created with different resonance frequencies. This means that controlling the spin of one qubit will not affect the spin of the neighbouring qubit, leading to fewer errors – an essential requirement for the development of a full-scale quantum computer.

“The ability to engineer the number of atoms within the qubits provides a way of selectively addressing one qubit from another, resulting in lower error rates even though they are so closely spaced,” says Professor Simmons.

“These results highlight the ongoing advantages of atomic qubits in silicon.”

This latest advance in spin control follows from the team’s recent research into controllable interactions between two qubits.