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The Micron Foundation (Nasdaq:MU) announced a $1 million grant for universities and nonprofit organizations to conduct research into how artificial intelligence (AI) can improve lives while ensuring safety, security and privacy. The grant was announced at the inaugural Micron Insight 2018 conference where the technology industry’s top minds gathered in San Francisco to discuss the future of AI, machine learning and data science, and how memory technology is essential in bringing intelligence to life.

“Artificial intelligence is one of the frontiers where science and engineering education can best be applied,” said Micron Foundation Executive Director Dee Mooney. “We want to accelerate advances in AI by investing in education and making sure that pioneers of this technology, reflect the diversity and richness of the world we live in and build a future where AI benefits everyone.”

Micron awarded a total of $500,000 to three initial recipients at Micron Insight 2018.

  • AI4All, a nonprofit organization, works to increase diversity and inclusion in AI education, research, development and policy. AI4All supports the next generation of diverse AI talent through its AI Summer Camp. Open to 9th-11th grade students, the camp gives special consideration to young women, underrepresented groups and families of lower socioeconomic status.
  • Berkeley Artificial Intelligence Research (BAIR) Lab supports researchers and graduate students developing fundamental advances in computer vision, machine learning, natural-language processing, planning and robotics. BAIR is based at UC Berkeley’s College of Engineering.
  • In a related announcement, the Micron Foundation launched a $1 million grant for universities and non-profit organizations to conduct research on AI. For more details, visit http://bit.ly/MicronFoundation.

The $1 million fund is available to select research universities focused on the future implications of AI in life, healthcare and business, with a portion specifically allocated to support women and underrepresented groups. The Micron Foundation supports researchers tackling some of AI’s greatest challenges – from building highly reliable software and hardware programs to finding solutions that address the business and consumer impacts of AI.

In August 2018, the Micron Foundation announced a $1 million fund for Virginia colleges and universities to advance STEM and STEM-related diversity programs in connection with Micron’s expansion of its memory production facilities in Manassas, Virginia.

Mentor, a Siemens business, today announced it has qualified complete solutions from its Calibre® nmPlatform™, Analog FastSPICE™ (AFS)™ Platform, Eldo® Platform and Nitro-SoC place and route system for GLOBALFOUNDRIES’ 22FDX Fully-Depleted Silicon-On-Insulator (FD-SOI) integrated circuit (IC) manufacturing processes. GF and Mentor have mutually developed an advanced, first-of-its-kind automated fill flow that ensures analog devices are able to leverage the full performance of these new processes in emerging markets such as ADAS/autonomous driving, IoT, 5G communications, cloud computing and artificial intelligence.

“Mentor is pleased to be taking another step in our longstanding relationship with GF to deliver to our mutual customers solutions that help develop industry innovations,” said Ravi Subramanian, vice president and general manager, IC Verification Solutions, Mentor, a Siemens business. “The combined expertise of GF and Mentor gives designers the ability to develop innovative ICs for a broad number of applications.”

“Mentor has an extremely long history of partnership with GF, as Calibre’s first customer ever,” said Richard Trihy, senior director, Design Enablement at GF. “That partnership continues today with not only additional design kit certifications, but flows that help accelerate design fill efforts at a time when market windows are increasingly shorter.”

Mentor Calibre nmPlatform for GF’s 22FDX

Mentor has made enhancements across its Calibre nmPlatform for GF’s 22FDX process. One of the most significant of these is an industry-first, automated fill flow targeting both analog and radio frequency (RF) IP blocks and full chips. The new fill flow automates a task that previously required fabless design teams to manually develop custom scripts to perform fill effectively. The new flow combines Calibre PERC™, Calibre Pattern Matching and Calibre YieldEnhancer tool capabilities to create both net-aware and orientation-aware filling that results in consistent analog and RF performance independent of where the blocks are placed in the chip.

In addition, Mentor enhanced the Calibre nmDRC™ and Calibre nmLVS™ tools for GF’s 22FDX process. Mentor worked with GF to ensure appropriate coverage, and the two companies are collaborating to continuously optimize the Calibre design kits for runtime performance. At the same time, GF and Mentor worked together to make advanced process requirements transparent to mutual customers within the Calibre design rule checking (DRC) and multi-patterning software.

The Calibre xACTTM parasitic extraction tool is available for GF’s 22FDX process, allowing customers to efficiently balance the needs of high accuracy of critical structures along with high performance required for full chip signoff.

The Calibre PERC reliability platform is a verification solution for both IP and full-chip reliability analysis. Point-to-point and ESD current density reliability checks are critical for today’s complex, dense chip designs, but completing these checks on very large 22FDX designs requires scalability. GF and Mentor collaborated to enable a Calibre PERC solution leveraging a new multi-CPU run capability that allows mutual customers to more quickly find and resolve ESD reliability concerns in their designs.

The Calibre YieldEnhancer tool is certified for GF’s 22FDX processes. Mentor and GF are also jointly delivering enhanced use models that optimize fill runtimes, minimize shape removal caused by an engineering change order (ECO), and ensure consistency across all layers, intellectual property (IP) blocks and full-chip system-on-chips (SoCs) using fill-as-you-go methodologies.

Mentor AFS Platform and Eldo Platform for GF’s 22FDX

Mentor’s AFS Platform and Eldo Platform are supported in the GF 22FDX process. Mutual customers benefit from the AFS Platform (delivering fast, SPICE-accurate verification for the largest nanometer-scale circuits), and Eldo Platform (circuit verification for analog-centric circuits) to verify their chips designed for GF technologies.

Mentor Nitro SoC for GF 22FDX

Mentor’s Nitro SoC place and route system is certified for GF’s 22FDX process. In addition to support for 22FDX process rules, Mentor enhanced the Nitro SoC core engines to meet the new architecture requirements and design rules for this process. This enables Mentor to deliver an optimized digital implementation flow for the 22FDX node.

Synopsys, Inc. (Nasdaq: SNPS) today announced the Synopsys Design Platform fully supports TSMC’s wafer-on-wafer (WoW) direct stacking and chip-on-wafer-on-substrate (CoWoS®) advanced packaging technologies. The design platform enablement, combined with the 3D-IC reference flow, enables customer deployments for high-performance, high-connectivity multi-die technology in mobile computing, network communication, consumer, and automotive electronics applications.

The platform-wide Synopsys solution includes multi-die and interposer layout capture, physical floorplanning, and implementation, as well as parasitic extraction and timing analysis coupled with physical verification. Key products and features of the Synopsys Design Platform supporting TSMC’s advanced WoW and CoWoS packaging technologies include:

  • IC Compiler™ II place-and-route: Supports multi-die floorplanning and implementation, including interposer and 3D stack-die generation, TSV placement and connectivity assignment, orthogonal multi-layer, 45-degree single-layer, and interface inter-die block generation for inter-die extraction and checking
  • StarRC™ extraction: Supports modeling of TSV and backside RDL metal extraction, silicon interposer extraction, and inter-die coupling capacitance extraction
  • IC Validator: Supports full-system DRC and LVS verification, inter-die DRC, and LVS checking of inter-die interface
  • PrimeTime® signoff analysis: Full-system static timing analysis, supports multi-die static timing analysis (STA)

“High-performance advanced 3D silicon fabrication and wafer stacking technologies require new EDA features and flows to support the corresponding increase in design and verification complexity,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We extend our collaboration with Synopsys to deliver design solutions for TSMC’s CoWoS and WoW advanced packaging technologies. We look forward to our mutual customers benefiting from the enabled design solutions, boosting designer productivity and accelerating time-to-market.”

“Built through deep collaboration, the design solution and reference flow for TSMC’s WoW and CoWoS chip integration solutions will enable our mutual customers to achieve optimal quality of results,” said Michael Jackson, corporate vice president of marketing and business development for Synopsys’ Design Group. “The Synopsys Design Platform and methodologies will allow designers to confidently meet their schedules for cost-effective, high-performance, and low-power multi-die solutions.”

Synopsys jointly highlighted the advances and collaborations of TSMC 2.5D and 3D technologies in a paper titled “Onwards and Upwards: How Xilinx is Leveraging TSMC’s Latest Integration and Packaging Technologies with Synopsys’ Platform-wide Solution for Next-generation Designs” at the TSMC Open Innovation Platform® (OIP) Ecosystem Forum on October 3, 2018 in Santa Clara, California.

WIN Semiconductors Corp. (TPEx:3105), the world’’s largest pure-play compound semiconductor foundry, is driving the development and deployment of 5G user equipment and network infrastructure in the sub-6GHz and mmWave frequency bands. Front-end semiconductor technology has a significant influence on battery life and total power consumption of mobile devices and active antenna arrays employed in mmWave network infrastructure. GaAs is the technology of choice for front-ends used in LTE mobile devices and satisfies stringent linearity and efficiency requirements providing high quality of service while maximizing battery life. 5G user equipment and MIMO access points will impose more difficult linearity/power consumption specifications than LTE, and WIN’s portfolio of high performance GaAs technologies is well positioned to meet these new requirements and provide best value front-end solutions.

The fundamental performance advantages of GaAs make it the dominant semiconductor technology for cellular and Wi-Fi RF front-ends used in mobile devices. The technical and manufacturing demands of these large and highly competitive markets have driven significant advances in GaAs technology, and now offers best-in-class front-end performance in all 5G bands and multifunction integration necessary for complex mmWave active antenna systems. WIN’s advanced GaAs platforms integrate best-in-class transmit and receive amplifier technologies with high performance switch, logic and ESD protection functions to realize compact high performance, single chip, front-ends for mobile devices and MIMO access points operating in the sub-6GHz and mmWave 5G bands.

WIN Semiconductors’ innovative GaAs technologies, such as PIH1-10, can now monolithically integrate a high efficiency Tx power amplifier (PA), ultra-low Fmin Rx low-noise amplifier (LNA) and low loss PIN switch in a single chip mmWave front-end. In addition, this highly integrated GaAs technology provides optional linear Schottky diodes for power detectors and mixers, low capacitance PIN diodes for ESD protection and optimized E/D transistors for logic interfaces. This suite of capabilities comes in a humidity-rugged back-end, available with a copper redistribution layer and copper pillar bumps to reduce die size and allow flip chip assembly, enabling GaAs front-ends to fit within 28 and 39 GHz antenna lattice spacing.

GLOBALFOUNDRIES announced this week at its annual Global Technology Conference (GTC), that the company’s mobile-optimized 8SW 300mm RF SOI technology platform has been qualified and is in production. Several clients are currently engaged for this RF SOI process, tailored to accommodate aggressive LTE and Sub-6 GHz standards for front-end module (FEM) applications, including 5G IoT, mobile device and wireless communications.

Leveraging the 300mm RF SOI process, 8SW delivers significant performance, integration and area advantages with up to 70 percent power reduction and 20 percent smaller overall die size compared to the previous generation. The technology enables superior LNAs (low-noise amplifiers) switches and tuners by supplying higher voltage handling and a best-in-class on-resistance (Ron) and off-capacitance (Coff) for reduced insertion loss with high isolation. The optimized RF FEM platform helps designers develop solutions that enable extremely fast downloads, higher quality connections and reliable data connectivity for today’s 4G/LTE Advanced operating frequencies and future sub-6GHz 5G mobile and wireless communication applications.

“GF has now delivered more than 40 billion RF SOI chips for the world’s smart devices, and this latest generation of RF SOI technology is another proof point that we’re poised to meet accelerating global demand for solutions that deliver seamless, reliable data connectivity everywhere,” said Christine Dunbar, vice president of RF business unit at GF. “The mobile market continues to favor RF SOI, and GF’s industry leading, 8SW process in 300 mm manufacturing is specifically designed to help our clients take advantage of more frequency bands that will deliver ultra-reliable communications across high-band LTE and future 5G applications.”

“We are proud to support GF’s new advanced and differentiated 8SW technology on 300mm RF SOI substrates and to continue our long-term strategic engineering and manufacturing collaboration enabling next-generation connectivity solutions,” said Dr. Bernard Aspar, EVP, Soitec. “We are ready to deliver the 300mm RF SOI substrates in high volumes to meet GF clients’ growing market demands.”

“SEH congratulates GF on their 8SW platform. SEH believes 300 mm RF SOI products are an important technology, whose time has come,” Nobuhiko Noto, General Manager of SOI Division at SEH. “SEH has been a long time partner on RF technology and looks forward to supporting GF for their future generations of RF technologies as well. We will continue to be a supplier to the 300 mm RF SOI market as it grows.”

GF’s manufacturing legacy and deep technical expertise in RF SOI process has resulted in more than 40 billion RF SOI chips shipped for next-generation RF-enabled devices.

8SW is manufactured on GF’s 300mm production line at Fab 10 in East Fishkill, N.Y., enabling clients to take advantage of advanced tooling and processes for faster time-to-market with industry-leading RF SOI. Qualified process design kits are available now.

As part of the company’s new focus on intensifying investment in differentiation, GLOBALFOUNDRIES announced today at its annual Global Technology Conference (GTC), plans to introduce a full set of new technology features to its 14/12nm FinFET offering. The features are designed to deliver better scalability and performance for applications in high-growth markets such as hyperscale datacenters and autonomous vehicles.

In today’s data-intensive world, there is an insatiable demand for high-performance chips to process and analyze the surge of information produced by connected devices. GF’s FinFET offering is an ideal platform for designing high-performance, power-efficient system-on-chips (SoCs) for the most demanding compute applications. The new platform features will improve power, performance and scalability by delivering transistor enhancements optimized for ultra-high performance and enhanced RF connectivity, as well as new high-speed, high-density memories for emerging enterprise and cloud security needs.

“We are committed to enhancing our differentiated offerings to help clients get more value out of their investments in each technology generation,” said Dr. Bami Bastani, senior vice president of business units at GF. “By introducing these new features to our FinFET offering we are delivering powerful technology enhancements that will enable clients to extend performance and create innovative products for the next generation of intelligent systems.”

GF’s 14/12nm FinFET platform provides advanced performance and power with significant cost advantages. The feature-rich enhancements being added to the platform include:

  • Ultra-high density: Delivers increased transistor density through continued improvements to the 12LP design library (7.5T), combined with SRAM and analog advances, delivering a smaller die area to support clients in core compute, connect and store applications, as well as mobility and consumer.
  • Performance boost: Increases performance through reducing SRAM Vmin by 100mV and standby leakage current by ~50 percent – to extend performance for both existing and emerging applications in machine learning and artificial intelligence.
  • RF/analog: Provides a full suite of passive devices, ultra-thick metal and LDMOS options for advanced RF performance with Ft/Fmax at 340GHz targeting <6GHz RF SoCs with high digital content.
  • Embedded memory: Offers ultra-high security, one-time programmable (OTP) and multi-time programmable (MTP) embedded non-volatile (eNVM) memory for emerging enterprise, cloud and communication applications. Using physically undetectable charge-trapping technology (CTT) enables security solutions including “physically unclonable device” capabilities and efficient non-volatile memories for higher levels of SoC integration. GF’s CTT solution requires no additional processing or masking steps and delivers up to twice the density of similar OTP solutions based on dielectric fuse technology.

The company’s 14LPP technology can provide up to 55 percent higher device performance and 60 percent lower total power compared to 28nm technologies, while its 12LP technology provides as much as a 15 percent improvement in circuit density and more than a 10 percent improvement in performance over 16/14nm FinFET solutions on the market today. GF’s leading-edge FinFET platform has been in high-volume production since early 2016, and is Automotive Grade 2 ready.

Keysight Technologies, Inc. (NYSE: KEYS), a technology company that helps enterprises, service providers, and governments accelerate innovation to connect and secure the world, today announced that the company’s 3D planar electromagnetic (EM) simulator, Momentum, has been certified for GLOBALFOUNDRIES (GF) 22FDX®, 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology.

Keysight’s Momentum is a 3D planar EM simulator used for passive circuit modeling and analysis. It accepts arbitrary design geometries (including multi-layer structures) and uses frequency-domain Method of Moments (MoM) technology to accurately simulate complex EM effects including coupling and parasitics.

As a result of the certification, designers can now perform accurate EM simulation with GF’s cutting-edge 22FDX technology, facilitating analysis of electromagnetic effect and behavior in today’s ever shrinking and complex designs. Momentum stack-up files are integrated with the latest 22FDX PDK available from GF.

“The certification of GF 22FDX for Keysight’s EM simulator is testimony to the continuous collaboration between GF and Keysight under Keysight’s Foundry Program,” said Punmark Ngangom, RFIC Foundry Program Manager for Keysight Technologies. “Our mutual customers will now be able to leverage Keysight’s GF certified Momentum stack-up files, which are available with GF’s standard 22FDX PDK package.”

Keysight’s Momentum has also been certified for RF/mmWave-optimized metal options with different inductors, attaining highly precise correlation with silicon measurements and circuit models up to 100 GHz per GF’s certification standards.

GOWIN Semiconductor Corp., a developer of programmable logic devices, announces 2 new additions to the current families of embedded memory FPGA devices, the GW1NR-LV4MG81 and GW1NSR-LX2CQN48.  As computing functions are being distributed to edge locations, the need for silicon to adapt to these new uses is becoming prevalent.  The 2 new embedded FPGA devices were designed with low power, small package size, and low cost in mind.

Adopting an edge to cloud infrastructure is challenging.  Each portion of the chain has its own unique characteristics in design.  For the edge, size of sensor or data gatherer affects product real estate; power consumption affects the power source, especially battery life.  The new embedded memory FPGA devices solve these issues by enhancing the integration of multiple devices into a nice, single package device.

“GOWIN’s vision has always been one of developing new products for customer’s needs,” said Jason Zhu, CEO of GOWIN Semiconductor.  “We saw a lack of product integration at the edge and aimed to fix this with easy to use solutions at cost-effective price points.”

The GW1NR-LV4MG81 is a 4K LUT FPGA fabric with 64Mb internal high-speed memory.  The package size is ultra-small, 4.5mm x 4.5 mm PBGA and .83mm thick.  A great logic device for applications where the thickness is an issue.  Power consumption has been optimized to the lowest possible using TSMC’s 55nm LP process.  And up to 69 user IO’s are available supporting GOWIN’s flexible IO structures.

In a 5mm x 5mm QFN package, the GW1NSR-LX2CQN48 is GOWIN’s first device that combines a 2K LUT FPGA fabric with 32Mb internal high-speed memory and an Arm Cortex M3 microprocessor.  With additional user programmable flash, internal SRAM, ADC, and both USB2.0 and MIPI D-PHY interfaces, this makes the GW1NSR-LX2CQN48 a true SoC to solve low power requirements at the edge and elsewhere.

GOWIN offers a complete all-in-one toolchain for both FPGA fabric programming and Cortex M3 programming.  In addition, a complete library of IP cores and reference designs are available to assist in developing platform solutions.  All of these resources are available for download on GOWIN’s website, www.gowinsemi.com.

SUNY Polytechnic Institute (SUNY Poly) announced today that Professor of Nanobioscience Dr. Nate Cady has been awarded $500,000 in funding from the National Science Foundation to develop advanced computing systems based on a novel approach to the creation of non-volatile memory architecture. This research, which will also support student opportunities, aims to advance today’s typical computing model, in which processing and memory are separate, by bringing them together to make the entire process faster and more energy efficient.

“I am proud to congratulate Professor Cady on this National Science Foundation (NSF) award which is focused on enabling advanced computing capabilities, and notably, has important implications for advances in artificial intelligence,” said SUNY Poly Interim President Dr. Grace Wang. “The NSF’s selection of Dr. Cady’s research for this funding exemplifies the quality and impact of SUNY Poly’s research where our faculty and students leverage our world-class high-tech resources, explore new frontiers, and develop critical technologies for our society.”

The research will enable the design of a scalable computing infrastructure that uses nanoscale non-volatile memory (NVM) devices for both storage and computation. One of the current limits to computing speed is the result of current personal computing architecture, which separates the processor and memory and leads to a cap on data throughput, known as the “von Neumann bottleneck.” By combining storage and computation on the same device, the project circumvents this barrier and creates scalable solutions for extreme-scale computing—computing that is up to one thousand times more capable than current comparable computing—based on wires that cross each other to form memory cells at every intersection. This more powerful capability is made possible because each memory cell, acting like a synapse of the human brain, can be switched on or off, similar to the 1’s and 0’s of current computing, but it can also store many other values between the on or off states, increasing the amount of information that a given memory cell can store exponentially.

“This grant showcases the incredible potential of our faculty to tackle real-world problems with high-tech solutions that stem from the SUNY Poly’s advanced labs, cleanrooms, and capabilities. This news is especially exciting for a number of our graduate students who will be able to focus on this promising research area where they will be at the cutting-edge,” said SUNY Poly Interim Provost Dr. Steven Schneider.

“Dr. Cady’s research is a powerful example of the kind of expertise that SUNY Poly’s faculty possess as our innovation-centered ecosystem provides us with unique opportunities to move the technologies of the future forward,” said SUNY Poly Interim Dean of the College of Nanoscale Sciences; Empire Innovation Professor of Nanoscale Science; and Executive Director, Center for Nanoscale Metrology Dr. Alain Diebold.

“I look forward to advancing this non-volatile memory research at SUNY Poly, using the institution’s cutting-edge fabrication facilities in order to address current computing bottlenecks that slow computing capability and waste energy,” said Dr. Cady. “This grant will drive the development of computing and memory infrastructure that will be evaluated using high-performance simulations and experimental benchmarking within our state-of-the-art laboratory at SUNY Poly where we are eager to develop the architecture that can help revolutionize processing and memory capabilities for next-gen computers.”

Dr. Cady’s research will support SUNY Poly graduate students who will be able to obtain hands-on experience developing the computing/memory structures. The materials for this project will be developed, demonstrated, and then integrated with traditional complementary metal-oxide-semiconductor (CMOS) computer chips as part of a larger production, which will utilize SUNY Poly’s 200mm and 300mm state-of-the-art fabrication facilities. The University of Central Florida is receiving its own funds for collaborative research related to this effort.

Computing using multiple parallel flows of current through data stored in nanoscale “crossbars” is often fast and more energy-efficient, but the design of such crossbars is highly unintuitive for human designers. More specifically, this project explores formal methods for more efficiently conducting Boolean searches and using artificial intelligence techniques such as best-first search, in addition to automatically synthesizing non-volatile memory crossbar designs from specifications written in a high-level programming language.

Brewer Science, Inc. today from SEMICON Taiwan introduced the latest additions to its industry-leading BrewerBOND® family of temporary bonding materials, as well as the first product in its new BrewerBUILD™ line of thin spin-on packaging materials. BrewerBUILD delivers an industry-first solution to address manufacturers’ evolving wafer-level packaging challenges.

The BrewerBOND T1100 and BrewerBOND C1300 series combine to create Brewer Science’s first complete, dual-layer system for temporary bonding and debonding of product wafers. The new system was developed for power, memory and chip-first fan-out devices – all of which have stringent requirements with respect to temperature, power and performance. The system can be used with either mechanical or laser debonding methods.

The BrewerBUILD material was specifically created for redistribution-layer (RDL)-first fan-out wafer-level packaging (FOWLP). Developed to meet the needs of chipmakers looking to transition from chip-first FOWLP but not yet ready to tackle 2.5D/3D packaging, the single-layer material is compatible with both wafer- and panel-level temporary bonding/debonding processes.

“As industry requirements advance, Brewer Science continues to push forward the state of the art in our materials offerings,” said Kim Arnold, executive director, Advanced Packaging Business Unit, Brewer Science Inc. “Through close collaboration with our customers, we are driving the technology forward, leveraging our R&D braintrust to create unique solutions like these that are designed to meet customers’ needs – current and future.”