Tag Archives: letter-ap-tech

Winbond Electronics Corporation, a global supplier of semiconductor memory solutions, today announced the introduction of the W25N01JW, a high-performance, 1.8V Serial NAND Flash memory IC delivering a new high in data-transfer rates: 83MB/s via a Quad Serial Peripheral Interface (QSPI).

Winbond’s new high-performance Serial NAND technology also supports a two-chip dual quad interface which gives a maximum data transfer rate of 166MB/s.

This high-speed Read operation, some four times faster than existing serial NAND memory devices offer, means that the 1.8V W25N01JW chip can replace SPI NOR Flash memory in automotive applications such as data storage for instrument clusters or the center information displays (CIDs).

This is important for automotive OEMs because the adoption of more sophisticated graphics displays in the instrument cluster, and larger display sizes of 7 inches and above in the CID, is increasing system memory requirements to capacities of 1Gbit and higher. At these capacities, serial NAND Flash has a markedly lower unit cost than that of SPI NOR Flash, and occupies a smaller board area per megabit of storage capacity.

SPI NOR Flash has been the preferred memory technology in automotive displays for many years because of its high read speed, which supports the fast boot requirements of automotive user interfaces, and because of its high reliability and long data retention. By raising the data transfer rate of its serial NAND technology to 83MB/s – matching the read speed of automotive SPI NOR Flash – Winbond has ensured that the W25N01JW can support fast boot operation and the demanding requirements of sophisticated graphics applications.

The W25N01JW also meets strict automotive requirements for quality and reliability. Built with high-reliability single-level sell (SLC) memory technology, and implementing 1-bit error correction code (ECC) on all Read and Write operations, it complies with the endurance, retention and quality requirements of the AEC-Q100 standard and relevant JEDEC specifications.

The W25N01JW device operates from -40°C to 105°C and retains data for 10 years at 85°C after 1,000 program/erase cycles, whereas eMMC can only retain data for a fraction of that time under these conditions even when used in SLC mode, which are today widely used for data storage in the CIDs of high-end vehicles.

“Cars’ large and attractive displays need higher memory capacity, beyond the ‘sweet spot’ of SPI NOR Flash, which is good for up to 512Mbits,” said William Chen, deputy director of the Flash Product Marketing Division at Winbond. “For systems that require high-speed memory in capacities of 1Gbit or higher, Winbond’s high-performance Serial NAND Flash is the new best choice for automotive OEMs, offering a combination of lower unit cost, smaller size and excellent reliability and data retention.”

The W25N01JW is available for sampling today in a capacity of 1Gbit. A two-chip implementation in dual-quad I/O mode provides 2Gbits of memory capacity and a maximum data transfer rate of 166MB/s.

The chip is available in industrial grade and in an extended-temperature automotive grade version operating at up to 105°C. It is compatible with standard SPI NAND Flash protocols. It is housed in standard 8mm x 6mm WSON and TFBGA packages that are footprint-compatible with standard SPI NOR Flash products.

Ease of use and design re-use across frequencies have not traditionally been associated with RF power solutions — until now. Today, NXP Semiconductors N.V. (NASDAQ:NXPI), a developer of RF power, introduces two new power blocks that promise to become a new standard for years to come.

The simplicity of these new devices lies in the availability of laterally diffused metal oxide semiconductor (LDMOS) technology for RF transistors in ubiquitous TO-247 and TO-220 power packages, that come with well established assembly processes. This is augmented with the simultaneous availability of very compact reference circuits that can be reused from 1.8 Megahertz (MHz) to 250 MHz. This results in considerable savings, fast time to market and optimized supply chain for most High Frequency (HF) and Very High Frequency (VHF) power systems.

Removing Barrier to Entry for RF Power
NXP’s new RF solutions include the MRF101AN 100 watt (W) transistor that is housed in the TO-220 package, and the MRF300AN 300 W transistor that is housed in the TO-247 package. While current plastic packages for high power RF require a precise solder reflow process, these transistors can be assembled to a printed circuit board (PCB) using a standard through-hole technology, reducing costs. Heatsinking is also simplified since the transistors can be mounted vertically to a chassis, or in more creative and versatile ways such as under the PCB. This opens many options for the mechanical design, contributing to lower the Bill of Materials (BoM) and reduce time to market.

“RF Power is moving increasingly into new applications, where the requirements for ease of use, high performance and versatility are essential,” said Pierre Piel, senior director and general manager for multi-market RF power at NXP. “We continue our mission to ease the use of RF Power by delivering solutions that minimize design requirements, reduce time to market and simplify the supply chain for our customers.”

Flexibility Without Compromise on Performance
At 40.68 MHz, the MRF300AN outputs 330 W Continuous Wave (CW), with 28 decibels (dB) of gain and 79 percent efficiency. As part of NXP’s series of extremely rugged transistors, the family is designed for use in unforgiving industrial applications and can withstand 65:1 Voltage Standing Wave Ratio (VSWR).

This performance is supported by 2 x 3 inch (5.1 x 7.1 centimeters) power block reference designs that use cost-effective PCB material. With only a change of coils and discrete components, and no change to the PCB layout, the board can be adapted to support any other frequency from 1.8 to 250 MHz. This ensures quick design cycle for RF designers to develop power amplifiers that address new markets.

For even more flexibility, each transistor comes in two configurations. For example, the MRF101BN mirrors the pin-out of the MRF101AN, enabling a compact push-pull layout to address wideband applications without compromise on efficiency.

The MRF101AN and MRF300AN target Industrial, Scientific and Medical (ISM) applications as well as HF and VHF communications. A new market is also expected with switch-mode power supply, since this technology enables switching at higher frequencies than existing solutions, reducing the size of other components of the BoM. The devices are part of NXP’s Product Longevity Program guaranteeing availability for 15 years.

Availability
The MRF300AN is available now. The MRF101AN is currently sampling, with production expected in September 2018. Reference circuits for the MRF300AN are available for 27 MHz, 40.68 MHz, 81.36 MHz and 230 MHz. For pricing or additional information, please contact your local NXP sales office or approved distributor.

TowerJazz, the global specialty foundry leader, and Gpixel, Inc., a fast-growing CMOS image sensor (CIS) provider focusing on professional applications, announced today that Gpixel’s GMAX0505, a new 25Mp global shutter sensor has been developed based on TowerJazz’s 2.5um global shutter pixel in a 1.1″ optical format with the highest resolution in C-mount optics. This type of lens mount is commonly found in closed-circuit television cameras, machine vision and scientific cameras. Gpixel’s new product is optimal for high resolution industrial, machine vision, intelligent transport systems (ITS) and surveillance applications. According to an IC Insights report, the industrial CMOS sensor market is growing at a CAGR of about 18% from $400M in 2015 to $910M in 2020.

TowerJazz’s new offering is the smallest in the world; the otherwise currently available smallest pixel for such high-end applications used in the market is 3.2um (65% larger) and demonstrates overall lower performances. TowerJazz’s 2.5um global shutter pixel is integrated with a unique light pipe technology, offers great angular response, more than 80dB shutter efficiency in spite of the extreme small size, and extremely low noise (one electron). Gpixel has started prototyping its GMAX0505 using TowerJazz’s state of the art, 65nm technology on a 300mm platform in its Uozu, Japan facility.

“TowerJazz has been an important and strategic fab partner of Gpixel for many years. We are very pleased with the support of great technology innovation from TowerJazz with our current global shutter sensor families, backside illuminated scientific CMOS sensor solutions and today, the next generation global shutter industrial sensor product family,” said Dr. Xinyang Wang, CEO of Gpixel, Inc. “The GMAX0505 is our second product after our first 2.8um pixel product that is already ramped up into production at TowerJazz’s Arai fab in Japan. We are very excited and looking forward to seeing more products using this pixel technology in the near future. The successful introduction of the new 25Mp product will bring our customers a unique advantage in the growing demand of machine vision applications.”

Dr. Avi Strum, TowerJazz Senior VP and General Manager of CMOS Image Sensor Business Unit, said, “We are very excited to be the first and only foundry in the world to offer this new technology – the smallest global shutter pixel available. Through our collaboration with Gpixel, we are able to create acompact package design which allows for miniature camera design. We are pleased with our long term relationship with Gpixel and with the way our technology combined with their excellent products allow us to target and gain market share in the growing high resolution industrial markets.”

The 64th annual IEEE International Electron Devices Meeting(IEDM), to be held at the Hilton San Francisco Union Square hotel December 1-5, 2018, has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Wednesday, August 1, 2018. Authors are asked to submit four-page camera-ready papers. Accepted papers will be published as-is in the proceedings. A limited number of late-news papers will be accepted. Authors are asked to submit late-news papers announcing only the most recent and noteworthy developments. The late-news submission deadline is September 10, 2018.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics gather to participate in a technical program consisting of more than 220 presentations, along with a variety of panels, special sessions, Short Courses, a supplier exhibit, IEEE/EDS award presentations and other events highlighting leading work in more areas of the field than any other conference.

This year, special emphasis is placed on the following topics:

  • Neuromorphic computing/AI
  • Quantum computing devices and links
  • Devices for RF, 5G, THz and mmWave
  • Advanced memory technologies
  • More-than-Moore devices and integrations
  • Technologies for advanced logic nodes
  • Non-charge-based devices and systems
  • Sensors and MEMS devices
  • Package-device level interactions
  • Electron device simulation and modeling
  • Advanced characterization, reliability and noise
  • Optoelectronics, displays and imaging systems

Overall, papers in the following areas of technology are encouraged:

  • Circuit and Device Interaction
  • Characterization, Reliability and Yield
  • Compound Semiconductor and High-Speed Devices
  • Memory Technology
  • Modeling and Simulation
  • Nano Device Technology
  • Optoelectronics, Displays and Imagers
  • Power Devices
  • Process and Manufacturing Technology
  • Sensors, MEMS and BioMEMS

Further information

For more information, interested persons should visit the IEDM 2018 home page at www.ieee-iedm.org.

A Columbia University-led international team of researchers has developed a technique to manipulate the electrical conductivity of graphene with compression, bringing the material one step closer to being a viable semiconductor for use in today’s electronic devices.

By compressing layers of boron nitride and graphene, researchers were able to enhance the material's band gap, bringing it one step closer to being a viable semiconductor for use in today's electronic devices. Credit: Philip Krantz

By compressing layers of boron nitride and graphene, researchers were able to enhance the material’s band gap, bringing it one step closer to being a viable semiconductor for use in today’s electronic devices. Credit: Philip Krantz

“Graphene is the best electrical conductor that we know of on Earth,” said Matthew Yankowitz, a postdoctoral research scientist in Columbia’s physics department and first author on the study. “The problem is that it’s too good at conducting electricity, and we don’t know how to stop it effectively. Our work establishes for the first time a route to realizing a technologically relevant band gap in graphene without compromising its quality. Additionally, if applied to other interesting combinations of 2D materials, the technique we used may lead to new emergent phenomena, such as magnetism, superconductivity, and more.”

The study, funded by the National Science Foundation and the David and Lucille Packard Foundation, appears in the May 17 issue of Nature.

The unusual electronic properties of graphene, a two-dimensional (2D) material comprised of hexagonally-bonded carbon atoms, have excited the physics community since its discovery more than a decade ago. Graphene is the strongest, thinnest material known to exist. It also happens to be a superior conductor of electricity – the unique atomic arrangement of the carbon atoms in graphene allows its electrons to easily travel at extremely high velocity without the significant chance of scattering, saving precious energy typically lost in other conductors.

But turning off the transmission of electrons through the material without altering or sacrificing the favorable qualities of graphene has proven unsuccessful to-date.

“One of the grand goals in graphene research is to figure out a way to keep all the good things about graphene but also create a band gap – an electrical on-off switch,” said Cory Dean, assistant professor of physics at Columbia University and the study’s principal investigator. He explained that past efforts to modify graphene to create such a band gap have degraded the intrinsically good properties of graphene, rendering it much less useful. One superstructure does show promise, however. When graphene is sandwiched between layers of boron nitride (BN), an atomically-thin electrical insulator, and the two materials are rotationally aligned, the BN has been shown to modify the electronic structure of the graphene, creating a band gap that allows the material to behave as a semiconductor – that is, both as an electrical conductor and an insulator. The band gap created by this layering alone, however, is not large enough to be useful in the operation of electrical transistor devices at room temperature.

In an effort to enhance this band gap, Yankowitz, Dean, and their colleagues at the National High Magnetic Field Laboratory, the University of Seoul in Korea, and the National University of Singapore, compressed the layers of the BN-graphene structure and found that applying pressure substantially increased the size of the band gap, more effectively blocking the flow of electricity through the graphene.

“As we squeeze and apply pressure, the band gap grows,” Yankowitz said. “It’s still not a big enough gap – a strong enough switch – to be used in transistor devices at room temperature, but we have gained a fundamentally better understanding of why this band gap exists in the first place, how it can be tuned, and how we may target it in the future. Transistors are ubiquitous in our modern electronic devices, so if we can find a way to use graphene as a transistor it would have widespread applications.”

Yankowitz added that scientists have been conducting experiments at high pressures in conventional three-dimensional materials for years, but no one had yet figured out a way to do them with 2D materials. Now, researchers will be able to test how applying various degrees of pressure changes the properties of a vast range of combinations of stacked 2D materials.

“Any emergent property that results from the combination of 2D materials should grow stronger as the materials are compressed,” Yankowitz said. “We can take any of these arbitrary structures now and squeeze them and the strength of the resulting effect is tunable. We’ve added a new experimental tool to the toolbox we use to manipulate 2D materials and that tool opens boundless possibilities for creating devices with designer properties.”

TowerJazz, the global specialty foundry leader, and Newsight Imaging, today announced production of Newsight’s advanced CMOS image sensor (CIS) chips and camera modules, customized for very high volume LiDAR and machine vision markets, combining sensors, digital algorithms and pixel array on the same chip. Newsight’s CIS chips are used in ADAS (advanced driver assistance systems) and autonomous vehicles as well as in drones and robotics.

LiDAR (Light Detection and Ranging), a detection system which works on the principle of radar, but uses light from a laser, is considered a must have for autonomous driving due to its high resolution at long distances, and market growth is expected to be exponential once L4/L5 autonomous vehicles become mainstream. IHS estimates the automotive LiDAR semiconductor market will reach $1.8 billion by 2026, with 37% CAGR (2018-2026). By utilizing TowerJazz’s advanced 180nm technology, featuring a wide range of customizable pixel architectures and technologies, Newsight is well-positioned to address the vast opportunities in the automotive market as well as in the security, defense, medical, industrial, and consumer markets.

Newsight’s innovative image sensor chips are ideal for high volume, competitive applications requiring cost effectiveness, low power consumption, high performance, and analog and digital integration. The NSI3000 sensor family, currently in mass production at TowerJazz’s Migdal Haemek, Israel facility, offers extremely high sensitivity pixels, enabling the replacement of expensive CCD (charge-coupled device) sensors in many applications and is designed for programmable high frame rate speeds, allowing better analysis and reaction to events.

In addition, Newsight’s innovative NSI5000, currently in development with TowerJazz at its fab in Israel, is an integrated LiDAR solution for long-range applications and includes a top DSP (digital signal processor) controller which enables complex calculations for depth and machine vision. NSI5000 is used in cutting-edge 3D pulsed based LiDARs for automotive applications and is based on Newsight’s eTOF (enhanced time-of-flight), which bridges the gap between short-distance iTOF (indirect time-of-flight) and the long distance automotive requirement, by extending the dynamic range while retaining high accuracy.

“We chose TowerJazz for its advanced pixel technology, specially customized for our CMOS image sensor chips addressing very high volume markets. Together with our technology, we were able to demonstrate a 4X better sensitivity to our customers. TowerJazz’s CIS offering is proven in the industry and we are pleased to manufacture locally in Israel with a leader in the global analog foundry space,” said Eli Assoolin, Chief Executive Officer, Newsight Imaging.

“With our high-end pixel offering, tailored to specific product and application needs, we are able to provide advanced technology used for high dynamic range CMOS sensors and solutions for the growing LiDAR and automotive markets. We are very happy to work closely with Newsight Imaging to provide market leading solutions and achieve quick time to market. They have shown to be an extremely fast-moving customer and we have a lot of confidence in their success,” said Dr. Avi Strum, TowerJazz Sr. Vice President and GM, CMOS Image Sensor Business Unit.

TowerJazz today announced the release of its 300mm 65nm BCD (Bipolar-CMOS-DMOS) process, the most advanced power management platform for up to 16V operation and 24V maximum voltage.  This technology is manufactured in TowerJazz’s Uozu, Japan facility, with best-in-class quality and cycle time, and is based on the Company’s 300mm 65nm automotive qualified flows.

This platform provides significant material competitive advantages for any type of power management chip up to 16V regardless of application, including a wide variety of products such as: PMICs, load switches, DC-DC converters, LED drivers, motor drivers, battery management, analog and digital controllers, and more. IHS Markit Power IC Analyst, Kevin Anderson forecasts a $9.4 billion available market, which this technology addresses, in 2018 with continual growth.

TowerJazz’s 65nm BCD process is leading this low voltage market segment with the highest power efficiency, very small die size, best digital integration capability; and superior cost effectiveness through both the smallest aerial footprint and the lowest mask count.

The process includes four leading edge power LDMOS transistors: 5V, 7V, 12V and 16V operation, each with the best available Rdson and Qgd parameters. In addition to the new aforementioned cost and figure of merit benchmarks, multiple chips can be integrated to a single monolithic IC solution replacing a multiple chip module for an improved system cost structure and system performance.

TowerJazz’s power transistors are fully isolated to withstand high currents, all with an ultra-low Rdson, e.g. less than 1mΩ*mm² for the 5V LDMOS. For products which operate at the megahertz (MHz) switching frequencies, the 65nm BCD power transistors benefit from a very low Qgd down to 2.6mΩ*nC. In addition, very low metal resistance is achieved using a single or dual 3.3um top thick copper. The 65nm BCD also offers aggressive 113Kgate/mm² 5V digital density and an 800Kgate/mm² 1.2V digital library.

“This new 65nm BCD platform establishes TowerJazz as a technology leader in the related growing markets for up to 16V power applications,” said Shimon Greenberg, Vice President and General Manager of Power Management & Mixed-Signal/CMOS Business Unit, TowerJazz. “Best addressing the vast low voltage power management market segment, we are experiencing very high interest from early adopter customers and plan a mass production ramp by the fourth quarter of 2018.”

TowerJazz will be exhibiting at ISPSD, the 30th IEEE International Symposium on Power Semiconductor Devices and ICs on May 13-17, 2018 in Chicago, USA.

Research appearing today in Nature Communications finds useful new information-handling potential in samples of tin(II) sulfide (SnS), a candidate “valleytronics” transistor material that might one day enable chipmakers to pack more computing power onto microchips.

Valleytronics utilizes different local energy extrema (valleys) with selection rules to store 0s and 1s. In SnS, these extrema have different shapes and responses to different polarizations of light, allowing the 0s and 1s to be directly recognized. This schematic illustrates the variation of electron energy in different states, represented by curved surfaces in space. The two valleys of the curved surface are shown. Credit: Berkeley Lab

Valleytronics utilizes different local energy extrema (valleys) with selection rules to store 0s and 1s. In SnS, these extrema have different shapes and responses to different polarizations of light, allowing the 0s and 1s to be directly recognized. This schematic illustrates the variation of electron energy in different states, represented by curved surfaces in space. The two valleys of the curved surface are shown. Credit: Berkeley Lab

The research was led by Jie Yao of the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and Shuren Lin of UC Berkeley’s Department of Materials Science and Engineering and included scientists from Singapore and China. Berkeley Lab’s Molecular Foundry, a DOE Office of Science user facility, contributed to the work.

For several decades, improvements in conventional transistor materials have been sufficient to sustain Moore’s Law – the historical pattern of microchip manufacturers packing more transistors (and thus more information storage and handling capacity) into a given volume of silicon. Today, however, chipmakers are concerned that they might soon reach the fundamental limits of conventional materials. If they can’t continue to pack more transistors into smaller spaces, they worry that Moore’s Law would break down, preventing future circuits from becoming smaller and more powerful than their predecessors.

That’s why researchers worldwide are on the hunt for new materials that can compute in smaller spaces, primarily by taking advantage of the additional degrees of freedom that the materials offer – in other words, using a material’s unique properties to compute more 0s and 1s in the same space. Spintronics, for example, is a concept for transistors that harnesses the up and down spins of electrons in materials as the on/off transistor states.

Valleytronics, another emerging approach, utilizes the highly selective response of candidate crystalline materials under specific illumination conditions to denote their on/off states – that is, using the materials’ band structures so that the information of 0s and 1s is stored in separate energy valleys of electrons, which are dependent on the crystal structures of the materials.

In this new study, the research team has shown that tin(II) sulfide (SnS) is able to absorb different polarizations of light and then selectively reemit light of different colors at different polarizations. This is useful for concurrently accessing both the usual electronic – and the material’s valleytronic – degrees of freedom, which would substantially increase the computing power and data storage density of circuits made with the material.

“We show a new material with distinctive energy valleys that can be directly identified and separately controlled,” said Yao. “This is important because it provides us a platform to understand how valley signatures are carried by electrons and how information can be easily stored and processed between the valleys, which are of both scientific and engineering significance.”

Lin, the first author of the paper, said the material is different from previously investigated candidate valleytronics materials because it possesses such selectivity at room temperature without additional biases apart from the excitation light source, which alleviates the previously stringent requirements in controlling the valleys. Compared to its predecessor materials, SnS is also much easier to process.

With this finding, researchers will be able to develop operational valleytronic devices, which may one day be integrated into electronic circuits. The unique coupling between light and valleys in this new material may also pave the way toward future hybrid electronic/photonic chips.

Berkeley Lab’s “Beyond Moore’s Law” initiative leverages the basic science capabilities and unique user facilities of Berkeley Lab and UC Berkeley to evaluate promising candidates for next-generation electronics and computing technologies. Its objective is to build close partnerships with industry to accelerate the time it typically takes to move from the discovery of a technology to its scale-up and commercialization.

Spin Transfer Technologies, Inc., the developer of advanced STT-MRAM for embedded SRAM and stand-alone DRAM applications, today announced results of its unique Precessional Spin Current (PSC™) structure. The results from advanced testing of the PSC structure confirm that it will increase the spin-torque efficiency of any MRAM device by 40-70 percent — enabling dramatically higher data retention while consuming less power. This gain translates to retention times lengthening by a factor of over 10,000 (e.g., 1 hour retention becomes more than 1 year retention) while reducing write current. Improved efficiency is critical for enabling MRAM to replace SRAM and DRAM in mobile, datacenter and AI applications, as well as for improving retention and performance in high-temperature automotive applications. The company reported these results at the prestigious Intermag 2018 Conference.

Spin-torque efficiency is one of the core performance metrics of the pMTJ (perpendicular magnetic tunnel junction — the “bit” that stores the memory state in an MRAM memory) and is defined by the ratio between the thermal retention barrier, measuring how long data can be reliably stored in the memory, and the switching current necessary to change the value of the bit. In previous MRAM implementations, increasing the energy barrier to increase retention would require a proportional increase in write current — leading to higher power consumption and much faster wear-out of the pMTJ devices (lower endurance). The PSC structure is a breakthrough because it effectively decouples the static energy barrier that determines retention from the dynamic switching processes that govern the switching current. As a result, when the PSC structure is added to any pMTJ, benefits include:

  • A higher energy barrier when the pMTJ does not have current flowing through it, which is ideal for retaining data for long periods
  • An increased spin polarization when current is flowing and the device is writing a new state, which is ideal for minimizing switching current and extending the life of the device by many orders of magnitude

The PSC structure was designed from the outset to be modular and fabricated with any pMTJ — either the company’s own pMTJs, or a pMTJ from other sources. The PSC structure is fabricated during the pMTJ deposition process and adds approximately 4nm to the height of the pMTJ stack. The structure is compatible with a wide range of standard MRAM manufacturing processes, materials and tool sets — enabling any foundry to readily incorporate the PSC structure into existing pMTJ stacks without adding significant complexity or manufacturing costs.

“MRAM is attracting a lot of attention as an embedded memory for ASICs and MCUs, but issues of write current and data retention have caused concern,” said Jim Handy, general director of Objective Analysis. “Spin Transfer Technologies’ new PSC structure shows a lot of promise to solve a number of those issues and pave the path for MRAM to take a significant share of the embedded memory market.”

Spin Transfer Technologies’ testing of the PSC structure involved comparing the performance of the same pMTJ devices with and without PSC for a large number of devices within CMOS test chip arrays at various temperatures and device diameters. The tests exhibited a robust performance advantage due to the PSC structure, both during writing of the low-resistance (“0”) and the high-resistance (“1”) memory states. Some specific examples of the advantages that the data have shown are as follows:

  • Increase of the spin-torque efficiency by up to 70 percent
  • Demonstration of the efficiency gain across a range of sizes (40-60nm) and temperatures (30°C to 125°C)
  • Increase of the thermal energy barriers by 50 percent corresponding to an increase in data retention time of greater than four orders of magnitude while reducing the switching current
  • Reduction of read disturb error rate up to five orders of magnitude

These advantages have come without degradation to other performance parameters. The data for the PSC structure indicate significant potential for enabling high-speed applications as well as high-temperature automotive and other applications. Furthermore, since the data shows that the PSC structure’s efficiency gains actually increase as the pMTJ get smaller, the PSC structure opens new pathways to achieving embedded SRAMs in the latest 7nm and 5nm generations.

“There is a huge demand for a memory with the endurance of SRAM, but with higher density, lower operating power and with non-volatility. We believe the improvements the PSC structure brings to STT-MRAM technology will make it a highly attractive alternative to SRAM for these reasons,” said Mustafa Pinarbasi, CTO and SVP of Magnetics Technology at Spin Transfer Technologies. “We are excited to enable the next generation of STT-MRAM and to shake up the status quo of the memory industry through our innovation.”

Mobile Semiconductor, a Seattle WA based company, today announced the inclusion of its new 22nm ULL (Ultra Low Leakage) memory compilers in the industry leading GLOBALFOUNDRIES FDXcelerator Program.  This new embedded SRAM technology on 22nm FDX offers the best in class memory solution using the GLOBALFOUNDRIES low leakage FDSOI bit cells and ultra-low leakage devices.

Cameron Fisher, CEO and Founder of Mobile Semiconductor, said, “This is a very important technology for low cost industrial and consumer products.  Our customers come from a wide range of markets, but one thing they share in common is the need to drive the power usage down to allow maximum battery life.”

This new compiler, equipped with multiple speed grades, allows the customer to maximize performance of their end product balancing power vs speed.  These low leakage memories make intelligent use of the reverse body bias capabilities of the FDSOI technology to control leakage and enhance performance.

Mobile Semiconductor’s 22nm ULL memory complier is unique in the industry and comes with the same high-quality design, testing, and support that customers have come to expect from their products.

Fisher said, “Mobile Semiconductor remains the leader in providing low power solutions and this complier removes the roadblocks that engineers have struggled with in their previous designs. Almost every single product developed for the IoT Market, will have new and more stringent demands placed on them.  We believe that Mobile Semiconductor is meeting the most important one – power!”