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Chemical precursors (inorganic and organic) used to form high dielectric constant (High-K) materials, metals and metal nitrides needed in advanced ICs are forecasted to reach $400M USD in global sales by 2020, as highlighted in TECHCET’s 2016 Critical Materials Report. Estimated to have totaled over $258M in 2015, this market consists of ~51% high-k metal precursors used for gate dielectrics and capacitors, and ~49% other metal precursors used for electrode and interconnect processes.

The largest usage for High K ALD and CVD (Atomic Layer Deposition and Chemical Vapor Deposition) precursors will continue to be capacitor formation for volatile memory devices through 2020. However, it is expected that revenues for High-K gate oxides processes may surpass memory capacitors by 2021. Compared to CVD, the ALD process relies on unique properties of precursors to self-limit reactions at the atomic level, so ALD precursors are generally chemically engineered complex molecules that command relatively higher average selling prices.

Atomic Layer Etching (ALE) is a new technology similar to ALD, in that alternating sequential surface-limited steps remove precise layers. When engineering atom-scale device features, chip fabricators will continue to rely on such high precision processes employing new and existing materials to enable high quality surfaces. Besides the physical plasma assisted path to ALE employing Cl2 and Ar ions, the chemical path to ALE uses metal organic compounds and hydro fluoric acid, and recent research is focused on using tin(II) acetylacetonate and other beta-diketonates.

Understanding the complex dynamics of materials interactions are critical to the successful use of novel processes and materials in IC HVM. Challenges and opportunities relating to the affordable, controllable, and safe implementation of new materials will be presented in detail at the Critical Materials Conference 2016—open to the public May 5-6, in Hillsboro, Oregon—in conjunction with the private Critical Materials Council (CMC) meetings. For more info on TECHCET’s Report or to Register for the CMC Conference, please go to www.cmcfabs.org/seminars/ or contact [email protected]

TECHCET’s work is focused on process materials supply-chains and materials technology trends for Semiconductor, Display, Solar/PV, and LED manufacturing industries. The company has been responsible for producing the Critical Material Reports for SEMATECH and the industry since 2000. This work continues to benefit the Critical Materials Council, now organized as CMC Fabs. For more info please go to: www.cmcfabs.org or www.techcet.com

Front-end fab equipment spending (including new, used, and in-house) is projected to increase 3.7 percent in 2016 (to US$ 37.2 billion) and another 13 percent in 2017 (to $42.1 billion) according to most recent edition of the SEMI World Fab Forecast.  Fab equipment spending for 2015 ended almost flat ($35.9 billion), with a slight decrease of -0.4 percent year-over-year.

The SEMI World Fab Forecast report presents details of fab-related spending through the industry and extends the outlook through the end of 2017.  Fab equipment spending is expected to pick up slowly in the first half of 2016, and accelerate into the second half when momentum starts to build for 2017, with a return to double-digit growth rates (see Figure 1).

Figure 1

Figure 1

The biggest contributors to the growth are foundries, 3D NAND fabs, and companies beginning to equip and prepare for the 10nm ramp-up in 2017. Dedicated foundries continue to represent the largest spending segment. Spending for 2015 dropped slightly from $10.7 billion to $9.8 billion (-8 percent YoY), but is expected to increase by 5 percent in 2016 and almost 10 percent in 2017.

DRAM spending ranks second place after foundries. After a strong 2015, DRAM spending is expected to slow in 2016 (-23 percent) and increase again in 2017 by 10 percent.

In terms of spending growth rates, the big momentum comes from 3D NAND (including 3D XPoint). Spending doubled from about $1.8 billion in 2014 to $3.6 billion in 2015, 101 percent growth. In 2016, it will again rise to more than $5.6 billion (50 percent growth).

The increase in equipment spending is also supported by six companies, which are among the top 10 spenders globally. The six have announced plans to increase their respective capital expenditures in 2016, while the assumption for the largest spender, Samsung, is that capital expenditure will be less than in 2015.

Equipment spending growth for 2017 is also buoyed by new 24 facilities (excluding R&D) which began construction in 2015 or will begin construction this year. These projects are located around the world, including eight planned in China alone.

The industry has recently set records for mergers and acquisitions, and more are expected in 2016.  The combined flat growth for semiconductor equipment spending in 2015 and slow growth in 2016 confirm a more mature industry.  New technologies — new nodes and newer memory devices — will drive the increase in spending currently forecasted for 2017.

Learn more about SEMI fab databases at: www.semi.org/en/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

According to IC Insights’ new 2016 edition of The McClean Report, total worldwide semiconductor industry capital spending is forecast to show low single-digit growth in 2016 after registering a 1% decline in 2015.  As discussed below, last year’s drop in semiconductor industry capital spending was a significant departure from historical patterns that go back more than 30 years.

Figure 1 shows the annual worldwide semiconductor industry capital spending changes from 1983-2015.  Over the past 33 years, there have been six periods when semiconductor industry capital spending declined by double-digits rates for one or two years (1985-1986, 1992, 1997-1998, 2001-2002, 2008-2009, and 2012-2013).  It is interesting to note that in every case except the 2012-2013 spending downturn, within two years after the period of decline in capital spending, a surge in spending of at least 45% occurred.  The second year increases in spending after the cutbacks were typically stronger than the first year after a downturn with the lone exception to this being the 2010 spending rebound after the 2008-2009 downturn.  This was because most semiconductor producers tend to act very conservatively coming out of a market slowdown and wait until they have logged about 4-6 quarters of good operating results before significantly increasing their capital spending again.

As shown in Figure 1, the streak of strong capital spending growth within two years after a spending cutback timeperiod ended in 2015, with capital spending registering a 1% decline.  IC Insights believes that this is yet another indication of a maturing semiconductor industry.

Figure 1

Figure 1

More detailed information on semiconductor industry capital spending, including 2016 capital spending forecasts by company, can be found in IC Insights’ flagship market research report, The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry. The new 478-page McClean Report provides IC market and technology trend forecasts from 2016 through 2020.

The FinFET technology market is expected to grow from $4.91 billion USD in 2015 to $35.12 billion by 2022, at a compound annual growth rate (CAGR) of 26.2% between 2016 and 2022, according to the new market research report,”FinFET Technology Market by Technology (22nm, 20nm, 16nm, 14nm, 10nm, 7nm), Product (CPU, SoC, FPGA, GPU, MCU, and Network Processor), End-User (Smartphones, Computers & Tablets, Wearables, and Automotive) and Geography – Global Forecast to 2022,” published by MarketsandMarkets.

The FinFET technology market is driven by factors such as miniaturization of semiconductor devices with increase in the performance, growing mobile and consumer electronics market, and high performance with lower current leakage than bulk technology.

FinFET Technology was first introduced at the 22nm process node by Intel (U.S.)

On the basis of technology the FinFET technology market is segmented into 22nm, 20nm, 16nm, 14nm, 10nm, and 7nm. Intel (U.S.) was the first company to manufacture products at the 22nm FinFET technology, which basically have their applications in computers and servers. With the increasing need of miniaturization of semiconductor components along with better performance parameters and reduction in power consumption, the market for the 7nm FinFET technology is expected to grow at a high rate in future.

Applications in wearables to register the highest growth rate

Computers and smartphones were early adopters of FinFET technology and are driving the market, currently. Application processors in smartphones have the same functionalities as that of CPUs. Samsung (South Korea) led the market for application processors in 2015 by introducing its Exynos Octa 7 chips manufactured using the 14nm FinFET technology. By 2016, the next chip in the Exynos series (Exynos Octa 8) is expected to power the smartphones with more functionalities and improved performance. FinFETs are also gaining popularity in several application areas such as wearables, high-end networks, and automotive. The wearable device market is expected to grow at a high rate, catapulting the FinFET technology market further.

Asia-Pacific to be the fastest-growing market

North America accounted for majority large share of the overall FinFET Technology Market in 2015. The market in APAC is expected to grow at the highest CAGR between 2016 and 2022. Dome countries in Asia-Pacific are major manufacturing hubs and are expected to provide ample opportunities for the growth of the FinFET technology. The growing demand for high performance in smartphones and automotive CPUs is driving the market in this region.

This global report gives a detailed view of the market across the four regions, namely, North America, Europe, Asia-Pacific, and Rest of the World which includes the Middle East and Africa. The report profiles the 10 most promising players in the FinFET technology market.

The competitive landscape of the market presents a very interesting picture, wherein the OEMs, component manufacturers, and system integrators in the FinFET technology market value chain have come together and are majorly focused on the development of advanced and improved FinFET products.

Major players in this market are Intel (U.S.), TSMC (Taiwan), Samsung (South Korea), and GlobalFoundries (U.S.).

How Texas Instruments got greener, safer and saved money.

BY STEVEN BALLANCE Texas Instruments, Dallas, TX, KARL OLANDER and JOE SWEENEY, Entegris, Billerica, MA

Over the last decade, considerable efforts have been put forth by manufacturers and suppliers to help reduce costs, consumption of natural resources, and where economically viable or by mandate, to become more green in fab operations. In the early 2000s, Texas Instruments (TI) outlined an opportunity to re-think its approach around one of the largest energy and cleanroom air consumption areas in the fab—ion implant operations.

In comparison to other manufacturing tools in the fab, ion implanters require the largest exhaust volume, typically using 2500 CFM in total ventilation, split between the gas box [400+ CFM] and the containment shell enclosure [2000+ CFM]. The energy cost to replace this volume of air equates to about $8,000 per tool and, with up to 30 implanters in a typical fab, the operating costs can reach up to $240K annually. In addition, the investment needed to replace this volume of clean, highly conditioned air is substantial and requires large infrastructure expenditures (FIGURE 1).

Ion Implant 1

In the late 2000s, TI provided the industry with a glimpse of what was possible around air handling and energy reduction in its implant centers. The initial concept, implementation and projected results had been years in the making and were first published in August, 2009 by Solid State Technology, as provided by Steve Russo, then a senior member of TI’s technical staff.

In the article, Russo explained the operating protocols for handling the highly toxic materials utilized in the ion implant process, which are traditionally stored within the tool itself. Now, after years of development and modification, a bigger picture, along with intriguing data, has emerged.

Recycling the shell exhaust

The 2009 article described how TI recycled the implanter shell exhaust within the fab, reducing the make-up air requirement by 80% [2000 CFM per tool]. Fab air is drawn through the implanter shell to dissipate heat from the process and provide dilution in the event of a process leak. This volume of air is treated as general exhaust, and traditionally expelled from the fab using blowers on the roof.

The successful implementation of the first phase, led to the recycle of the shell exhaust on more than 60 ion implant tools across three fabs without incident. Whereas the initial installation included ductwork to convey shell exhaust to the roof (if needed in an emergency), subsequent facilities were built on the premise of continuously returning the shell exhaust to the fab. In practice, the reconfigured exhaust systems amounted to a $57,000 capital cost avoidance per process tool. FIGURE 2 illustrates these cost savings projections.

Ion Implant 2

Recycling the shell exhaust has resulted in avoiding $1.7 million in capital for exhaust and make-up air infrastructure, as well as, reducing annual energy cost by $470,000. The lower energy usage equates to reduced CO2 emissions of 6,500 metric tons. FIGURE 3 illustrates the new design configuration for shell exhaust recycle.

Ion Implant 3

The role of sub-atmospheric pressure gas sources

In redesigning the implant exhaust configuration, Russo and his team he relied on using only the safest gas packaging technology— sub-atmospheric gas sources, or SAGS.

These packages deliver gases below atmospheric pressure, greatly reducing the likelihood of a gas leak and providing the basis to redirect the shell exhaust back into the fab.

It is interesting to note that around the same time Russo published his first article on his new design, the National Fire Protection Agency (NFPA) adopted the SAGS classification for gas packages into the standard. The NFPA classified gas packages that store and deliver gas sub-atmospherically as SAGS Type I and packages that store gas under pressure but deliver gas sub-atmospher- ically as SAGS Type II. Both SAGS systems share a common feature—they require a process vacuum in order to deliver the toxic gas, virtually eliminating accidental gas releases (FIGURE 4).

Ion Implant 4

The initial planning for re-configuring the shell exhaust system in the new design was done to take full advantage of the safety profile of the SAGS packages. Using traditional high pressure delivery systems in the new design wouldn’t have been prudent because of the higher gas leak potential and lower safety profile. Exclusively using SAGS technologies enabled the exhaust reduction program approach. Continuous efforts and success rely on doing everything possible to see that gas delivery is always sub-atmospheric and TI has taken precautions to ensure the gas delivery systems are consistently performing in this way.

Gas box exhaust reductions

The process of lowering implanter shell exhaust began over 12 years ago, and since then most TI tools have been fitted with this design. On its continued quest for reduced energy and costs, TI identified the gas box as being the next best opportunity.

The gas box exhaust, potentially containing hazardous materials, is sent through a scrubber before being released. Scrubbed (or acid) exhausts, therefore, consume more resources than shell exhaust and contribute more to the costs of fab operations.

Over the past few years, Texas Instruments and ATMI, now Entegris, providers of SAGS technologies, have teamed up to continue to look for efficiencies and safety measures in managing exhaust gas and energy usage in ion implant operations. After evaluating the energy reduction potential of the tool gas box exhaust, TI made modifications that led to reduced gas box exhaust rates of about 200 cfm, down from over 400 cfm. This resulted in an additional $800 savings per tool per year. Additional strategies to reduce gas box exhaust rates and improve overall safety are suggested below.

Building an integrated [smart] exhaust system

Today, ion implanters utilize dopant cylinders with manual valves that had their start when “lecture bottles” were first used 30 years ago—and space in the gas box was at a premium. Small cylinders and manual valves were standard. Even as solid source vaporizers were replaced, and the use of gases in larger cylinders became prevalent, the use of manual valves continued.

Interestingly, the Type 1 and Type 2 sub-atmospheric gas delivery cylinders used worldwide to supply implant dopant gases use manual valves. The presence of the manual valve presents a continuing risk because of the possibility of human error during installation and purging sequences which could result in a gas release, albeit small. Yet, there is still room to reduce risk and continue to improve safety through the application of “smart” solutions.

Ultimately, the cornerstone to minimizing the occurrence and impact of a gas leak is all about maintaining the system under sub-atmospheric conditions at all times. Operating under sub-atmospheric pressure entails the continuous monitoring of gas pressure(s) in the delivery manifolds and the ability to respond quickly if pre-set pressure thresholds are exceeded.

The use of normally closed pneumatic valves provides the means to isolate the toxic gas within the dopant cylinder should the delivery manifold deviate from sub-atmospheric pressure protocols. The normally closed condition also removes from consideration cases where valves are either poorly closed or over-torqued. Cylinder cycle purging can then be done automatically, more efficiently and without the possibility of backfilling purge gas into the cylinder.

Varying the gas box flow rate

The ability to minimize the smallest of leaks would allow the gas box to be exhausted as a function of actual risk as opposed to continuously operating at a rate needed to mitigate projected worst-case scenarios. Controlling the gas box exhaust rate using a two position damper is one possible solution.

A two-position damper can control the gas box exhaust in either a low or high flow mode. The normal or reduced exhaust condition is allowed when all of the dopant delivery cylinders are showing a sub-atmospheric pressure condition or all of the cylinder valves are closed. Interlocks initiate the high flow rate any time the gas box door is opened, such as during cylinder changes or maintenance periods, or when triggered by events such as toxic gas detection, smoke detector alarm or detection of a super-atmospheric pressure condition in the dopant delivery manifold. It is estimated that the exhaust system would operate in the low flow mode >95% of the time.

With SAGS, a nominal rate of 40 cfm can be sufficient to satisfy regulations providing a 90% reduction in gas box exhaust requirements.

Taking the next step forward

TI justified recirculating the ion implanter shell exhaust within the fab based on a thorough risk analysis built around using SAGS technology. Over the last decade, they refined the practice and proliferated it across new fab installations, significantly reducing capital require- ments for make-up air.

Developing an integrated exhaust system can ultimately reduce implant make-up air requirements by 98%— without compromising safety. Operating costs associated with the lower exhaust have been proportionately reduced,along with carbon dioxide emissions.

Further advances in exhaust/energy reduction are possible via a partnership between toolmakers, dopant suppliers and fab designers to incorporate an integrated exhaust system for ion implanters, and possibly other tools. It begins with insuring operating gas delivery is under sub-atmospheric pressure conditions all the time.

Future changes may include:

1. Adding pneumatic valve operators to the dopant cylinders

2. Variably exhausting the gas box proportional to actual risk conditions

Outstanding economic and environmental gains can continue to be made – and new standards created – if manufacturers, equipment makers and suppliers work together to envision the possibilities. As an industry, and as responsible corporate citizens, working together to pursue these types of opportunities can reduce energy consumption and exhaust while improving overall process safety.

Based on text, graphics and data originally presented at the 26th Annual IEEE/SEMI Advanced Semiconductors Manufacturing Conference (ASMC 2015), May 3-6, 2015, Saratoga Springs, New York.

STEVEN BALLANCE, P.E., is a facilities engineer at Texas Instruments, Dallas, TX. KARL OLANDER and JOE SWEENEY are with the Electronic Materials division of Entegris, Danbury, CT.

A new 5D solution utilizes multiple types of metrology systems to identify and control fab-wide sources of pattern variation, with an intelligent analysis system to handle the data being generated.

BY ROBERT CAPPEL and CATHY PERRY-SULLIVAN, KLA-Tencor Corp., Milpitas, CA

In order to produce IC devices at sub-16nm design nodes, semiconductor manufacturers are integrating many novel technologies, including multiple patterning, spacer pitch splitting, 3D logic and memory structures, new materials and complex reticles. The challenges associated with these innovative technologies place huge cost strains on the semiconductor industry. In this environment, high yields and fast ramps play critical roles in helping semiconductor manufacturers maintain profitability.

Process control has helped IC manufacturers accelerate yield over the last 30 years, providing the inspection and metrology technologies necessary for early identification of critical process issues. As IC device design nodes shrunk over time, process control systems kept pace through the implementation of innovative technologies that enabled detection of defects and process variations that inhibited yield and reliability. For example, KLA-Tencor’s optical wafer inspection systems have evolved over the past 30 years from using a tungsten-halogen light source, off-the-shelf microscope objectives and an off-the-shelf sensor to utilizing a laser-pumped broadband light source that is brighter than the sun, optics that are as complex as those used in steppers and custom sensors that are 1,000 times faster than a digital camera. Today’s broadband plasma optical patterned wafer inspectors are now capable of detecting 10nm defects—only four times larger than the diameter of a DNA strand. Moreover, the detection of these defects across all die on a 300mm wafer is equivalent to finding hundreds of coins dispersed across an area the size of the state of California from many miles in space—in an hour.

The multiple technologies used to produce today’s leading-edge devices create challenges for process control. Inspection and metrology systems need to be able to extract signal from smaller defects and process/ pattern variations, often on complex 3D structures with high-aspect ratio features. With novel materials and increased process variability, this signal extraction needs to happen in an environment of increased background noise. In addition, with multiple patterning and more process steps, inspection and metrology tools need to provide increased productivity to enable sufficient production monitoring to detect excursions. For example, FinFETs produced using multiple patterning techniques require process control strategies that utilize advanced inspection and metrology systems that integrate design information and produce the sensitivity necessary to help address smaller critical defects, 3D structures and narrow process windows. In addition, the inspection and metrology solutions must also provide improved productivity to help cost-effectively monitor and control the increased number of process steps associated with fabricating the FinFETs using multiple patterning.

These challenges drive the innovation that produces the unique process control technologies and solutions that find design, patterning or process issues early. This capability is essential for IC manufacturers as it enables production of today’s leading-edge and future technologies with maximum yield and device performance at reduced risk and cost.

The value of process control

The inspection and metrology systems at the core of process control are not used to fabricate IC devices, as they do not add or remove materials or create patterns. However, rather than being superfluous steps in IC manufacturing, process control is critical for making high-yielding, reliable devices. By finding defects and measuring critical parameters, inspection and metrology systems monitor the hundreds of steps required to manufacture a device. These process control measurements help fab engineers identify and troubleshoot process issues when there is an excursion. Process control is fundamentally tied to yield as it would be near impossible for fabs to pinpoint process issues that affect yield without inspection and metrology.

Achieving a fast yield ramp to get products to market quickly is essential for chipmakers—any delay in yield ramp affects revenue [1] and can affect future investment in R&D and the release of next-gener- ation products. By taking steps such as implementing capable process control strategies, a fab can attain shorter development times, faster manufacturing ramps and improved production yield. In fact, the value chipmakers can attain from process control is realized in many forms, including: strong return on investment; lower manufacturing costs and risks; increased revenues; faster time to money; improved cycle times; greater profits; and, business continuity.

In order to provide deeper insight into the value of process control, the ten fundamental truths of process control (FIGURE 1) were compiled. Each of the fundamental truths has been introduced in a series of Process Watch articles [2-10], including details on the applications of these truths to semiconductor IC manufacturing. By understanding the fundamental nature of process control through these ten truths, fabs can implement strategies to identify critical defects, find excursions and reduce sources of variation.

Yield 1

Given the increasing complexity of advanced devices and process integration, one of the most critical fundamental truths that fabs must account for going forward is: Process control requirements increase with each design rule [9]. As FIGURE 2 shows, the number of process steps increases dramatically starting with the 16/14nm design node. As the number of process steps increases, all steps must be held to a higher standard for excursions, defect density and variability. If the per-step yield stays constant at the level achieved for the 28nm node, then the predicted cumulative yield will drop with each smaller design node (FIGURE 3). Because of this compounding nature of yield loss, fabs must obtain tighter controls and lower defect density at each individual process step. This drives the need for new process control strategies that not only detect yield- critical defects and subtle process variations, but also allow engineers to increase inspection and metrology sampling. Such process control capability enables direct monitoring of the increased number of process steps and quick detection of excursions that can have a tremendous impact on wafer manufacturing costs.

Yield 2

FIGURE 3. With increasing process steps, the predicted cumulative yield will drop for advanced design nodes if the per- step yield stays constant at 28nm levels.

FIGURE 3. With increasing process steps, the predicted cumulative yield will drop for advanced design nodes if the per- step yield stays constant at 28nm levels.

 

Strategy for future process control challenges

In moving to sub-16nm design nodes, semiconductor manufacturers are faced with many challenges to Moore’s Law. On the technical side, there are the complexities associated with the integration of novel technologies (e.g., multiple patterning, 3D structures, new materials, complex reticles, increased number of process steps). On the economic side, the convergence of these multiple technologies creates increased pressure on fabs to maintain control of costs. Transistor costs are related to the scaling factor, manufacturing costs and yields. With rising fab, design, development and lithography costs, the best solution semiconductor manufacturers have to achieving the cost goals of Moore’s Law is accelerating yield.

In trying to achieve faster yield ramps, IC manufacturers must confront the many issues surrounding the robustness of their design and process window. On the design side, engineers must be able to find and assess design weak points in order to drive improvements that ensure the device design and fabrication techniques are stable for production. At the sub-16nm design nodes, the required pattern overlay budgets are ≤4.5nm, critical dimension specifications are ~2nm and process windows are extremely narrow. In order to drive the changes necessary to achieve these tight patterning specifications (FIGURE 4), engineers need to understand fab-wide sources of patterning error and the impact of variations on process windows. In this environment of tackling difficult technical challenges within cost targets, process control is essential.

FIGURE 4. For advanced multi-patterning technologies, the sources of patterning errors are fab-wide—occurring both inside and outside the lithography cell. In order to meet the incredibly tight specifications for overlay and critical dimensions, engineers must look at reducing the fab-wide sources of process variation.

FIGURE 4. For advanced multi-patterning technologies, the sources of patterning errors are fab-wide—occurring both inside and outside the lithography cell. In order to meet the incredibly tight specifications for overlay and critical dimensions, engineers must look at reducing the fab-wide sources of process variation.

Developing the necessary process control solutions is challenging—requiring both tremendous innovation and close collaboration among multiple sectors within the semiconductor industry. Not only is it necessary to develop novel technologies that provide advanced inspection and metrology system performance, it is also essential to pursue innovation towards comprehensive process control solutions—strategies that tie process control systems together, so they work in concert in the fab with intelligent analysis systems handling the complex, high-volume data being generated. These process control “system of systems” can help fabs achieve faster yield ramp through quick design verification and process window discovery, expansion and control.

Two examples of process control solutions are shown in FIGURE 5. With defect discovery the goal is to detect and identify yield-critical defects that highlight design issues during development and process drift during production. The discovery system leverages design information through NanoPoint technology on the 2920 Series broadband plasma optical defect inspection systems to find critical pattern defects that affect yield the most dramatically. The Surfscan SP5 unpatterned wafer inspection system aids in preventing yield issues by detecting tiny substrate defects that can distort the subsequent films and pattern structures on advanced 3D devices, such as FinFETs and vertical NAND flash. Finally, the eDR-7110 e-beam review and classification system identifies the defects detected by the 2920 Series and Surfscan inspectors. By producing comprehensive information on critical nanoscale defects, the defect discovery solution helps fab engineers characterize, optimize and monitor their advanced processes to accelerate time-to-market.

FIGURE 5. The future of process control involves “system of systems” solutions which tie together multiple inspection and metrology systems with intelligent data analysis. Shown are two examples of process control solutions: KLA-Tencor’s defect discovery solution on the left and KLA-Tencor’s 5D patterning control solution on the right.

FIGURE 5. The future of process control involves “system of systems” solutions which tie together multiple inspection and metrology systems with intelligent data analysis. Shown are two examples of process control solutions: KLA-Tencor’s defect discovery solution on the left and KLA-Tencor’s 5D patterning control solution on the right.

FIGURE 5. The future of process control involves “system of systems” solutions which tie together multiple inspection and metrology systems with intelligent data analysis. Shown are two examples of process control solutions: KLA-Tencor’s defect discovery solution on the left and KLA-Tencor’s 5D patterning control solution on the right.

The goal of the 5D patterning control solution [11, 12] is to help IC manufacturers obtain optimal patterning on advanced devices. With today’s complex multiple patterning and spacer pitch splitting technologies, patterning errors are no longer tied to the lithography cell. Patterning errors can come from fab-wide sources, such as wafer distortion caused by CMP that directly relates to scanner focus errors. The 5D solution utilizes multiple types of metrology systems to identify and control fab-wide sources of pattern variation, with an intelligent analysis system to handle the data being generated. A critical component of this system solution is the ability to feed back and feed forward metrology data (FIGURE 6). Feedback loops have been utilized for many design nodes. For example, Archer 500LCM overlay metrology systems identify patterning errors and feed back information to the lithography module and scanner to improve the patterning of future lots. But, there is also the opportunity to feed forward information that can further improve patterning. For example the Wafer-Sight PWG patterned wafer geometry measurement system can measure wafer shape after processes such as etch and CMP and this data can be fed forward to the scanner to improve patterning [13 – 15]. Overall, this 5D solution—utilizing fab-wide, comprehensive measurements and an intelligent combination of feedback and feed forward control loops—can help fab engineers expand their process windows, reduce variation within those windows, and ultimately obtain better patterning results.

FIGURE 6. KLA-Tencor’s 5D patterning control solution implements multiple data loops to help optimize patterning. Existing feedback loops (blue) have existed for several design nodes and detect and compensate for process variations. New, optimized feedback loops (green) provide earlier detection of process changes. Innovative feed forward loops (orange) utilize metrology systems to measure variations at the source, then feed that data forward to subsequent process steps.

FIGURE 6. KLA-Tencor’s 5D patterning control solution implements multiple data loops to help optimize patterning. Existing feedback loops (blue) have existed for several design nodes and detect and compensate for process variations. New, optimized feedback loops (green) provide earlier detection of process changes. Innovative feed forward loops (orange) utilize metrology systems to measure variations at the source, then feed that data forward to subsequent process steps.

These comprehensive process control solutions are a critical part of IC industry success, enabling high yields and fast ramps by allowing engineers to more quickly and cost-effectively address a broad range of process issues. Going forward, it is essential to maintain an ecosystem of innovation and collaboration that ensures novel process control systems and solutions are developed that address IC process and cost challenges.

References

1. “The Chip Insider,” VLSI research, March 26, 2013.
2. PriceandSutherland,“Process Watch:You Can’t Fix What You Can’t Find,” Solid State Technology, July 2014. http://electroiq.com/blog/2014/07/process-watch-the-10-fundamental-truths-of-
process-control-for-the-semiconductor-ic-industry/
3. PriceandSutherland,“Process Watch:Sampling Matters,”
Semiconductor Manufacturing and Design, September 2014. http://semimd.com/blog/2014/09/15/process-watch-sampling-matters/
4. PriceandSutherland,“Process Watch:The Most Expensive Defect,” Solid State Technology, December 2014. http:// electroiq.com/blog/2014/12/the-most-expensive-defect/
5. Sutherland and Price, “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014. http:// electroiq.com/blog/2014/12/process-watch-fab-managers-dont- like-surprises/
6. Sutherland and Price, “Process Watch: Know Your Enemy,” Solid State Technology, March 2015. http://electroiq.com/ blog/2015/03/process-watch-know-your-enemy/
7. SutherlandandPrice,“Process Watch:Time is The Enemy of Profitability,” Solid State Technology, May 2015. http://electroiq.com/blog/2015/05/process-watch-time-is-the-enemy-of-profitability/
8. Price and Sutherland, “Process Watch: The Most Expensive Defect, Part 2,” Solid State Technology, July 2015. http://electroiq.com/blog/2015/07/process-watch-the-most-expensive-defect-part-2/
9. Price and Sutherland, “Process Watch: Increasing Process Steps and the Tyranny of Numbers,” Solid State Technology, July 2015. http://electroiq.com/blog/2015/07/process-watch-increasing-process-steps-and-the-tyranny-of-numbers/
10. Sutherland and Price, “Process Watch: Risky Business,” Solid State Technology, September 2015. http://electroiq.com/blog/2015/09/process-watch-risky-business/
11. Korczynski, “Overlay Metrology Suite for Multiple Patterning,” Semiconductor Manufacturing and Design, August 2014. http://semimd.com/blog/2014/08/26/overlay-metrology-suite-for-multiple-patterning/
12. Moyer, “Feed It Forward (And Back),” Electronic Engineering Journal, September 2014. http://www.eejournal.com/archives/ articles/20140915-klat5d/
13. Lee et al, “Improvement of Depth of Focus Control using Wafer Geometry,” Proc. of SPIE, Vol. 9424, 942428, 2015.
14. Tran et al, “Process Induced Wafer Geometry Impact on Center and Edge Lithography Performance for Sub 2X nm Nodes,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.
15. Morgenfeld et al, “Monitoring process-induced focus errors using high resolution flatness metrology,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.

ROBERT CAPPEL is Senior Director and CATHY PERRY-SULLIVAN is Technical Marketing Manager, Global Customer Organization, KLA-Tencor Corporation Milpitas, CA.

The health of the IC industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong IC market growth without at least a “good” worldwide economy to support it. Consequently, IC Insights expects annual global IC market growth rates to closely track the performance of worldwide GDP growth. In the recently released The McClean Report 2016, IC Insights forecasts 2.7% global GDP growth for 2016, only marginally ahead of what is considered to be the recession threshold of 2.5% growth.

Figure 1 puts the worldwide electronics and semiconductor industries into perspective. The top figure, worldwide GDP, represents all global economic activity. Essentially, the worldwide total available market (TAM) for business (i.e., GDP) was $78.4 trillion in 2015.

In many areas of the world, local economies have slowed. For example, economic growth in China slipped below 7% in 2015. China, which is the leading market for personal computers, digital TVs, smartphones, new commercial aircraft, and automobiles, is forecast to lose more economic momentum in 2016. Its GDP is forecast to increase 6.3% in 2016, which continues a slide in that country’s annual GDP growth rate that started in 2010.

While the U.S. economy is far from perfect, it is currently one of the most significant positive driving forces in the worldwide economy. The U.S. accounted for 22% of worldwide GDP in 2015. U.S. GDP is forecast to grow 2.5% in 2016. Given its size and strength, the U.S. economy greatly influences overall global GDP growth. An improving employment picture and the low price of oil are factors that should positively impact the U.S. economy in 2016.

Other noteworthy industry highlights from the 2016 edition of The McClean Report include the following:

Global semiconductor sales decreased 1% in 2015 but are forecast to grow 4% in 2016. IC Insights expects the worldwide IC market to increase 4% in 2016, and sales of optoelectronics, sensors, and discrete (OSD) devices collectively to register 5% growth.

Figure 1

Figure 1

• Total semiconductor unit shipments (including IC and OSD devices) reached almost 840-billion units in 2015 and are expected to exceed one trillion units in 2018. After increasing 4% in 2015, IC unit shipments are forecast to grow 5% in 2016. Analog devices are forecast to account for 53% of total IC unit shipments in 2016.

• A stable IC pricing environment is expected through 2020 due in part to fewer suppliers in various IC markets (i.e., DRAM, MPU, etc.), lower capital spending as a percent of sales, and no significant new IC manufacturers entering the market in the future (the surge of Chinese IC companies that entered the market in the early 2000’s is assumed to be the last large group of newcomers.

Semiconductor industry capital spending grew to $65.9 billion in 2015. IC Insights forecasts semiconductor capital spending will decrease 1% in 2016. Spending on flash memory and within the foundry segment is forecast to increase in 2016 but spending for all other market segments, including DRAM, is expected to decline. Semiconductor capital spending as a percent of sales is forecast to remain in the mid- to high-teens range through 2020. IC Insights believes spending at this level will not lead to an industry-wide overcapacity during the forecast period.

Semiconductor R&D spending increased 1% in 2015 to new record high of $56.4 billion. Intel dedicated $12.1 billion to R&D in 2015 (24.0% of sales) to remain the largest semiconductor R&D spender in 2015. R&D spending at TSMC, the industry’s biggest pure-play foundry rose 10% in 2015, ranking it 5th among top R&D spenders. TSMC joined the group of top-10 R&D spenders for the first time in 2010, giving an indication of just how important TSMC and other pure-play foundries have become to the IC industry with continuing technological progress.

Further trends and analysis relating to the IC market are covered in the main 400-plus page 2016 edition of The McClean Report.

Technavio analysts forecast the global semiconductor packaging and assembly equipment market to post a CAGR of 4.7% by 2020, according to their latest report.

The research study covers the present scenario and growth prospects of the global semiconductor packaging and assembly equipment market for 2016-2020. To calculate the market size, the report considers the revenue generated from the sale of die-level and wafer-level packaging and assembly equipment to semiconductor manufacturers.

Technavio’s report segments the market in two different main types of equipment:

  • Global die-level packaging and assembly equipment
  • Global wafer-level packaging and assembly equipment

“In 2015, die-level packaging and assembly equipment was the most prominent segment of the global semiconductor packaging and assembly equipment market, accounting for 60.6% of the total market. The primary reason behind the segment’s market dominance is the increasing demand for the application process, baseband, and SoCs, which are integrated in mobile devices. Wafer-level packaging and assembly equipment accounted for 39.42% of the overall market in 2015,” said Technavio lead semiconductor equipment analyst Asif Gani.

Technavio’s report highlights four major factors that are influencing the growth of the global semiconductor packaging and assembly equipment market:

  • Rising demand for polymer adhesive wafer bonding equipment
  • Growing application of semiconductor ICs in the IoT
  • Increasing complexity of semiconductor IC designs
  • Increasing miniaturization of electronic devices

Rising demand for polymer adhesive wafer bonding equipment

The demand for polymer adhesive wafer bonding equipment is rising due to the increasing adoption of advanced packaging applications like TSV, 2.5D and 3D ICs, stacked die packaging, and MEMS packaging. Polymer adhesive wafer bonding equipment provides reliable thinning and backside processing of the stacked dies. In addition, it lowers the cost of TSV integration. The rising demand for polymer adhesive wafer bonding equipment will therefore have a moderately high impact on the market for semiconductor devices, as this equipment supports 3D packaging, which is the future of the semiconductor packaging and assembly industry.

Growing application of semiconductor ICs in the IoT

An estimated 30 billion devices will be connected through the IoT by 2020. The IoT enables devices to collect data using sensors and actuators and transmit data to a centralized location on a real-time basis. The IoT has been extensively adopted in multiple market segments (consumer electronics, automotive, medical) and will likely drive the market for semiconductor devices and associated equipment during the forecast period.

The IoT requires the application of ultra-low power (ULP) processors. Therefore, to reduce the size of the processor chip and to fit in compact devices like wearables, development of new packaging technologies is necessary. The growing application of semiconductor ICs in the IoT will have a moderately high impact on semiconductor device manufacturers, as it is estimated that the market for semiconductors and sensors for IoT applications will cross the USD 50 billion mark by the end of 2020. Manufacturers will have to either increase their production capacity or revamp their technologies to match the changing technological environment.

Increasing complexity of semiconductor IC designs

Due to the increasing functionalities of consumer electronics, there is an increasing need for multifunctional ICs. Semiconductor manufacturers have addressed this need by developing sophisticated architecture and designs for semiconductor ICs. Manufacturing semiconductor ICs based on these designs is complicated, which has created a demand for upgraded packaging and assembly equipment.

“The increasing complexity of the semiconductor wafer design will have a moderate impact on semiconductor device manufacturers, as they must invest in packaging and assembly equipment to maintain the performance of semiconductor ICs,” said Asif.

Increasing miniaturization of electronic devices

The increasing demand for compact electronic devices used in multiple sectors like telecommunications and automotive has led to further miniaturization of semiconductor ICs. With advances in technology like 3D ICs and MEMS, as well as changes in the design of ICs such as finer patterning, electronic equipment is becoming more compact and user-friendly. MEMS is a technology used for miniaturization of chips by the process of microfabrication.

The mobile sector is driving production and market growth; however a new market driver, IoT is on the horizon and is expected to have a significant impact on the advanced packaging industry.

“IoT driven semiconductor industry consolidation, is reflecting into a highly dynamic advanced packaging landscape,” commented Andrej Ivankovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole Développement.

And he added: “Numerous packaging options developed by the industry leaders, are being explored as new IoT applications arise.”

In parallel, Yole Développement’ analysts highlight the noteworthy demand for advanced packaging solutions and the increasing number of shipped wafers: focus is turning to integration and wafer level packages to enable a functionality driven roadmap and revive the cost/performance curve.

ap platforms

Yole Développement (Yole), the “More than Moore” market research and strategy consulting reinforces its market positioning within the advanced packaging area with the release of its first report “Status of the Advanced Packaging Industry”This first edition brings a thorough analysis including dynamics and disruptions of the market, market forecasts per packaging platform and device type from 2014 to 2020, market shares…This analysis also presents a detailed analysis of the advanced packaging supply chain, financial evolutions and mergers & acquisitions. Yole’s advanced packaging team proposes a packaging technology segmentation and highlights with this new analysis, the impact of Internet of Things and the adoption of 2.5D/3D, Fan-Out and Fan-In solutions.

“A transformation of the semiconductor industry is under way,” said Andrej Ivankovic, Yole. “Advanced packaging is part of the scaling and functionality roadmaps.”

The latest events in the technology market indicate that 2015 marks the beginning of an exciting new era for the IT and electronics industry. At semiconductor supply chain level, the industry entered a profound consolidation phase with high M&A activity reshaping the business landscape. FEOL device scaling and related cost reduction are deviating from the path they followed for the past few decades, with Moore’s law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially.

As the smartphone market matures, new forces are appearing in the form of IoT. While the mobile sector continues to drive the market, the scent of IoT is already spreading in the consumer sector with products such as wearables and first smart home appliances. IoT market, application and technology segmentation has begun. Companies across the industry are restructuring, merging and acquiring in order to adjust their portfolio, enable a complete platform offer and establish leading positions on the market.

Yole’s advanced packaging analysts also identified other market dynamics. They announced:
•   The foundry involvement is no longer a dent in advanced packaging production.
•   Increased activity of Chinese capital on the market.
•   And more

At the level of technology, as profitability of FEOL scaling options remains uncertain and IoT promises application diversification, the spotlight is now turning to advanced packages for cost reduction, performance boost and functional integration.

In order to answer market demands, the advanced packaging segment focuses on integration and WLP. Emerging packages such as Fan-Out WLP, 2.5D/3D IC and related System-in-Package solutions aim to bridge the gap and revive the cost/performance curve.

How will the advanced packaging industry evolve, which changes in the semiconductor supply chain are taking place and which packaging technologies will be most critical in the years to come? Yole proposes with this new technology and market analysis, a deep understanding of the advanced packaging technical and market challenges. Under this new report, the market research and strategy consulting company brings a thorough analysis of the advanced packaging industry and its future development covering platforms Fan-Out WLP, Fan-In WLP, Flip Chip and 2.5D / 3D.

Worldwide semiconductor revenue totaled $333.7 billion in 2015, a 1.9 percent decrease from 2014 revenue of $340.3 billion, according to preliminary results by Gartner, Inc. The top 25 semiconductor vendors’ combined revenue increased 0.2 percent, which was more than the overall industry’s growth. The top 25 vendors accounted for 73.2 percent of total market revenue, up from 71.7 percent in 2014.

“Weakened demand for key electronic equipment, the continuing impact of the strong dollar in some regions and elevated inventory are to blame for the decline in the market in 2015,” said Sergis Mushell, research director at Gartner. “In contrast to 2014, which saw revenue growth in all key device categories, 2015 saw mixed performance with optoelectronics, nonoptical sensors, analog and ASIC all reporting revenue growth while the rest of the market saw declines. Strongest growth was from the ASIC segment with growth of 2.4 percent due to demand from Apple, followed by analog and nonoptical sensors with 1.9 percent and 1.6 percent growth, respectively. Memory, the most volatile segment of the semiconductor industry, saw revenue decline by 0.6 percent, with DRAM experiencing negative growth and NAND flash experiencing growth.”

Intel recorded a 1.2 percent revenue decline, due to falls in PC shipments (see Table 1). However, it retained the No. 1 market share position for the 24th year in a row with 15.5 percent market share. Samsung’s memory business helped drive growth of 11.8 percent in 2015, and the company maintained the No. 2 spot with 11.6 percent market share.

Table 1. Top 10 Semiconductor Vendors by Revenue, Worldwide, 2015 (Millions of Dollars)

Rank 2014

Rank 2015

Vendor

2014 Revenue 

2015 Estimated Revenue 

2014-2015 Growth (%)

2015 Market Share (%)

1

1

Intel

52,331

51,709

-1.2

15.5

2

2

Samsung Electronics

34,742

38,855

11.8

11.6

5

3

SK Hynix

15,997

16,494

3.1

4.9

3

4

Qualcomm

19,291

15,936

-17.4

4.8

4

5

Micron Technology

16,278

14,448

-11.2

4.3

6

6

Texas Instruments

11,538

11,533

0.0

3.5

7

7

Toshiba

10,665

9,622

-9.8

2.9

8

8

Broadcom

8,428

8,419

-0.1

2.5

9

9

STMicroelectronics

7,376

6,890

-6.6

2.1

12

10

Infineon Technologies

5,693

6,630

16.5

2.0

Others

157,992

153,182

-3.0

41.2

Total

340,331

333,718

-1.9

100

Source: Gartner (January 2016)

“The rise of the U.S. dollar against a number of different currencies significantly impacted the total semiconductor market in 2015,” said Mr. Mushell. “End equipment demand was weakened in regions where the local currency depreciated against the dollar. For example in the eurozone, the sales prices of mobile phones or PCs increased in local currency, as many of the components are priced in U.S. dollars. This resulted in buyers either delaying purchases or buying cheaper substitute products, resulting in lower semiconductor sales. Additionally, Gartner’s semiconductor revenue statistics are based on U.S. dollars; thus, sharp depreciation of the Japanese yen shrinks the revenue and the market share of the Japanese semiconductor vendors when measured in U.S. dollars.”

The NAND market continued to deteriorate throughout the year. As a result, revenue grew only 4.1 percent in 2015, fueled by elevated supply bit growth that resulted in an aggressive pricing environment. The tumultuous NAND pricing environment rippled through most of the NAND solutions, particularly solid-state drives (SSDs), which continue to encroach on hard-disk drives (HDDs). The ensuing price war in SSDs further pressured the profitability of the NAND flash makers amid the biggest technology transition in flash history — 3D NAND. While 3D NAND commercialization was modest, it was limited to only one vendor — Samsung. Modest revenue gains have not stopped investment in NAND flash and 3D technology, with all vendors continuing to spend aggressively in the technology and most with new fabs.

After 32.0 percent revenue growth in 2014, the DRAM market hit a downturn in 2015. An oversupply in the commodity portion of the market caused by weak PC demand led to severe declines in average selling prices (ASPs), and revenue contracted by 2.4 percent compared with 2014. The oversupply and the extent of ASP declines could have been significantly worse if Micron Technologies’ bit growth had performed in line with its South Korean rivals. Fortunately for the market, the company saw negative bit growth due to its transition to 20 nm, sparing the industry from an even more severe downturn.

Additional information is provided in the Gartner report “Market Share Analysis: Semiconductors, Worldwide, Preliminary 2015 Estimates.”