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POET Technologies Inc., a designer, developer and manufacturer of optoelectronic devices, including light sources, passive wave guides, and Photonic Integrated Circuits (PICs) for the data- and tele-communication markets, today announced that it had entered into an agreement with the highly-respected firm, MillView Photonics, Inc. (“MillView”) to establish a collaborative design center in Ottawa, Ontario, Canada.

MillView was established two years ago by Dr. Trevor J. Hall, Professor in the School of Electrical Engineering & Computer Science and Founding Director of the Centre for Research in Photonics at the University of Ottawa. Along with his team, which includes Peng Liu, senior passive component designer, Mihail Dumitrescu, senior active component designer, and supported by doctoral and postdoctoral graduate engineers, MillView serves clients in photonics research, simulation, design and process development.

The agreement between the two companies brings together in one lab the MillView team, including Dr. Hall, additional staff from MillView, and three PhD-level photonics engineers from POET.  The team is also supported by POET’s Senior Vice President, Dr. William Ring, and additional POET design engineering resources.

Commenting on the collaboration agreement, Dr. Trevor Hall, a graduate of Cambridge University, noted, “MillView Photonics was founded along the same model as Cambridge Consultants where I worked on my return to Cambridge following PhD studies at University College London, U.K.  Cambridge Consultants tapped into a vast reservoir of talent to solve real-world design and engineering challenges utilizing academic/industry partnerships.  MillView is similarly situated to bring in the specific talent needed to address and solve a broad range of engineering challenges in photonics.  We are all really gratified to be working as a team with POET Technologies.  POET’s unique Optical Interposer™ platform has tremendous market potential, and we are all committed as one team to its success.”

POET’s Chief Executive Officer, Dr. Suresh Venkatesan, commented: “POET’s partnership with MillView rapidly expands our effort with experienced photonics engineering talent and substantial simulation and design capacity.  In line with our stated strategy, we have assembled a team in one place dedicated to one goal – the design and development of waveguides and filters for our Optical Interposer platform. In addition, this places POET squarely in both a region and University where photonics design and development are vibrant and pervasive.  The number of companies engaged in the photonics industry and the quality of the engineering talent available is extraordinary.  We are very appreciative for the reception that Dr. Hall has extended to POET that allows us to function as one team.”

2019 TSX Venture 50
POET also announced today that the Company has been named to the 2019 TSX Venture 50 list, a ranking of the top performers on the TSX Venture Exchange over the past year. The TSX Venture 50 ranking is comprised of ten companies from each of the five industry sectors represented on the TSX Venture Exchange. Companies are selected based on three equally weighted criteria: market capitalization growth, share price appreciation and trading volume.

POET’s Executive Vice President and Chief Financial Officer, Thomas Mika, commented, “We are gratified to be recognized as one of the top technology companies on the TSX Venture Exchange for 2019. Last year was a transformational year for the Company, highlighted by our first orders for our POET Optical Interposer-based solutions from leading global communications companies targeting data communications applications. Additionally, we recently received an offer to purchase our DenseLight subsidiary as part of our plan to pursue a fab-light strategy with a less capital-intensive business model. In fact, today’s announced collaboration agreement with MillView for combining design capabilities also furthers these efforts by leveraging key strategic partnerships to establish POET as a world-class organization with leading optical products. We look forward to building on our growing momentum in 2019 as we realize the substantial commercial potential for POET’s technology.”

pSemi Corporation today announced that its parent company and executive leadership has approved the recommendation of Chairman and Chief Executive Officer Jim Cable for an evolution of the company’s senior leadership structure.  Under the new structure, the company’s current VP of Product Marketing, Sumit Tomar, will succeed Jim as CEO, effective July 1, 2019.  Jim will continue as Chairman and Chief Technology Officer.  In addition, Jim will remain as global semiconductor R&D director for the parent company Murata Manufacturing.

“I am very proud of what we have accomplished here at pSemi Corporation.  In our over 30 years of innovation, we have consistently pushed the envelope of technology.  Now it is time to ensure we can continue to compete just as strongly in the future.  To that end, I have selected an internal candidate to succeed me as CEO,” says Jim Cable.  “I have watched Sumit in action, he knows our company and I am 100 percent committed to a successful transition for him and the company. We did an extensive external search and decided that the right choice was already here.”

Tomar is a 20-year industry veteran with a proven track record of bringing successful products to the market.  An expert in the RF ecosystem, Tomar has a solid understanding of RF products and has driven product execution from inception to production for hundreds of market-shaping products. From 2012 to 2016, Tomar served as the general manager of Qorvo’s wireless infrastructure business unit. In addition, he worked in RF product management at Texas Instruments, Sierra Monolithics and Skyworks. His product marketing experience spans 4/5G smartphone and radio access networks, automotive semiconductors, 802.11ax access points, SDN/NFV for data centers, and machine learning and artificial intelligence for mobile edge networks. In 2016, he co-founded C-RAN Inc., a startup that is developing a 5G RF system prototype. Tomar holds a Master of Science in electrical engineering and completed the StanfordExecutive Management Program. He joined pSemi Corporation in August of 2017 as the Vice President of Product Marketing.  “Sumit has been instrumental in managing our relationship with Murata to ensure that we support our parent company while continuing to innovate new products in the RF space,” continues Cable.

“Murata believes that successful succession planning requires careful consideration and attention to ensure a strong talent pipeline,” says Norio Nakajima, senior executive vice president and board member for Murata Manufacturing. “Jim’s selection of Sumit is an ideal example of outstanding succession planning.  I have had the pleasure of watching Sumit in action and I am convinced he is the right person to succeed Jim.”

Electro Scientific Industries (ESI), a division of MKS Instruments, Inc. (NASDAQ:MKSI) and an innovator in laser-based manufacturing solutions for the micro-machining industry, today announced an order for its recently-released CapStone laser drilling solution for processing flexible printed circuits (FPC). The order follows an extensive on-site system evaluation at Compeq Manufacturing, Huizhou, China, where CapStone delivered exceptional throughput and performance. Similar evaluations are underway at other major manufacturers where systems have already been qualified for production.

“Our testing and evaluation process for CapStone has been rigorous and extensive,” said Cathay Wu, director, purchasing, Material Division, Compeq. “We have processed thousands of panels over the last few months with the CapStone system. We evaluated the system on a wide range of applications and material stacks, as well as numerous via types and sizes—in both panel and roll-to-roll processes—and achieved excellent yield. CapStone showed significant increases in throughput and savings in cost-per-panel, and has met or exceeded our expectations. We look forward to leveraging CapStone for a number of applications and taking advantage of its throughput and yield to stay competitive in this very demanding market.”

“Capstone offers twice the throughput of our previous-generation system while maintaining yields, increasing uptime and significantly reducing maintenance costs,” said John Williams, ESI’s vice president of marketing. “These all translate directly into greater productivity and lower cost per panel. In the simplest analysis, doubling throughput doubles return on investment and halves the payback period.”

“Since we put our first CapStone systems in the field, we have processed over a hundred thousand panels,” Williams continued. “All systems are currently qualified and running in high-volume production. Given the cost-driven nature of the printed circuit board (PCB) processing industry, and CapStone’s extraordinary value proposition, the system continues to generate significant interest and early customer adoption. We are looking forward to finalizing the placement of additional systems as the market learns what CapStone can do.”

Developed by ESI, the CapStone system is optimized to process the FPCs widely used in consumer electronics, such as smartphones and other handheld devices. Building on the proven ESI platform, CapStone’s new laser technology and control capabilities deliver breakthrough performance at twice the throughput of the previous-generation model, and with equivalent accuracy and precision in critical parameters such as via diameter and placement.

Soitec (Euronext Paris), a designer and manufacturer of innovative semiconductor materials, and Shanghai Simgui Technology Co., Ltd. (Simgui), a Chinese silicon-based semiconductor materials company, jointly announced today an enhanced partnership and an increase in annual production capacity of 200mm silicon-on-insulator (SOI) wafers from 180,000 to 360,000 at Simgui’s manufacturing facility in Shanghai, China, to better serve the growing global market for RF-SOI in mobile and Power-SOI products.

Since signing their original licensing and technology transfer agreement in May 2014, the companies have achieved high quality standards with Simgui mastering Soitec’s Smart Cut(TM) proprietary process to deliver world-class RF-SOI and Power-SOI products. Simgui’s strategic partnership with Soitec allows them to use the same tools and processes to deliver the same products meeting the same specifications.

This ramp up in production is a direct result of the close collaboration and customer focus of both partners to deliver high quality SOI products at high volume. To further advance this mission,  Simgui and Soitec have redefined their original financial agreement and specific roles regarding the 200 mm wafers produced by Simgui. Simgui will focus on SOI wafer manufacturing and Soitec will manage worldwide product resale. To meet increasing worldwide demand for 200mm SOI in response to the growing market for RF-SOI used in mobile front-end modules (FEM) and for Power-SOI used in automotive and consumer electronics, Simgui has invested in their Shanghai fabrication line to offer customers this increased production capacity. The fab is production ready, having been qualified by multiple key customers inside and outside China.

“We are very pleased to continue our long-standing history and manufacturing partnership with Simgui to secure 200 mm capacity for our customers in markets where RF-SOI is today a standard for RF FEM for 4G & 5G and Power-SOI shows strong growth,” said Dr. Bernard Aspar, Soitec’s Executive Vice President, Communications and Power Business Unit. “Soitec and Simgui are committed to serve this industry with the right level of capacity and product quality.”

“Through our industrial collaboration with Soitec, Simgui has proven the robustness and high-volume scalability of Soitec’s Smart Cut technology and we are pleased to announce this new step in our relationship and increase in production capacity to serve our existing and future customers,” said Dr. Jeffrey Wang, Simgui’s Chief Executive Officer. “China has design, wafer manufacturing and good momentum in the IC industry. We are committed to our strategic partnership with Soitec to keep advancing SOI as China’s key differentiator.”

eSilicon, a provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the achievement of multiple milestones related to the company’s growth in the tier one FinFET ASIC market, serving high-bandwidth networking, high-performance computing, AI and 5G infrastructure.

Critical requirements to serve these markets include leading-edge, high-performance, differentiating semiconductor IP that is validated in advanced process nodes, a track record of successful design and fabrication of complex, FinFET-class ASICs and expertise in the design and manufacture of 2.5D package assemblies, including the integration of HBM memory stacks.

In the fall of last year, eSilicon announced availability of its neuASIC™ IP platform for AI ASIC design. The innovative IP platform includes an HBM2 PHY and AI mega/giga cells, including a convolution engine and accelerator builder software, all verified in 7nm technology. In that same time frame, the company announced that its 56G long-reach 7nm DSP SerDes was available for licensing.

In January, 2019, eSilicon announced a new high-performance test system to facilitate customer validation of its SerDes IP. At the recent DesignConshow, eSilicon demonstrated the new test system and its SerDes driving a five-meter copper cable at 56Gbps with very low error rates. Several customer engagements are underway with this SerDes IP, and customer feedback is validating its best-in-class capabilities. Also in January, eSilicon announced the formation of a technical advisory board for its AI initiatives staffed by three prominent technologists from academia and industry.

The company is in active production bring-up with two FinFET designs, including 2.5D technology utilizing its HBM2 PHY. All performance parameters are being met and both designs are on track to achieve full-scale production this year. One of the designs represents the largest ASIC eSilicon has ever built. It is believed to be the largest chip the foundry has ever produced as well.

“Our customers demand best-in-class IP, advanced ASIC and packaging expertise and the resources and technical depth to facilitate production bring-up of the final device,” said Hugh Durdan, vice president of strategy and products at eSilicon. “I am pleased to say we are delivering on all fronts. Recently, a tier one customer reported that they were usually quite critical of all IP. They went on to say they could find nothing to criticize after detailed evaluation of our SerDes.”

eSilicon will be presenting “A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET” at ISSCC in San Francisco on February 18. The company will be demonstrating its SerDes live at ISSCC that day as well. You can also find eSilicon at OFC in San Diego from March 5-7 (booth #5416), where the company will present two high-speed SerDes demonstrations and a demonstration if its HBM2 PHY.

During IBM THINK 2019, IBM’s annual conference focused on technology and business, Samsung SDS announced it is continuing its collaboration with IBM in support of advancing Hyperledger Fabric, an open source cross-industry blockchain technology, with recent code contributions, research and a new white paper.

As a contributor to Hyperledger Fabric, Samsung SDS is working to improve fabric capabilities and actively contributing its new “Accelerator” code to the open source community. The new code is expected to significantly improve Hyperledger Fabric performance for specific use cases.

Samsung SDS is also making a new white paper available, “Accelerating Throughput in Permissioned Blockchain Networks,” co-written by IBM. The paper validates the applicability of Accelerator to Hyperledger Fabric, provides a roadmap and also illustrates performance improvement in terms of transactions per second. A copy of the white paper and the Innovation Sandbox environment is now available for external developers to test. (https://github.com/nexledger/accelerator)

While this technical initiative is being rigorously validated from the open source Hyperledger community, Samsung SDS will prepare to become IBM’s key go-to-market reseller partner of IBM Blockchain Platform in Korea.

Ted Kim, Vice President, Blockchain Team from Samsung SDS America has been named to the IBM Blockchain Board of Advisors. Additionally, during the IBM Think Conference in San Francisco, Kiwoon Sung, Head of Blockchain Research Lab, Samsung SDS, will discuss the company’s blockchain innovation efforts at a session entitled, “New Blockchain Solutions emerging from the IBM Blockchain ecosystem.”

Hyperledger is an open source collaborative effort created to advance cross-industry blockchain technologies. It is a global collaboration including leaders in finance, banking, Internet of Things, supply chains, manufacturing and Technology. The Linux Foundation hosts Hyperledger under the foundation. To learn more, visit: https://www.hyperledger.org/.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that GLOBALFOUNDRIES (GF) has chosen Cadence as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects. The Avera Semi engineering team has come to rely on the features, capacity, speed and scalability of the Cadence® digital and signoff, system and verification, custom IC and PCB design and analysis tools and flows. Establishing Cadence as their primary vendor has enabled them to improve engineering productivity.

Avera Semi has successfully completed several large, complex 12nm and 14nm tapeouts and delivered production designs using Cadence flagship solutions such as the Innovus™ Implementation System, the Genus™Synthesis Solution, the Tempus™ Timing Signoff Solution and Xcelium™Parallel Logic Simulation as well as the Virtuoso® custom IC design platform, Spectre® circuit simulation platform and Allegro® and Sigrity™tools, which are part of following product categories:

  • Digital and Signoff: The parallelized, integrated Cadence digital and signoff solutions provided Avera Semi with a trusted design flow to achieve industry-leading power, performance and area (PPA) results with integrated signoff accuracy for designs with more than 500M instances, complex clocking requirements and chip sizes at the mask reticle limit.
  • System and Verification: The Cadence Verification Suite helped the Avera Semi verification team find bugs more efficiently, quickly implement and bring up complex testbenches for faster project completion and fuel testbench automation, analysis and reuse for increased productivity.
  • Custom IC/Analog Design: The comprehensive analog and mixed-signal simulation capabilities in the Cadence custom IC design platform enabled Avera Semi to consistently, accurately and quickly design and verify complex IP such as the Avera Semi 112G Serial Link. Additionally, the tight integration of Cadence physical verification and design-for-manufacturing (DFM) tools within the Cadence Virtuoso IC design platform accelerated design and implementation.
  • PCB Design and Analysis: Cadence’s PCB design and analysis tools helped Avera Semi achieve a smooth and efficient interface between the chip and packaging teams, helping to manage and track engineering change requests. The tools’ customizability enabled Avera Semi to automate the numerous properties associated with a package, reducing manual errors and design cycle time.

“Today’s announcement is another solid step in our collaborative journey to achieve a higher level of productivity through Cadence’s design flow,” said Kevin O’Buckley, GM at Avera Semi. “We have already deployed the Cadence flows to complete a number of successful production designs for our customers using the GF 12nm and 14nm FinFET process technologies and will extend our collaboration with Cadence on advanced nodes. Standardizing on Cadence’s custom, digital and IC package flows and verification solutions will help us master new challenges encountered at advanced nodes and expand our leadership in designs for data centers, wired communications, and machine learning and artificial intelligence applications.”

“Avera Semi uses Cadence as its primary supplier due to many years of successful collaborations on large, complex designs that met evolving market demands,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “We are always working to optimize design flow speed, throughput and provide differentiated tool features to deliver best-in-class PPA to customers. As we expand upon our longstanding relationship with Avera Semi, their customers can also benefit from our continued innovation and dedication to advancing ASIC design.”

The semiconductor industry showed impressive figures in 2017: +21.6% YoY growth to reach about US$ 412 billion. Without any doubt, the industry is entering a new age, where innovation and disruption are the key words. In addition to mobile, Yole Développement (Yole) analysts identified emerging mega-drivers that are step by step changing our world. Big data, AI, 5G, HPC, IoT, smart automotive, industry 4.0, datacenters and more, all mega-trends becoming part of our day to day life, with a direct impact on the semiconductor industry and its supply chain. In its latest report, Status of the Advanced Packaging Industry, Yole predicts an impressive US$39 billion advanced packaging market in 2023 with 7% CAGR.

“The advanced packaging is also driven by the wind of changes, due to the impressive impact of the megatrends,” explained Emilie Jolivet, Division Director, Semiconductor & Software at Yole. “Yole and NCAP China have decided to combine their expertise this year again to propose the Advanced Packaging & System Integration Technology Symposium in Shanghai, prior NEPCON China. This Shanghai edition will be the place to be to understand the industry evolution and measure the impact of the megatrends”.

NCAP CHINA and Yole build an innovative program fully dedicated to the advanced packaging industry: the Advanced Packaging & System Integration Technology Symposium takes place in Shanghai, China, from April 22 to 23, 2019, prior to NEPCON China 2019. During 2 days, all packaging aspects, including Panel Level, Fan-Out, SiP , Advanced Substrates and 3D Technology, will be discussed. A focus on key applications such as AI, HPC, memory, transportation (48V, EV/HEV , embedded die packaging platform, PCB , advanced substrates), 5G and consumer (WLP and Fan-Out platforms) will be at the heart of the conference.

Both partners invite you to meet the leading executives and gain an in-depth understanding of the market evolution! More info.

Mega-trends create huge business opportunities amongst various advanced packaging platforms. Therefore, advanced packaging technologies are just ideal for fulfilling numerous performance and complex heterogeneous integration needs.

“Two advanced packaging roadmaps are foreseen: scaling and functional,” asserts Santosh Kumar, Principal Analyst & Director Packaging, Assembly & Substrates, Yole Korea. “And the semiconductor industry is developing products for both of them. Advanced packaging is seen as a way to increase the value of a semiconductor product, adding functionality, maintaining/increasing performance while lowering cost…”

Both roadmaps developed by the Semiconductor & Software team at Yole, hold more multi-die heterogeneous integration, called SiP, and higher levels of package customization in the future. A variety of SiP solutions is developing in both high and low end, for consumer, performance and specialized applications. Heterogeneous integration has clearly created opportunities for both the substrate and WLP based SiP.

More than that. The advanced packaging supply chain is also involved in this fantastic story. Leading companies, startups, R&D institutes, the worldwide advanced packaging industry is playing the game. In order to expand the business, explore new areas and prepare for future uncertainty, advanced packaging players are moving to different business models:

• Some IDMs such as Intel are entering the foundry business to leverage their front-end technology expertise and create additional revenue stream by utilizing their excess capacity. Samsung, SK Hynix are also part of the playground…
• OEMs , software and service companies are designing their own chips and controlling the supply chain of equipment & materials related to it. Betting on mega-trends such as AI, some OSATs are expanding into the fablite business model.
• Pure play foundries including TSMC, XMC, UMC and SMIC are entering the high-end packaging business to provide turnkey solution to their customers.
• OSATs, such as Amkor Technology, JCET/STATS ChipPAC, ASE, SPIL, Powertech Technology…, are directing considerable efforts in developing advanced wafer level and 3D IC packaging capability to support requirements for scaling & density. OSATs are expanding their testing expertise & traditional pure test players are investing in assembly and packaging capability.
• Substrate manufacturers are penetrating the advanced packaging area with panel-level fan-out packaging and embedded die in organic laminate.

It is a fact. Advanced packaging is at the heart of innovation. Mega-trend applications are bringing new challenges, and leading advanced packaging companies from all over the world will come to exchange ideas on their vision and future perspectives at the Advanced Packaging & System Integration Technology Symposium.

Dr. Cao LiQiang, NCAP’s CEO asserts: “Under the background of China 13th Five-Year Plan and Made in China 2025, local organizations, including NCAP, focus on the core technology development for semiconductor industry and make big progresses. Promoting international communication as well as global cooperation on advanced packaging is the goal shared by Yole and NCAP, and the reason why we insist to organize the activity and make it an annual big event. With good reputations, hot topics and insightful presentations, we firmly believe that 2019 symposium will be a success. Don’t miss the opportunity to learn technology trend and expand your business at China.”

Yole and NCAP have created an unprecedented program to understand the status of the advanced packaging industry and help the companies to be part of the ‘tomorrow’ industry. The Advanced Packaging & System Integration Technology Symposium is unique.

Silicon Catalyst, the world’s only incubator focused exclusively on accelerating solutions in silicon, today announced Soitec (Euronext Paris), a designer and manufacturer of semiconductor materials, as its first European Strategic Partner. This agreement provides Soitec access to early-stage silicon technology innovation targeting consumer, IoT and automotive segments and applications.

Silicon Catalyst is a Silicon Valley-based incubator providing silicon-focused start-ups access to a world-class network of advisors, design tools, silicon devices, networking, access to funding and marketing acumen needed to successfully launch their businesses. Soitec will engage in this start-up ecosystem to gain insight into the newest technologies and applications across high-growth markets, and to guide nascent technologies to successful market penetration.

“As a Strategic Partner of Silicon Catalyst, Soitec has a unique opportunity to grow our visibility among early-stage semiconductor companies,” said Thomas Piliszczuk, Executive VP of Global Strategy for Soitec. “Engineered substrates give semiconductor related start-ups a competitive edge in developing new high-performance, energy-efficient solutions. We are looking forward to supporting emerging trends and technology advancements with Silicon Catalyst’s distinguished portfolio of semiconductor entrepreneurs.”

“We are pleased to welcome Soitec as our first European Strategic Partner. Soitec is creating technical advances that are enabling the next generation of products across many market segments. Their SOI technology is a key ingredient to meet the diverse challenges for breakthrough differentiated semiconductor products, combining ultra-low power with excellent analog / mixed-signal performance,” stated Pete Rodriguez, CEO of Silicon Catalyst. “Joining our other Strategic Partners, Texas Instruments and ON Semiconductor, Soitec will participate in the selection of applicants to our incubator and provide guidance for our Portfolio Companies, contributing to the growth of startups that are creating the next generations of semiconductor innovation.”

Soitec’s substrate solutions, most notably silicon-on-insulator (SOI), address the full range of applications for electronics. SOI substrates are designed to support ultra-low power signal processing, wireless connectivity, power, image sensors and silicon photonics applications. Radio-frequency silicon-on-insulator (RF-SOI) substrates are the foundation of the RF incumbent technology for RF Front-End modules used in all smart phones manufactured today. RF-SOI and fully depleted SOI (FD-SOI) material enable ultra-low power connectivity, mobility, distributed AI and edge computing. Adding our new compound and piezo-electric on insulator substrates, Soitec offers a wide range of engineered substrates addressing numerous and fast growing segments like automotive, AI-IoT (AIoT) and 5G.

Global electronics manufacturing pillars Smart manufacturing, IoT and workforce development will come into sharp focus at SEMICON Southeast Asia (SEA) 2019, scheduled May 7-9, at the Malaysia International Trade and Exhibition Centre (MITEC) in Kuala Lumpur. Industry experts from around the world will gather at the region’s premiere global electronics manufacturing supply chain for critical insights into the semiconductor ecosystem, new business opportunities and collaboration. SEMICON SEA 2019 registration is now open.

Themed “Think Smart, Make Smart,” SEMICON SEA will feature three themed pavilions, five global pavilions, insightful keynote presentations and a host of technology forums to address key issues in the electronics manufacturing supply chain.

The new Workforce Pavilion addresses the critical industry shortage of skilled workers by attracting the young talent critical to sustaining industry innovation and growth. College students will meet with industry experts to explore career paths in microelectronics as tutorials enhance university students’ understanding of semiconductor manufacturing and opportunities.

The World of IoT Pavilion showcases applications and technologies enabling the IoT revolution. Companies from across the region will demonstrate technologies that enable Smart lifestyles as start-ups showcase pioneering and disruptive products and applications powered by IoT.

At the Smart Manufacturing Pavilion, the Artificial Intelligence exhibition zone highlights critical capabilities including collaborative robots, automated guided vehicles, cybersecurity and manufacturing excellence systems. The Pavilion’s Supply Chain Management zone provides insights into key elements of manufacturing excellence such as automated material handling and automated storage and retrieval. The Pavilion also features an augmented reality (AR) interactive human-machine interface to give visitors an immersive experience in smarter manufacturing processes.

SEMICON SEA 2019 will also feature an exclusive Hosted Buyer Programme. Hosted by SEMI, the customised business matching platform connects buyers in the electronics manufacturing supply chain with international solution providers for collaboration and business opportunities.

SEMICON Southeast Asia 2019 sponsors include ADLINK, Applied Materials, Cimetrix®, Evatec, GLOBALFOUNDRIES, Kanken Techno Co Ltd, Kulicke & Soffa, First Derivatives, Lam Research, Tokyo Electron and UPS.

For more information about SEMICON SEA is available on the event website.