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A lithographic method for TSV alignment to embedded targets was evaluated using in-line stepper self metrology, with TIS correction.

BY WARREN W. FLACK, Veeco Instruments, Plainview, NY and JOHN SLABBEKOORN, imec, Leuven, Belgium

Demand for consumer product related devices including backside illuminated image sensors, interposers and 3D memory is driving advanced packaging using through silicon via (TSV) [1]. The various process flows for TSV processing (via first, via middle and via last) affect the relative levels of integration required at the foundry and OSAT manufacturing locations. Via last provides distinct advantages for process integration, including minimizing the impact on back end of line (BEOL) processing, and does not require a TSV reveal for the wafer thinning process. Scaling the diameter of the TSV significantly improves the system performance and cost. Current via last diameters are approximately 30μm with advanced TSV designs at 5 μm [2].

Lithography is one of the critical factors affecting overall device performance and yield for via last TSV fabrication [2]. One of the unique lithography requirements for via last patterning is the need for back-to-front side wafer alignment. With smaller TSV diameters, the back-to- front overlay becomes a critical parameter because via landing pads on the first level metal must be large enough to include both TSV critical dimension (CD) and overlay variations, as shown in FIGURE 1. Reducing the size of via landing pads provide significant advantages for device design and final chip size. This study evaluates 5μm TSVs with overlay performance of ≤ 750nm.

Alignment, illumination and metrology

Lithography was performed using an advanced packaging 1X stepper with a 0.16 numerical aperture (NA) Wynne Dyson lens. This stepper has a dual side alignment (DSA) system which uses infrared (IR) illumination to view metal targets through a thinned silicon wafer [3]. For the purposes of this study and its results, the wafer device side is referred to as the “front side” and the silicon side is referred to as the “back side.” The side facing up on the lithography tool is the back side of the TSV wafer, as shown in FIGURE 2.

The top IR illumination method for viewing embedded alignment targets, shown in Fig. 2, provides practical advantages for integration with stepper lithography. Since the illumination and imaging are directed from the top, this method does not interfere with the design of the wafer chuck, and does not constrain alignment target positioning on the wafer. The top IR alignment method illuminates the alignment target from the back side using an IR wavelength capable of transmitting through silicon (shown as light green in FIGURE 2) and the process films (shown in blue). In this configuration the target (shown in orange) needs to be made from an IR reflective material such as metal for optimal contrast. The alignment sequence requires that the wafer move in the Z axis in order to shift alignment focus from the wafer surface to the embedded target.

Back-to-front side registration was measured using a metrology package on the lithography tool which uses the DSA alignment system. This stepper self metrology package (DSA-SSM) includes routines to diagnose and compensate for measurement error from having features at different heights. For each measurement site the optical metrology system needs to move the focus in Z between the resist feature and the embedded feature. Therefore angular differences between the Z axis of motion, the optical axis of the alignment camera, and the wafer normal will contribute to measurement error for the tool [3]. The quality of the wafer stage motion is also very important because a significant pitch and roll signature would result in a location dependent error for embedded feature measurement, which would complicate the analysis.

If the measurement operation is repeatable and consistent across the wafer, then a constant error coming from the measurement tool, commonly referred to as tool induced shift (TIS), can be characterized using the method of TIS calibration, which incorporates measurements at 0 and 180 degree orientations. The TIS error—or calibration—is calculated by dividing the sum of offsets for the two orientations by two [4]. While the TIS calibration is effective for many types of measurements for planar metrology, for embedded feature metrology, the quality of measurement and calibration also depend on the quality and repeatability of wafer positioning, including tilt. In previous studies, the registration data obtained from the current method were self consistent and proved to be an effective inspection method [3, 5]. However given the dependencies affecting TIS calibration for embedded feature metrology, it is desirable to confirm the registration result using an alternate metrology method [5]. In order to independently verify the DSA-SSM, overlay data dedicated electrical structures were designed and placed on the test chip.

Electrical verification of TSV alignment is performed after complete processing of the test chip and relies on the landing position of a TSV on a fork-to-fork test structure in the embedded metal 1 (damascene metal). When the TSV processing is complete the copper filled TSV will make contact with metal 1. The TSV creates a short between the two sets of metal forks, allowing measurement of two resistance values which can be translated into edge measurements. For the case of ideal TSV alignment, the two resistances are equal. The measurement resolution of the electrical structure is limited by the pitch of the fork branches. In this study resolution is enhanced by creating structures with four different fork pitches. A similar fork-to-fork structure rotated 90 degrees is used for the Y alignment. Using this approach both overlay error and size of the TSV in both X and Y can be electrically determined [6].

Experimental methods

This study scrutinizes image placement performance by examining DSA optical metrology repeatability after TSV lithography, and then comparing this optical registration data with final electrical registration data.

The TSV-last process begins with a 300mm device wafer with metal 1, temporarily bonded to a carrier for mechanical support as shown in FIGURE 3. The back side of the silicon device wafer (light green) is thinned by grinding and then polished smooth by chemical mechanical planarization (CMP). The TSV is imaged in photoresist (red) and etched through the thinned silicon layer. FIGURE 3 depicts the complete process flow including the TSV, STI and PMD etch, TSV fill, redis- tribution layer (RDL) and de-bonding from carrier. The aligned TSV structure must land completely on the metal 1 pad (dark blue).

TSV lithography is done with a stepper equipped with DSA. The photoresist is a gh-line novolac based positive- tone material requiring 1250mJ/cm2 exposure dose with a thickness of 7.5μm [5]. The TSV diameter is 5μm, and the silicon thickness is 50μm. TSV etching of the silicon is performed by Bosch etching [7]. Tight control of lithography and TSV etching is required to insure that vias land completely on metal 1 pads, as shown in FIGURE 1.

Acceptable features for DSA-SSM metrology need to fit the via process requirements for integration. Since the TSV etch process is very sensitive to pattern size and density, the TSV layer is restricted to one size of via, and the DSA-SSM measurement structure is constructed using this shape. The design of the DSA-SSM measurement structure uses a cluster of 5μm vias with unique grouping and clocked rotation to avoid confusion with adjacent TSV device patterns during alignment.

FIGURE 4 shows two different focus offsets of DSA camera images of the overlay structure. For this structure, the reference metal 1 feature (outlined by the blue ring) and the resist pattern feature (outlined by the red ring) are not in the same focal plane. For a silicon thickness of 50μm, focusing on one feature will render the other feature out of focus, requiring each feature to have its own focus offset, which is specified in the metrology measurement recipe.

Optical registration process control

This study leveraged a sampling plan of 23 lithography fields with 5 measurements per field, resulting in a total of 115 measurements per wafer. Since the full wafer layout contains 262 fields, this sampling plan provides a good statistical sample for monitoring linear grid and intrafield parameters.

In the initial run, the overlay settings were optimized using the DSA-SSM metrology feedback and then the parameters were fixed to investigate overlay stability over a nine-week period. Trend charts for mean and 3σ for seven TSV lots are shown in FIGURE 5. Each measurement lot consists of 8 wafers, with 115 measure- ments per wafer, and all data is corrected for TIS on a per lot basis using measurements of a single wafer at 0 and 180 degree orientations [3]. The lot 3σ is consistently less than 600nm over the nine-week period. There appears to be a consistent small Y mean error (blue diamond) that could be adjusted to improve subsequent overlay results. With a Y mean correction applied, the registration data shows mean plus 3σ ≤ 600nm.

Validating TSV alignment and in-line optical metrology

Two TSV last test chip wafers were completely processed to the stage that they can be electrically measured. TABLE 1 shows the registration numbers confirming a good match between the two metrology methods. It is important to note that an extra translation step is performed between the optical and the electrical measurement: the TSV etch.

In this analysis the TSV etch is assumed to be perfectly vertical. From the data we can conclude that the TSV etch is indeed vertical enough not to interfere with the overlay data. Otherwise this would show as translation or scaling effects between the two metrology methods.

Conclusions

The lithographic method for TSV alignment to embedded targets was evaluated using in-line stepper self metrology, with TIS correction. Registration data was collected over a nine-week period to characterize the stability of TSV alignment. With corrections applied, the registration data demonstrates mean plus 3σ ≤ 600nm. The in-line optical registration data was then correlated to detailed electrical measurements performed on the same wafers at the end of the process to provide independent assessment of the accuracy of the optical data. Good correlation between optical and electrical data confirms the accuracy of the in-line optical metrology method, and also confirms that the TSV etch through 50μm thick silicon is vertical.

References

1. Vardaman, J. et. al., TechSearch International: Advanced Packaging Update, July 2016.
2. Van Huylenbroeck, S. et. al., “Small Pitch High Aspect Ratio Via Last TSV Module”, The 66th Electronic Components and Technology Conference, Los Vegas, NV, May 2016.
3. Flack, W. et. al., “Optimization of Through Si Via Last Lithography for 3D Packaging”, Twelfth International Wafer- Level Packaging Conference, San Jose, CA, October 2015.
4. Preil, M. et. al, “Improving the Accuracy of Overlay Measurements through Reduction of Tool and Wafer Induced Shifts”, Metrology, Inspection, and Process Control for Microlithography Proceedings, SPIE 3050, 1997.
5. Flack, W. et. al., “Verification of Back-to-Front Side Alignment for Advanced Packaging”, Ninth Interna- tional Wafer-Level Packaging Conference, Santa Clara, CA, November. 2012.
6. Flack, W. et.al., “Overlay Performance of Through Si Via Last Lithography for 3D Packaging”, 18th Electronics Packaging Technology Conference, Singapore, December 2016
7. Slabbekoorn, J. et. al, “Bosch Process Characterization For Donut TSV’s” Eleventh International Wafer-Level Packaging Conference, Santa Clara, CA, November 2014.

Materials that are hybrid constructions (combining organic and inorganic precursors) and quasi-two-dimensional (with malleable and highly compactable molecular structures) are on the rise in several technological applications, such as the fabrication of ever-smaller optoelectronic devices.

An article published in the journal Physical Review B describes a study in this field resulting from the doctoral research of Diana Meneses Gustin and Luís Cabral, both supervised by Victor Lopez Richard, a professor at the Federal University of São Carlos (UFSCar) in Brazil. Cabral was co-supervised by Juarez Lopes Ferreira da Silva, a professor at the University of São Paulo’s São Carlos Chemistry Institute (IQSC-USP). Gustin was supported by São Paulo Research Foundation – FAPESP via a doctoral scholarship and a scholarship for a research internship abroad.

“Gustin and Cabral explain theoretically the unique optical and transport properties resulting from interaction between a molybdenum disulfide monolayer [inorganic substance MoS2] and a substrate of azobenzene [organic substance C12H10N2],” Lopez Richard told.

Illumination makes the azobenzene molecule switch isomerization and transition from a stable trans spatial configuration to a metastable cis form, producing effects on the electron cloud in the molybdenum disulfide monolayer. These effects, which are reversible, had previously been investigated experimentally by Emanuela Margapoti in postdoctoral research conducted at UFSCar and supported by FAPESP.

Gustin and Cabral developed a model to emulate the process theoretically. “They performed ab initio simulations [computational simulations using only established science] and calculations based on density functional theory [a quantum mechanical method used to investigate the dynamics of many-body systems]. They also modeled the transport properties of the molybdenum disulfide monolayer when disturbed by variations in the azobenzene substrate,” Richard explained.

While the published paper does not address technological applications, the deployment of the effect to build a light-activated two-dimensional transistor is on the researchers’ horizon.

“The quasi two-dimensional structure makes molybdenum disulfide as attractive as graphene in terms of space reduction and malleability, but it has virtues that potentially make it even better. It’s a semiconductor with similar electrical conductivity properties to graphene’s and it’s more versatile optically because it emits light in the wavelength range from infrared to the visible region,” Richard said.

The hybrid molybdenum-disulfide-azobenzene structure is considered a highly promising material, but a great deal of research and development will be required if it is to be effectively deployed in useful devices.

Researchers at Tokyo Institute of Technology (Tokyo Tech) report a unipolar n-type transistor with a world-leading electron mobility performance of up to 7.16 cm2 V-1 s-1. This achievement heralds an exciting future for organic electronics, including the development of innovative flexible displays and wearable technologies.

Researchers worldwide are on the hunt for novel materials that can improve the performance of basic components required to develop organic electronics.

Now, a research team at Tokyo Tech’s Department of Materials Science and Engineering including Tsuyoshi Michinobu and Yang Wang report a way of increasing the electron mobility of semiconducting polymers, which have previously proven difficult to optimize. Their high-performance material achieves an electron mobility of 7.16 cm2 V-1 s-1, representing more than a 40 percent increase over previous comparable results.

In their study published in the Journal of the American Chemical Society, they focused on enhancing the performance of materials known as n-type semiconducting polymers. These n-type (negative) materials are electron dominant, in contrast to p-type (positive) materials that are hole dominant. “As negatively-charged radicals are intrinsically unstable compared to those that are positively charged, producing stable n-type semiconducting polymers has been a major challenge in organic electronics,” Michinobu explains.

The research therefore addresses both a fundamental challenge and a practical need. Wang notes that many organic solar cells, for example, are made from p-type semiconducting polymers and n-type fullerene derivatives. The drawback is that the latter are costly, difficult to synthesize and incompatible with flexible devices. “To overcome these disadvantages,” he says, “high-performance n-type semiconducting polymers are highly desired to advance research on all-polymer solar cells.”

The team’s method involved using a series of new poly(benzothiadiazole-naphthalenediimide) derivatives and fine-tuning the material’s backbone conformation. This was made possible by the introduction of vinylene bridges[1] capable of forming hydrogen bonds with neighboring fluorine and oxygen atoms. Introducing these vinylene bridges required a technical feat so as to optimize the reaction conditions.

Overall, the resultant material had an improved molecular packaging order and greater strength, which contributed to the increased electron mobility.

Using techniques such as grazing-incidence wide-angle X-ray scattering (GIWAXS), the researchers confirmed that they achieved an extremely short π-π stacking distance[2] of only 3.40 angstrom. “This value is among the shortest for high mobility organic semiconducting polymers,” says Michinobu.

There are several remaining challenges. “We need to further optimize the backbone structure,” he continues. “At the same time, side chain groups also play a significant role in determining the crystallinity and packing orientation of semiconducting polymers. We still have room for improvement.”

Wang points out that the lowest unoccupied molecular orbital (LUMO) levels were located at -3.8 to -3.9 eV for the reported polymers. “As deeper LUMO levels lead to faster and more stable electron transport, further designs that introduce sp2-N, fluorine and chlorine atoms, for example, could help achieve even deeper LUMO levels,” he says.

In future, the researchers will also aim to improve the air stability of n-channel transistors — a crucial issue for realizing practical applications that would include complementary metal-oxide-semiconductor (CMOS)-like logic circuits, all-polymer solar cells, organic photodetectors and organic thermoelectrics.

Zips on the nanoscale


February 28, 2019

Nanostructures based on carbon are promising materials for nanoelectronics. However, to be suitable, they would often need to be formed on non-metallic surfaces, which has been a challenge – up to now. Researchers at Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) have found a method of forming nanographenes on metal oxide surfaces. Their research, conducted within the framework of collaborative research centre 953 – Synthetic Carbon Allotropes funded by the German Research Foundation (DFG), has now been published in the journal Science.

Two-dimensional, flexible, tear-resistant, lightweight, and versatile are all properties that apply to graphene, which is often described as a miracle material. In addition, this carbon-based nanostructure has unique electrical properties that make it attractive for nanoelectronic applications. Depending on its size and shape, nanographene can be conductive or semi-conductive – properties that are essential for use in nanotransistors. Thanks to its good electrical and thermal conductivity, it could also replace copper (which is conductive) and silicon (which is semi-conductive) in future nanoprocessors.

New: Nanographene on metal oxides

The problem: In order to create an electronic circuit, the molecules of nanographene must be synthesised and assembled directly on an insulating or semi-conductive surface. Although metal oxides are the best materials for this purpose, in contrast to metal surfaces, direct synthesis of nanographenes on metal oxide surfaces is not possible as they are considerably less chemically reactive. The researchers would have to carry out the process at high temperatures, which would lead to several uncontrollable secondary reactions. A team of scientists led by Dr. Konstantin Amsharov from the Chair of Organic Chemistry II have now developed a method of synthesising nanographenes on non-metallic surfaces, that is insulating surfaces or semi-conductors.

It’s all about the bond

The researchers’ method involves using a carbon fluorine bond, which is the strongest carbon bond. It is used to trigger a multilevel process. The desired nanographenes form like dominoes via cyclodehydrofluorination on the titanium oxide surface. All ‘missing’ carbon-carbon bonds are thus formed after each other in a formation that resembles a zip being closed. This enables the researchers to create nanographenes on titanium oxide, a semi-conductor. This method also allows them to define the shape of the nanographene by modifying the arrangement of the preliminary molecules. New carbon-carbon bonds and, ultimately, nanographenes form where the researchers place the fluourine atoms. For the first time, these research results demonstrate how carbon-based nanostructures can be manufactured by direct synthesis on the surfaces of technically-relevant semi-conducting or insulating surfaces. ‘This groundbreaking innovation offers effective and simple access to electronic nanocircuits that really work, which could scale down existing microelectronics to the nanometre scale,’ explains Dr. Amsharov.

Materials that are hybrid constructions (combining organic and inorganic precursors) and quasi-two-dimensional (with malleable and highly compactable molecular structures) are on the rise in several technological applications, such as the fabrication of ever-smaller optoelectronic devices.

An article published in the journal Physical Review B describes a study in this field resulting from the doctoral research of Diana Meneses Gustin and Luís Cabral, both supervised by Victor Lopez Richard, a professor at the Federal University of São Carlos (UFSCar) in Brazil. Cabral was co-supervised by Juarez Lopes Ferreira da Silva, a professor at the University of São Paulo’s São Carlos Chemistry Institute (IQSC-USP). Gustin was supported by São Paulo Research Foundation – FAPESP via a doctoral scholarship and a scholarship for a research internship abroad.

“Gustin and Cabral explain theoretically the unique optical and transport properties resulting from interaction between a molybdenum disulfide monolayer [inorganic substance MoS2] and a substrate of azobenzene [organic substance C12H10N2],” Lopez Richard told.

Illumination makes the azobenzene molecule switch isomerization and transition from a stable trans spatial configuration to a metastable cis form, producing effects on the electron cloud in the molybdenum disulfide monolayer. These effects, which are reversible, had previously been investigated experimentally by Emanuela Margapoti in postdoctoral research conducted at UFSCar and supported by FAPESP.

Gustin and Cabral developed a model to emulate the process theoretically. “They performed ab initio simulations [computational simulations using only established science] and calculations based on density functional theory [a quantum mechanical method used to investigate the dynamics of many-body systems]. They also modeled the transport properties of the molybdenum disulfide monolayer when disturbed by variations in the azobenzene substrate,” Richard explained.

While the published paper does not address technological applications, the deployment of the effect to build a light-activated two-dimensional transistor is on the researchers’ horizon.

“The quasi two-dimensional structure makes molybdenum disulfide as attractive as graphene in terms of space reduction and malleability, but it has virtues that potentially make it even better. It’s a semiconductor with similar electrical conductivity properties to graphene’s and it’s more versatile optically because it emits light in the wavelength range from infrared to the visible region,” Richard said.

The hybrid molybdenum-disulfide-azobenzene structure is considered a highly promising material, but a great deal of research and development will be required if it is to be effectively deployed in useful devices.

Nova (NASDAQ: NVMI) today announced that its co-authored paper with GLOBALFOUNDRIES on ‘Implementation of machine learning for high volume manufacturing metrology challenges’ has been selected as the winner of the Diana Nyyssonen award for ‘best paper at SPIE‘s 2018 Advanced Lithography Symposia.’ The award was granted to Nova and GF on the opening day of the 2019 Conference. The paper is a result of the continuous partnership between the companies and demonstrates the innovation Nova promotes in advanced process control utilizing its unique and differentiated software solutions. The methodology described in the paper was already installed and is utilized by GF in high volume manufacturing.

The joint effort demonstrates that predictive metrology based on machine learning is an advantageous and complementary technique for high volume semiconductor manufacturing. The collaborative work of Nova and GF examined the suitability of machine learning to address high volume manufacturing metrology requirements for applications in both front end of line (FEOL) and back end of line (BEOL) in advanced technology nodes. Feasibility to predict CD values from an inline measurement using machine learning engines was demonstrated, as well as the usage of machine learning data to directly predict electrical parameters.

“We are honored to be selected for this prestigious award in collaboration with our partners at GF,” said Dr. Shay Wolfling, Chief Technology Officer of Nova. “This innovative metrology solution is enabled by our NOVAFitTM technology that enhances traditional modeling capabilities with advanced machine learning algorithms. The joint work with GF has demonstrated once more that through collaboration with our customers our most advanced machine-learning solutions can quickly proliferate and be validated in high volume production in advanced technology nodes.”

Micron Technology, Inc. (Nasdaq: MU) today added a new cost-efficient solid-state drive (SSD) to its client computing portfolio. The Micron 1300 SSD makes flash storage accessible to more users, enabling its adoption in a broader set of personal computing devices for a better mobile computing experience. Consumers who are eager to move from rotating media to solid state drives value fast performance, quick startup, and reliability — whether for desktop, mobile or workstation PCs. SSDs address these needs better than power-hungry hard disk drives (HDDs), yet their higher prices have kept users from shifting to SSDs. Micron redesigned the 1300 SSD series to close the price gap.

“The deployment of advanced 3D NAND technologies has led the client SSD market to branch into value and higher-performance storage segments,” said Gregory Wong, president of Forward Insights. “Micron’s latest client SSD solutions provide a coherent migration path from HDD to value-oriented SSDs.”

The new Micron 1300 SATA SSD is one of the industry’s first 96-layer triple-level cell (TLC) 3D NAND-based SSDs, available in capacities up to 1TB (in M.2) and 2TB (in 2.5-inch). This product introduction extends Micron’s leadership in high-density SSD design and high-volume manufacturing of performance 3D NAND-based flash drives. The ability to build drives with very small footprints like the M.2 SSD form factor, which is as small as a stick of gum, also hinges on Micron’s leadership in 3D NAND technology.

“We are driving innovation to deliver on the personal computing needs of users who want thinner, lighter and less power-hungry devices,” said Roger Peene, vice president of product planning and strategy for Micron’s Storage Business Unit. “Expanding our broad SSD portfolio with high-density 96-layer NAND storage delivers greater performance, form factors and efficiency at lower cost to meet the demanding needs of today’s mobile workers.”

The Micron 1300 SSD enhances storage performance for mobile, desktop and workstation PCs with 2.7x higher read throughput over HDDs.* It delivers sequential reads/writes up to 530MB/520MB per second and random reads/writes up to 90,000/87,000 input/output operations per second (IOPS).

In addition, the Micron 1300 SSD, designed to be power efficient, extends battery life between charges for the mobile worker. It uses 75 milliwatts (mW) of power, which is only 45 percent of the active (read/write) power of an average HDD.** The Micron 1300 SSD also supports Microsoft® Windows® 10 Modern Standby requirements including adaptive thermal management and near-instant transmission to low-power mode for increased productivity. The SSD also offers important features to protect valuable data such as asynchronous power-loss protection for data at rest and optional Opal 2.0 self-encryption.

The Micron 1300 SSD is an extension of the popular Micron 1100 SATA client SSD. Continuing the widely adopted SATA connectivity, Micron’s 1300 SSD series offers compelling price-to-value ratios at a range of capacities.

Future technologies based on the principles of quantum mechanics could revolutionize information technology. But to realize the devices of tomorrow, today’s physicists must develop precise and reliable platforms to trap and manipulate quantum-mechanical particles.

In a paper published Feb. 25 in the journal Nature, a team of physicists from the University of Washington, the University of Hong Kong, the Oak Ridge National Laboratory and the University of Tennessee, report that they have developed a new system to trap individual excitons. These are bound pairs of electrons and their associated positive charges, known as holes, which can be produced when semiconductors absorb light. Excitons are promising candidates for developing new quantum technologies that could revolutionize the computation and communications fields.

The team, led by Xiaodong Xu, the UW’s Boeing Distinguished Professor of both physics and materials science and engineering, worked with two single-layered 2D semiconductors, molybdenum diselenide and tungsten diselenide, which have similar honeycomb-like arrangements of atoms in a single plane. When the researchers placed these 2D materials together, a small twist between the two layers created a “superlattice” structure known as a moiré pattern — a periodic geometric pattern when viewed from above. The researchers found that, at temperatures just a few degrees above absolute zero, this moiré pattern created a nanoscale-level textured landscape, similar to the dimples on the surface of a golf ball, which can trap excitons in place like eggs in an egg carton. Their system could form the basis of a novel experimental platform for monitoring excitons with precision and potentially developing new quantum technologies, said Xu, who is also a faculty researcher with the UW’s Clean Energy Institute.

Excitons are exciting candidates for communication and computer technologies because they interact with photons — single packets, or quanta, of light — in ways that change both exciton and photon properties. An exciton can be produced when a semiconductor absorbs a photon. The exciton also can later transform back into a photon. But when an exciton is first produced, it can inherit some specific properties from the individual photon, such as spin. These properties can then be manipulated by researchers, such as changing the spin direction with a magnetic field. When the exciton again becomes a photon, the photon retains information about how the exciton properties changed over its short life — typically, about a hundred nanoseconds for these excitons — in the semiconductor.

In order to utilize individual excitons’ “information-recording” properties in any technological application, researchers need a system to trap single excitons. The moiré pattern achieves this requirement. Without it, the tiny excitons, which are thought to be less than 2 nanometers in diameter, could diffuse anywhere in the sample — making it impossible to track individual excitons and the information they possess. While scientists had previously developed complex and sensitive approaches to trap several excitons close to one another, the moiré pattern developed by the UW-led team is essentially a naturally formed 2D array that can trap hundreds of excitons, if not more, with each acting as a quantum dot, a first in quantum physics.

A unique and groundbreaking feature of this system is that the properties of these traps, and thus the excitons, can be controlled by a twist. When the researchers changed the rotation angle between the two different 2D semiconductors, they observed different optical properties in excitons. For example, excitons in samples with twist angles of zero and 60 degrees displayed strikingly different magnetic moments, as well as different helicities of polarized light emission. After examining multiple samples, the researchers were able to identify these twist angle variations as “fingerprints” of excitons trapped in a moiré pattern.

In the future, the researchers hope to systematically study the effects of small twist angle variations, which can finely tune the spacing between the exciton traps — the egg carton dimples. Scientists could set the moiré pattern wavelength large enough to probe excitons in isolation or small enough that excitons are placed closely together and could “talk” to one another. This first-of-its-kind level of precision may let scientists probe the quantum-mechanical properties of excitons as they interact, which could foster the development of groundbreaking technologies, said Xu.

“In principle, these moiré potentials could function as arrays of homogenous quantum dots,” said Xu. “This artificial quantum platform is a very exciting system for exerting precision control over excitons — with engineered interaction effects and possible topological properties, which could lead to new types of devices based on the new physics.”

“The future is very rosy,” Xu added.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Toshiba Memory Corporation has successfully used the Cadence® CMP Process Optimizer, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices. With the Cadence solution in place, Toshiba Memory Corporation achieved 95.7 percent accuracy to silicon.

After conducting a thorough competitive evaluation, Toshiba Memory Corporation adopted the Cadence CMP Process Optimizer for its unparalleled feature set that addresses diverse layout topologies of array-based memory designs. The Cadence CMP Process Optimizer is based on a model-based approach versus a traditional, rules-based approach, which enabled Toshiba Memory Corporation to better predict complex, cumulative and long-range effects of chemical mechanical polishing (CMP) effects and CMP yield-limiting hotspots. Also, the Cadence CMP Process Optimizer allowed Toshiba Memory Corporation to perform simulations for the entire design stacks—both the transistor and routing layers—leading to improved accuracy. Toshiba Memory Corporation generated high-precision CMP models with the Cadence CMP Process Optimizer’s innovative capabilities. For more information on the Cadence CMP Process Optimizer, please visit www.cadence.com/go/ccpo.

“Advanced process technologies bring added complexities to the design process, and as a result, CMP effects have become more and more critical for us, particularly for our leading 3D flash memory solutions,” said Susumu Yoshikawa, technology executive, Memory Technology at Toshiba Memory Corporation. “We’ve been particularly impressed by the Cadence CMP Process Optimizer’s unparalleled capabilities, which enabled highly accurate modeling and analysis that we expect to improve product yield and accelerate the delivery of our flash devices.”

The Cadence CMP Process Optimizer offers feature-scale topography prediction and advanced reverse etch-back for accurate modeling and is part of the broader Cadence digital and signoff portfolio. From synthesis through implementation and signoff, the Cadence integrated full-flow digital and signoff tools provide a fast path to design closure and better predictability. The digital and signoff full-flow supports the company’s overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

Researchers at The University of Manchester in the UK, led by Dr Artem Mishchenko, Prof Volodya Fal’ko and Prof Andre Geim, have discovered the quantum Hall effect in bulk graphite – a layered crystal consisting of stacked graphene layers. This is an unexpected result because the quantum Hall effect is possible only in so-called two-dimensional (2D) systems where electrons’ motion is restricted to a plane and must be disallowed in the perpendicular direction. They have also found that the material behaves differently depending on whether it contains odd or even number of graphene layers – even when the number of layers in the crystal exceeds hundreds. The work is an important step to the understanding of the fundamental properties of graphite, which have often been misunderstood, esepcially in recent years.

In their work, published in Nature Physics, Mishchenko and colleagues studied devices made from cleaved graphite crystals, which essentially contain no defects. The researchers preserved the high quality of the material also by encapsulating it in another high-quality layered material – hexagonal boron nitride. They shaped their devices in a Hall bar geometry, which allowed them to measure electron transport in the thin graphite.

“The measurements were quite simple.” explains Dr Jun Yin, the first author of the paper. “We passed a small current along the Hall bar, applied strong magnetic field perpendicular to the Hall bar plane and then measured voltages generated along and across the device to extract longitudinal resistivity and Hall resistance.

Dimensional reduction

Fal’ko who led the theory part said: “We were quite surprised when we saw the quantum Hall effect (QHE) – a sequence of quantized plateaux in the Hall resistance – accompanied by zero longitudinal resistivity in our samples. These are thick enough to behave just as a normal bulk semimetal in which QHE should be forbidden.”

The researchers say that the QHE comes from the fact that the applied magnetic field forces the electrons in graphite to move in a reduced dimension, with conductivity only allowed in the direction parallel to the field. In thin enough samples, however, this one-dimensional motion can become quantized thanks to the formation of standing electron waves. The material thus goes from being a 3D electron system to a 2D one with discrete energy levels.

Even/odd number of graphene layers is important

Another big surprise is that this QHE is very sensitive to even/odd number of graphene layers. The electrons in graphite are similar to those in graphene and come in two “flavours” (called valleys). The standing waves formed from electrons of two different flavours sit on either even – or odd – numbered layers in graphite. In films with even number of layers, the number of even and odd layers is the same, so the energies of the standing waves of different flavours coincide.

The situation is different in films with odd numbers of layers, however, because the number of even and odd layers is different, that is, there is always an extra odd layer. This results in the energy levels of the standing waves of different flavours shifting with respect to each other and means that these samples have reduced QHE energy gaps. The phenomenon even persists for graphite hundreds of layers thick.

Observations of the fractional QHE

The unexpected discoveries did not end there: the researchers say they also observed the fractional QHE in thin graphite below 0.5 K. The FQHE is different from normal QHE and is a result of strong interactions between electrons. These interactions, which can often lead to important collective phenomena such as superconductivity, magnetism and superfluidity, make the charge carriers in a FQHE material behave as quasiparticles with charge that is a fraction of that of an electron.

“Most of the results we have observed can be explained using a simple single-electron model but seeing the FQHE tells us that the picture is not so simple,” says Mishchenko. “There are plenty of electron-electron interactions in our graphite samples at high magnetic fields and low temperatures, which shows that many-body physics is important in this material.”

Coming back to graphite

Graphene has been in the limelight these last 15 years, and with reason, and graphite was pushed back a little by its one-layer-thick offspring, Mishchenko adds. “We have now come back to this old material. Knowledge gained from graphene research, improved experimental techniques (such as van der Waals assembly technology) and a better theoretical understanding (again from graphene physics), has already allowed us to discover this novel type of the QHE in graphite devices we made.

“Our work is a new stepping stone to further studies on this material, including many-body physics, like density waves, excitonic condensation or Wigner crystallization.”

The graphite studied here has natural (Bernal) stacking, but there is another stable allotrope of graphite – rhombohedral. There are no reported transport measurements on this material so far, only lots of theoretical predictions, including high-temperature superconductivity and ferromagnetism. The Manchester researchers say they thus now plan to explore this allotrope too.

“For decades graphite was used by researchers as a kind of ‘philosopher’s stone’ that can deliver all probable and improbable phenomena including room-temperature superconductivity,” Geim adds with a smile. “Our work shows what is, in principle, possible in this material, at least when it is in its purest form.”