Tag Archives: letter-pulse-tech

The connection from fridge magnets to cutting edge materials science is shorter than what one might expect. The reason why a magnet sticks to your fridge is that electronic spins or magnetic moments in the magnetic material spontaneously align or order in one direction, which enables it to exert an attractive force to the steel door of your fridge and reminds you to buy milk.

Magnets are one type of materials with such built-in order. A ‘topological defect’ in such a material occurs as a discontinuity in this order, i.e. a boundary region where the order does not seamlessly transition from one area to another. These topological structures form naturally or can be highly engineered in advanced functional materials.

An article published this week in the leading journal Nature Materials by FLEET CI Prof Jan Seidel outlines emerging research into different types of ‘defective’ order, i.e. topological structures in materials, and their potential highly interesting applications in nanotechnology and nanoelectronics.

Seidel was invited by the journal editor to review current and discuss future research on domain walls and related topological structures.

Although known for a long time, domain walls as one type of topological structure have only been intensively studied in detail over recent years. It is only with recent developments in high-resolution electron microscopy (HREM) and scanning probe microscopy (SPM) that it has been shown that they can significantly affect macroscopic materials properties, and even more interestingly, that they can exhibit intrinsic properties of their own. Research in this field pioneered in part by Prof Seidel has grown extensively in the last few years and now has entire conferences dedicated to it, such as the annual International Workshop on Topological Structures in Ferroic Materials (TOPO), for which the first meeting was held in 2015 in Sydney.

Nanoelectronics based on topological structures was published in Nature Materials on 20 February 2019. Prof Seidel acknowledges funding support by the Australian Research Council (ARC) through Discovery Grants and the ARC Centre of Excellence in Future Low Energy Electronics Technologies (FLEET).

Prof Jan Seidel is a Professor at the School of Materials Science and Engineering at UNSW Sydney. Contact [email protected]

FLEET is an ARC-funded research centre bringing together over a hundred Australian and international experts to develop a new generation of ultra-low energy electronics, motivated by the need to reduce the energy consumed by computing.

GOWIN Semiconductor Corp., an innovator of programmable logic devices, announces the release of GOWIN’s new EDA tool, YunYuan 1.9. With the release of this new toolchain, GOWIN will enable enhanced features and performance capabilities on their current and future FPGA product families.

EDA toolchains are becoming increasingly complex as FPGA applications are integrating more functions for the cloud and endpoint markets. To enable this complexity change, the new toolchain will include Gowin Synthesis, an enhanced front end logic synthesis tool designed and developed by the GOWIN EDA software team. It’s a significant milestone for GOWIN as the total toolchain is now completely designed in-house, allowing for quick quality improvements as well as product updates for customers time to market requirements. While GOWIN’s FPGA’s will be more optimized for IP, performance, and utilization using the new Yun Yuan 1.9 toolchain, the toolchain will additionally support the current Synopsys Synplify Pro synthesis tool already integrated.

“The development of the new synthesis tool is a major step for GOWIN,” said Alan Liu, Director of Software Development, GOWIN Semiconductor. “We can now make tool adjustments in real-time, enhancing the user experience.”

GOWIN EDA (YunYuan®) is an easy-to-use integrated design environment, providing design engineers with a one-stop solution. The complete GUI based environment covers FPGA design entry, code synthesis, place & route, bitstream generation, download, and online debugging of GOWIN FPGA’s on customer’s boards. The new toolchain also incorporates the following updated IP blocks:

Communication:

  • CAN2.0 & CAN-FD IP
  • High-Speed MIPI Interface (1:8 & 1:16 Gear Box)
  • Ethernet 10/100/1000Mhz MAC Controller & Interface to MII/RMII/GMII

Memory Controller:

  • pSRAM Controller IP

Microprocessor:

  • Configurable RISC-V (5-Stage-Pipeline) CPU & System IP

DSP:

  • FIR
  • NLMS Filter
  • FDAF – Frequency Domain Adaptive Filter
  • Cross-Correlation

Nanowires have the potential to revolutionize the technology around us. Measuring just 5-100 nanometers in diameter (a nanometer is a millionth of a millimeter), these tiny, needle-shaped crystalline structures can alter how electricity or light passes through them.

EPFL researchers have found a way to control and standardize the production of nanowires on silicon surfaces. This discovery could make it possible to grow nanowires on electronic platforms, with potential applications including the integration of nanolasers into electronic chips and improved energy conversion in solar panels. Credit: Jamani Caillet / EPFL

They can emit, concentrate and absorb light and could therefore be used to add optical functionalities to electronic chips. They could, for example, make it possible to generate lasers directly on silicon chips and to integrate single-photon emitters for coding purposes. They could even be applied in solar panels to improve how sunlight is converted into electrical energy.

Up until now, it was impossible to reproduce the process of growing nanowires on silicon semiconductors – there was no way to repeatedly produce homogeneous nanowires in specific positions. But researchers from EPFL’s Laboratory of Semiconductor Materials, run by Anna Fontcuberta i Morral, together with colleagues from MIT and the IOFFE Institute, have come up with a way of growing nanowire networks in a highly controlled and fully reproducible manner. The key was to understand what happens at the onset of nanowire growth, which goes against currently accepted theories. Their work has been published in Nature Communications.

“We think that this discovery will make it possible to realistically integrate a series of nanowires on silicon substrates,” says Fontcuberta i Morral. “Up to now, these nanowires had to be grown individually, and the process couldn’t be reproduced.”

Getting the right ratio

The standard process for producing nanowires is to make tiny holes in silicon monoxide and fill them with a nanodrop of liquid gallium. This substance then solidifies when it comes into contact with arsenic. But with this process, the substance tends to harden at the corners of the nanoholes, which means that the angle at which the nanowires will grow can’t be predicted. The search was on for a way to produce homogeneous nanowires and control their position.

Research aimed at controlling the production process has tended to focus on the diameter of the hole, but this approach has not paid off. Now EPFL researchers have shown that by altering the diameter-to-height ratio of the hole, they can perfectly control how the nanowires grow. At the right ratio, the substance will solidify in a ring around the edge of the hole, which prevents the nanowires from growing at a non-perpendicular angle. And the researchers’ process should work for all types of nanowires.

“It’s kind of like growing a plant. They need water and sunlight, but you have to get the quantities right,” says Fontcuberta i Morral.

This new production technique will be a boon for nanowire research, and further samples should soon be developed.

A team of Cambridge researchers have found a way to control the sea of nuclei in semiconductor quantum dots so they can operate as a quantum memory device.

Quantum dots are crystals made up of thousands of atoms, and each of these atoms interacts magnetically with the trapped electron. If left alone to its own devices, this interaction of the electron with the nuclear spins, limits the usefulness of the electron as a quantum bit – a qubit.

Led by Professor Mete Atatüre, a Fellow at St John’s College, University of Cambridge, the research group, located at the Cavendish Laboratory, exploit the laws of quantum physics and optics to investigate computing, sensing or communication applications.

Atatüre said: “Quantum dots offer an ideal interface, as mediated by light, to a system where the dynamics of individual interacting spins could be controlled and exploited. Because the nuclei randomly ‘steal’ information from the electron they have traditionally been an annoyance, but we have shown we can harness them as a resource.”

The Cambridge team found a way to exploit the interaction between the electron and the thousands of nuclei using lasers to ‘cool’ the nuclei to less than 1 milliKelvin, or a thousandth of a degree above the absolute zero temperature. They then showed they can control and manipulate the thousands of nuclei as if they form a single body in unison, like a second qubit. This proves the nuclei in the quantum dot can exchange information with the electron qubit and can be used to store quantum information as a memory device. The findings have been published in Science today.

Quantum computing aims to harness fundamental concepts of quantum physics, such as entanglement and superposition principle, to outperform current approaches to computing and could revolutionise technology, business and research. Just like classical computers, quantum computers need a processor, memory, and a bus to transport the information backwards and forwards. The processor is a qubit which can be an electron trapped in a quantum dot, the bus is a single photon that these quantum dots generate and are ideal for exchanging information. But the missing link for quantum dots is quantum memory.

Atatüre said: “Instead of talking to individual nuclear spins, we worked on accessing collective spin waves by lasers. This is like a stadium where you don’t need to worry about who raises their hands in the Mexican wave going round, as long as there is one collective wave because they all dance in unison.

“We then went on to show that these spin waves have quantum coherence. This was the missing piece of the jigsaw and we now have everything needed to build a dedicated quantum memory for every qubit.”

In quantum technologies, the photon, the qubit and the memory need to interact with each other in a controlled way. This is mostly realised by interfacing different physical systems to form a single hybrid unit which can be inefficient. The researchers have been able to show that in quantum dots, the memory element is automatically there with every single qubit.

Dr Dorian Gangloff, one of the first authors of the paper and a Fellow at St John’s, said the discovery will renew interest in these types of semiconductor quantum dots. Dr Gangloff explained: “This is a Holy Grail breakthrough for quantum dot research – both for quantum memory and fundamental research; we now have the tools to study dynamics of complex systems in the spirit of quantum simulation.”

The long term opportunities of this work could be seen in the field of quantum computing. Last month, IBM launched the world’s first commercial quantum computer, and the Chief Executive of Microsoft has said quantum computing has the potential to ‘radically reshape the world’.

Gangloff said: “The impact of the qubit could be half a century away but the power of disruptive technology is that it is hard to conceive of the problems we might open up – you can try to think of it as known unknowns but at some point you get into new territory. We don’t yet know the kind of problems it will help to solve which is very exciting.”

UltraSoC, the provider of embedded analytics for the RISC-V ecosystem, today announced full support within its embedded analytics architecture for Western Digital’s RISC-V SweRV Core™ and associated OmniXtend™ cache-coherent interconnect. The two companies have worked together to create a debug and on-chip analytics ecosystem that will support the requirements of both Western Digital’s internal development teams, and third parties choosing to adopt the SweRV Core for their own applications.

“Western Digital has proven to be a powerful driving force within the RISC-V ecosystem, with a visionary approach encompassing processors that are closely tailored to their target applications,” said Rupert Baines, UltraSoC CEO. “The SweRV concept is a compelling one, and we’re extremely proud to have been selected to support it at an early stage of its evolution.”

SweRV is an open source RISC-V core intended to accelerate development of open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem, allowing it to create processors that are purpose-built for data-centric applications. Every storage product the company ships contains some kind of processor, and the company has committed to transitioning one billion of these cores to the RISC-V architecture.

UltraSoC launched the industry’s first – and still only – commercial RISC-V processor trace solution in June 2017, and is committed to supporting both standards-based and proprietary debug and analytics approaches. Trace functionality is a key tool for system developers, allowing the behavior of a program to be viewed in detail. UltraSoC’s embedded analytics technology is uniquely capable of supporting very powerful multicore system-on-chip (SoC) implementations, and enables seamless development and debug of systems containing multiple different types of processor: known as heterogeneous systems.

Western Digital’s RISC-V SweRV Core is based on a two-way superscalar design, with a 32-bit, nine-stage pipeline core that allows several instructions to be loaded at once and execute simultaneously. It is a compact, in-order core and is expected to run at around 5 CoreMarks/Mhz. Its power-efficient design offers clock speeds of up to 1.8Ghz on a 28nm CMOS process technology. Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.

Synopsys, Inc. (Nasdaq:SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40C to +150C junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nm Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.

“Arbe’s ultra-high-resolution radar is leveraging this cutting edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”

“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”

“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”

GLOBALFOUNDRIES & Synopsys at Mobile World Congress 2019

On February 25, 2019, Synopsys will join the GLOBALFOUNDRIES NEXTech Lab Theater Session at MWC19. A panel discussion, with leading industry experts, ​​including Joachim Kunkel, general manager of the Solutions Group at Synopsys, and Mike Cadigan, senior vice president of global sales, business development, customer and design engineering at GF, will offer insights about the importance of intelligent connectivity, the growth, demands, and innovations it is poised to bring, and its impacts across the semiconductor value chain. For more information, visit: https://www.globalfoundries.com/join-gf-mwc19.

Resources

For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:

Rice University integrated circuit (IC) designers are at Silicon Valley’s premier chip-design conference to unveil technology that is 10 times more reliable than current methods of producing unclonable digital fingerprints for Internet of Things (IoT) devices.

Rice’s Kaiyuan Yang and Dai Li will present their physically unclonable function (PUF) technology today at the 2019 International Solid-State Circuits Conference (ISSCC), a prestigious scientific conference known informally as the “Chip Olympics.” PUF uses a microchip’s physical imperfections to produce unique security keys that can be used to authenticate devices linked to the Internet of Things.

Considering that some experts expect Earth to pass the threshold of 1 trillion internet-connected sensors within five years, there is growing pressure to improve the security of IoT devices.

Yang and Li’s PUF provides a leap in reliability by generating two unique fingerprints for each PUF. This “zero-overhead” method uses the same PUF components to make both keys and does not require extra area and latency because of an innovative design feature that also allows their PUF to be about 15 times more energy efficient than previously published versions.

“Basically each PUF unit can work in two modes,” said Yang, assistant professor of electrical and computer engineering. “In the first mode, it creates one fingerprint, and in the other mode it gives a second fingerprint. Each one is a unique identifier, and dual keys are much better for reliability. On the off chance the device fails in the first mode, it can use the second key. The probability that it will fail in both modes is extremely small.”

As a means of authentication, PUF fingerprints have several of the same advantages as human fingerprints, he said.

“First, they are unique,” Yang said. “You don’t have to worry about two people having the same fingerprint. Second, they are bonded to the individual. You cannot change your fingerprint or copy it to someone else’s finger. And finally, a fingerprint is unclonable. There’s no way to create a new person who has the same fingerprint as someone else.”

PUF-derived encryption keys are also unique, bonded and unclonable. To understand why, it helps to understand that each transistor on a computer chip is incredibly small. More than a billion of them can be crammed onto a chip half the size of a credit card. But for all their precision, microchips are not perfect. The difference between transistors can amount to a few more atoms in one or a few less in another, but those miniscule differences are enough to produce the electronic fingerprints used to make PUF keys.

For a 128-bit key, a PUF device would send request signals to an array of PUF cells comprising several hundred transistors, allocating a one or zero to each bit based on the responses from the PUF cells. Unlike a numeric key that’s stored in a traditional digital format, PUF keys are actively created each time they’re requested, and different keys can be used by activating a different set of transistors.

Adopting PUF would allow chipmakers to inexpensively and securely generate secret keys for encryption as a standard feature on next-generation computer chips for IoT devices like “smart home” thermostats, security cameras and lightbulbs.

Encrypted lightbulbs? If that sounds like overkill, consider that unsecured IoT devices are what three young computer savants assembled by the hundreds of thousands to mount the October 2016 distributed denial-of-service attack that crippled the internet on the East Coast for most of a day.

“The general concept for IoT is to connect physical objects to the internet in order to integrate the physical and cyber worlds,” Yang said. “In most consumer IoT today, the concept isn’t fully realized because many of the devices are powered and almost all use existing IC feature sets that were developed for the mobile market.”

In contrast, the devices coming out of research labs like Yang’s are designed for IoT from the ground up. Measuring just a few millimeters in size, the latest IoT prototypes can pack a processor, flash memory, wireless transmitter, antenna, one or more sensors, batteries and more into an area the size of a grain of rice.

PUF is not a new idea for IoT security, but Yang and Li’s version of PUF is unique in terms of reliability, energy efficiency and the amount of area it would take to implement on a chip. For starters, Yang said the performance gains were measured in tests at military-grade temperatures ranging from 125 degrees Celsius to minus 55 degrees Celsius and when supply voltage dropped by up to 50 percent.

“If even one transistor behaves abnormally under varying environmental conditions, the device will produce the wrong key, and it will look like an inauthentic device,” Yang said. “For that reason, reliability, or stability, is the most important measure for PUF.”

Energy efficiency also is important for IoT, where devices can be expected to run for a decade on a single battery charge. In Yang and Li’s PUF, keys are created using a static voltage rather than by actively powering up the transistor. It’s counterintuitive that the static approach would be more energy efficient because it’s the equivalent of leaving the lights on 24/7 rather than flicking the switch to get a quick glance of the room.

“Normally, people have sleep mode activated, and when they want to create a key, they activate the transistor, switch it once and then put it to sleep again,” Yang said. “In our design, the PUF module is always on, but it takes very little power, even less than a conventional system in sleep mode.”

On-chip area — the amount of space and expense manufacturers would have to allocate to put the PUF device on a production chip — is the third metric where they outperform previously reported work. Their design occupied 2.37 square micrometers to generate one bit on prototypes produced using 65-nanometer complementary metal-oxide-semiconductor (CMOS) technology.

The research was funded by Rice University.

Researchers at CEA-Leti and Stanford University have developed the world’s first circuit integrating multiple-bit non-volatile memory (NVM) technology called Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM. Target applications include energy-efficient, smart-sensor nodes to support artificial intelligence on the Internet of Things, or “edge AI”.

The proof-of-concept chip has been validated for a wide variety of applications (machine learning, control, security). Designed by a Stanford team led by Professors Subhasish Mitra and H.-S. Philip Wong and realized in CEA-Leti’s cleanroom in Grenoble, France, the chip monolithically integrates two heterogeneous technologies: 18 kilobytes (KB) of on-chip RRAM on top of commercial 130nm silicon CMOS with a 16-bit general-purpose microcontroller core with 8KB of SRAM.

The new chip delivers 10-times better energy efficiency (at similar speed) versus standard embedded FLASH, thanks to its low operation energy, as well as ultra-fast and energy-efficient transitions from on mode to off mode and vice versa. To save energy, smart-sensor nodes must turn themselves off. Non-volatility, which enables memories to retain data when power is off, is thus becoming an essential on-chip memory characteristic for edge nodes. The design of 2.3 bits/cell RRAM enables higher memory density (NVM dense integration) yielding better application results: 2.3x better neural network inference accuracy, for example, compared to a 1-bit/cell equivalent memory.

The technology was presented on Feb. 19, at the International Solid-State Circuits Conference (ISSCC) 2019 in San Francisco in a paper titled, “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques”.

But NVM technologies (RRAM and others) suffer from write failures. Such write failures have catastrophic impact at the application level and significantly diminish the usefulness of NVM such as RRAM. The CEA-Leti and Stanford team created a new technique called ENDURER that overcomes this major challenge. This gives the chip a 10-year functional lifetime when continuously running inference with the Modified National Institute of Standards and Technology (MNIST) database, for example.

“The Stanford/CEA-Leti team demonstrated a complete chip that stores multiple bits per on-chip RRAM cell. Stored information is correctly processed when compared with previous demonstrations using standalone RRAM or a few cells in a RAM array,” said Thomas Ernst, Leti’s chief scientist for silicon components and technologies. “This multi-bit storage improves the accuracy of neural network inference, a vital component of AI.”

Mitra said the chip demonstrates several industry firsts for RRAM technology. These include new algorithms that achieve multiple bits-per-cell RRAM at the full memory level, new techniques that exploit RRAM features as well as application characteristics to demonstrate the effectiveness of multiple bits-per-cell RRAM at the computing system level, and new resilience techniques that achieve a useful lifetime for RRAM-based computing systems.

“This is only possible with a unique team with end-to-end expertise across technology, circuits, architecture, and applications,” he said. “The Stanford SystemX Alliance and the Carnot Chair of Excellence in NanoSystems at CEA-Leti enabled such a unique collaboration.”

GLOBALFOUNDRIES (GF) and Dolphin Integration, a provider of semiconductor IP, today announced a collaboration to develop a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of system-on-chip (SoC) on GF’s 22nm FD-SOI (22FDX) process technology for a wide range of high-growth applications such as 5G, IoT and automotive.

As part of the collaboration, Dolphin Integration and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias implementation on SoC designs. ABB is a unique 22FDX feature that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone.

The ABB solutions in development consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF’s 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs.

“We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO at Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.”

“In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of Ecosystem at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.”

Design kits with turnkey adaptive body bias solutions on GF’s 22FDX will be available starting in Q2 2019.

UltraSoC today announced a significant extension of its embedded analytics architecture, allowing designers and innovators to incorporate powerful data-driven features into their products. Developers in the automotive, storage and high performance computing industries can now integrate even more sophisticated hardware-based security, safety and performance tuning capabilities within their products, as well as reaping substantial time-to-market and cost benefits of using UltraSoC in the system on chip (SoC) development cycle.

The new features allow SoC designers to build on-chip monitoring and analytics systems with up to 65,000 elements, allowing seamless support for systems with many thousands of processors. Future iterations will allow even higher numbers of processors for Exascale systems. In addition to this dramatically improved scaling capability, new System Memory Buffer (SMB) IP allows the embedded analytics infrastructure to handle the high volumes of data generated by multicore systems, and to cope with “bursty” real-world traffic.

The new UltraSoC architecture is capable of monitoring effectively unlimited numbers of the internal building blocks that make up the most complex SoC products – and to analyze the impact on system-level behavior of the interactions between them. Such heterogeneous multicore chips are becoming increasingly common, particularly in enabling the artificial intelligence and machine learning technologies required in leading edge applications such as driverless cars.

Dave Ditzel, Founder and CEO of Esperanto, commented: “Esperanto’s mission is to enable the most energy-efficient high-performance computing systems for artificial intelligence, machine learning and other emerging applications. That requires us to put over a thousand RISC-V processors and AI/ML accelerators on a single chip; UltraSoC’s ability to match that level of scaling with monitoring, analytics and debug capabilities is a vital enabler for our business.”

UltraSoC CEO, Rupert Baines, said: “Our solutions are unique in the market in their ability to deal with multiple heterogeneous processors, standard and proprietary bus structures and even custom logic. This dramatic extension of our architecture takes us even further ahead of traditional solutions – both in the debug and development arena, and in allowing our customers to incorporate in-life monitoring capabilities to ensure security, functional safety and real-world performance optimization.”

UltraSoC’s system-level monitoring and analytics capabilities extend beyond the chip’s core processing components to all parts of the system – which may include thousands of IP blocks and subsystems, buses, interconnects and software. The new features within the UltraSoC architecture allow chip designers to deploy tens of thousands of monitoring and analytics modules within a single infrastructure. By providing an integrated, coherent analysis of the behavior of the system, UltraSoC significantly reduces the development burden for next-generation machine learning and artificial intelligence applications, as well as allowing the implementation of innovative product features such as hardware-based security and functional safety.

Extension of the UltraSoC architecture to encompass effectively unlimited monitoring capabilities helps developers to address the problems of systemic complexity which are among the most pressing issues faced by the electronics industry today. In addition to the sheer size of modern SoCs, machine learning and artificial intelligence algorithms are often inherently non-deterministic: because they devise their own ways of solving problems by ‘learning’, it is impossible for the system’s original designer to predict how they will behave in the final application. In-life monitoring of the chip’s behavior is therefore the only way of getting a true picture of what is going on inside the chip, and the wider system.

The complex interactions between multiple hardware blocks, firmware and software within SoCs have already made real-time in-life monitoring an indispensable tool for SoC designers. Changes in design approaches are also making system-wide monitoring more necessary than ever. Agile software development and ad hoc programming practices inherently require high-granularity visibility of the real system. Similarly, system hardware and software may not be ‘architected’ in the traditional sense: again, engineers need clear visibility of the run-time behavior of their systems.