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A new class of carbon nanotubes could be the next-generation clean-up crew for toxic sludge and contaminated water, say researchers at Rochester Institute of Technology.

Single-walled carbon nanotubes filter dirty water in experiments at RIT. Credit: John-David Rocha and Reginald Rogers

Single-walled carbon nanotubes filter dirty water in experiments at RIT. Credit: John-David Rocha and Reginald Rogers

Enhanced single-walled carbon nanotubes offer a more effective and sustainable approach to water treatment and remediation than the standard industry materials–silicon gels and activated carbon–according to a paper published in the March issue of Environmental Science Water: Research and Technology.

RIT researchers John-David Rocha and Reginald Rogers, authors of the study, demonstrate the potential of this emerging technology to clean polluted water. Their work applies carbon nanotubes to environmental problems in a specific new way that builds on a nearly two decades of nanomaterial research. Nanotubes are more commonly associated with fuel-cell research.

“This aspect is new–taking knowledge of carbon nanotubes and their properties and realizing, with new processing and characterization techniques, the advantages nanotubes can provide for removing contaminants for water,” said Rocha, assistant professor in the School of Chemistry and Materials Science in RIT’s College of Science.

Rocha and Rogers are advancing nanotube technology for environmental remediation and water filtration for home use.

“We have shown that we can regenerate these materials,” said Rogers, assistant professor of chemical engineering in RIT’s Kate Gleason College of Engineering. “In the future, when your water filter finally gets saturated, put it in the microwave for about five minutes and the impurities will get evaporated off.”

Carbon nanotubes are storage units measuring about 50,000 times smaller than the width of a human hair. Carbon reduced to the nanoscale defies the rules of physics and operates in a world of quantum mechanics in which small materials become mighty.

“We know carbon as graphite for our pencils, as diamonds, as soot,” Rocha said. “We can transform that soot or graphite into a nanometer-type material known as graphene.”

A single-walled carbon nanotube is created when a sheet of graphene is rolled up. The physical change alters the material’s chemical structure and determines how it behaves. The result is “one of the most heat conductive and electrically conductive materials in the world,” Rocha said. “These are properties that only come into play because they are at the nanometer scale.”

The RIT researchers created new techniques for manipulating the tiny materials. Rocha developed a method for isolating high-quality, single-walled carbon nanotubes and for sorting them according to their semiconductive or metallic properties. Rogers redistributed the pure carbon nanotubes into thin papers akin to carbon-copy paper.

“Once the papers are formed, now we have the adsorbent–what we use to pull the contaminants out of water,” Rogers said.

The filtration process works because “carbon nanotubes dislike water,” he added. Only the organic contaminants in the water stick to the nanotube, not the water molecules.

“This type of application has not been done before,” Rogers said. “Nanotubes used in this respect is new.”

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its IC Validator physical verification product has been successfully used for signoff on more than 100 tapeouts at advanced FinFET nodes. These tapeouts were completed with process technologies from multiple foundries at 16nm, 14nm, 10nm and 7nm. IC Validator’s massively parallel scalability to more than 200 CPUs has proven a critical factor in its ability to deliver overnight run times for today’s highly complex technology rules and very large designs. Synopsys has cooperated closely with foundries for several years to ensure the uncompromising accuracy of IC Validator’s results. This dependable accuracy has been key to IC Validator’s growing list of successful adoptions by industry leaders in many markets ranging from top CPU and GPU design companies in the US to leading fabless SoC designers in Taiwan and Japan.

IC Validator, part of the Synopsys Galaxy Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (ERC), dummy fill and DFM enhancement. IC Validator is configured to meet the challenges of today’s extremely large designs by enabling 8 CPUs with a single license. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than 200 CPUs. IC Validator enables coding at higher levels of abstraction and is architected for near-linear scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies.

IC Validator is a companion product to the IC Compiler II place-and-route system for In-Design physical verification. In-Design is enabled by the intelligent integration of IC Validator and IC Compiler II place-and-route, making it possible for engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology also enables new high-productivity functionality within the place-and-route environment, including automatic DRC repair, improved quality of timing results with timing-aware metal fill, and rapid ECO validation. In-Design physical verification eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.

“As manufacturing complexity is placing increased challenges on designers to deliver within schedule, it is extremely important that we continue to collaborate closely with leading foundries to deliver high-performance solutions,” said Bijan Kiani, vice president, product marketing, Design Group at Synopsys. “This milestone confirms our mature ecosystem strategy that has led to strong growth in IC Validator’s market share.”

For the last few decades, microchip manufacturers have been on a quest to find ways to make the patterns of wires and components in their microchips ever smaller, in order to fit more of them onto a single chip and thus continue the relentless progress toward faster and more powerful computers. That progress has become more difficult recently, as manufacturing processes bump up against fundamental limits involving, for example, the wavelengths of the light used to create the patterns.

Now, a team of researchers at MIT and in Chicago has found an approach that could break through some of those limits and make it possible to produce some of the narrowest wires yet, using a process that could easily be scaled up for mass manufacturing with standard kinds of equipment.

The new findings are reported this week in the journal Nature Nanotechnology, in a paper by postdoc Do Han Kim, graduate student Priya Moni, and Professor Karen Gleason, all at MIT, and by postdoc Hyo Seon Suh, Professor Paul Nealey, and three others at the University of Chicago and Argonne National Laboratory. While there are other methods that can achieve such fine lines, the team says, none of them are cost-effective for large-scale manufacturing.

The new approach uses a self-assembly technique in which materials known as block copolymers are covered by a second polymer. They are deposited on a surface by first heating the precursor so it vaporizes, then allowing it to condense on a cooler surface, much as water condenses on the outside of a cold drinking glass on a hot day.

“People always want smaller and smaller patterns, but achieving that has been getting more and more expensive,” says Gleason, who is MIT’s associate provost as well as the Alexander and I. Michael Kasser (1960) Professor of Chemical Engineering. Today’s methods for producing features smaller than about 22 nanometers (billionths of a meter) across generally require building up an image line by line, by scanning a beam of electrons or ions across the chip surface — a very slow process and therefore expensive to implement at large scale.

The new process uses a novel integration of two existing methods. First, a pattern of lines is produced on the chip surface using standard lithographic techniques, in which light shines through a negative mask placed on the chip surface. That surface is chemically etched so that the areas that were illuminated get dissolved away, leaving the spaces between them as conductive “wires” that connect parts of the circuit.

Then, a layer of material known as a block copolymer — a mix of two different polymer materials that naturally segregate themselves into alternating layers or other predictable patterns — is formed by spin coating a solution. The block copolymers are made up of chain-like molecules, each consisting of two different polymer materials connected end-to-end.

“One half is friendly with oil, the other half is friendly with water,” Kim explains. “But because they are completely bonded, they’re kind of stuck with each other.” The dimensions of the two chains predetermine the sizes of layers or other patterns they will assemble themselves into when they are deposited.

Finally, a top, protective polymer layer is deposited on top of the others using chemical vapor deposition (CVD). This top coat, it turns out, is a key to the process: It constrains the way the block copolymers self-assemble, forcing them to form into vertical layers rather than horizontal ones, like a layer cake on its side.

The underlying lithographed pattern guides the positioning of these layers, but the natural tendencies of the copolymers cause their width to be much smaller than that of the base lines. The result is that there are now four (or more, depending on the chemistry) lines, each of them a fourth as wide, in place of each original one. The lithographed layer “controls both the orientation and the alignment” of the resulting finer lines, explains Moni.

Because the top polymer layer can additionally be patterned, the system can be used to build up any kind of complex patterning, as needed for the interconnections of a microchip.

Most microchip manufacturing facilities use the existing lithographic method, and the CVD process itself is a well-understood additional step that could be added relatively easily. Thus, implementing the new method could be much more straightforward than other proposed methods of making finer lines, such as the use of extreme ultraviolet light, which would require the development of new light sources and new lenses to focus the light. With the new method, Gleason says, “you wouldn’t need to change all those machines. And everything that’s involved are well-known materials.”

ams, a worldwide supplier of high performance sensor solutions, today announced the AS7225 tunable-white lighting smart system sensor, further broadening the solution set for sensor-integrated tunable-white lighting solutions. With the addition of the AS7225, OEM lighting manufacturers can access ams’ closed-loop CCT tuning and daylight compensation, while retaining the existing host microprocessor architecture in their smart lighting design. The result is higher precision, more flexible LED binning, and lower system costs for tunable white lighting systems.

The AS7225 is equipped with the product family’s industry-first embedded tri-stimulus CIE XYZ color sensor to enable precise color sensing with direct mapping to the International Commission on Illumination (CIE) 1931 color space which is recognized as the standard coordinate definition for human color perception. CCT and daylighting tuning directives are communicated to the host microprocessor via an industry-standard I2C interface, allowing IoT smart lighting manufacturers to avoid costly calibration and tuning algorithm development and reduce time to deployment.

“As the lighting industry moves to tunable solutions, the inclusion of closed loop sensor-driven integration not only increases white or daylighting tuning precision, it also loosens the required precision for both LED binning and system components. This results in cost reductions for both the overall bill of materials, as well as in time and cost savings in the materials management and manufacturing processes”, commented Tom Griffiths, Senior Marketing Manager at ams.

The AS7225 is an extension of ams’ Cognitive Lighting smart lighting manager family. The efficient AS7225 is available in a 4.5 x 4.7mm LGA package, for flexible integration into luminaires, light-engines and larger replacement lamps, such as LED linear T-LED products. The device provides precise CCT tuning direction between configured warm and cool white LED strings within a luminaire. In addition to the CCT- tuning functions, the AS7225 can additionally be used looking outward in luminaire designs to provide precise daylight management, or can deliver combined CCT-tuning and daylighting directives by the addition of ams’ TSL4531 ambient light sensor.

“Recent trends in LED device pricing show that chips have moved away from being the primary cost element in a typical commercial luminaire. This means that in just a few years, tunable lighting will become the standard for new commercial lighting installations”, Griffiths added. “The comfort, productivity and health benefits of good lighting have been clear for decades, and as it is becoming cost effective to do so, tunable lighting will be a key element in delivering those benefits from LED smart lighting platforms.”

Pricing for the AS7225 spectral tuning IoT smart lighting manager is set at $2.40 in quantities of 5,000 pieces, and is available in production volumes now.

Silego Technology, a developer of Configurable Mixed-signal Integrated Circuits (CMICs), announced today an extension of its performance-driven GFET3 Integrated Power Switch (IPS) portfolio. Addressing extremely PCB-space-constrained, high-performance applications in tablet PC, smartphones and fitness band markets, these three new WLCSP products cover high-side power control applications from 1 A to 4 A.

For smartphone and fitness band applications, the 0.64 mm2 (0.8 mm x 0.8 mm) SLG59M1730C (33 mΩ/1 A) and the SLG59M1736C (33 mΩ/2.2 A) are low-leakage, self-powered pFET IPSs that can operate from 2.5 V to 5.5 V supply voltages and draw very little supply current. Both products offer low-threshold ON/OFF control, fast output voltage discharge, and a novel, controlled input current profile on startup. Since small form-factor Li-ion batteries exhibit very low amp-hour capacities, the SLG59M1730C/SLG59M1736C’s controlled 16.5 mA inrush current profile on startup prevents Li-ion battery voltage sag when Bluetooth radios or other high current-demand operations are enabled. When compared to other 4-ball WLCSPs in the market with fast, fixed output voltage rise times, the magnitude of the inrush current – directly proportional to the load capacitor value – can be quite large. If the resultant inrush current is large enough to cause the Li-ion battery voltage to sag, an inadvertent system reset can result. Thus, the SLG59M1730C/SLG59M1736C’s controlled inrush current attribute prevents unintended system resets from occurring.

For higher-power tablet pc applications, the SLG59M1735C is a 10.5 mΩ/4 A nFET IPS with a full suite of protection features. Powered from 2.5 V to 5.5 V supplies, the input voltage range extends down to 0.9 V to accommodate 1.0 V high-current rails found in FPGA, ASIC, and processor power sequencing applications. The SLG59M1735C feature set includes: ON/OFF control, soft-start control, undervoltage detection, and two-level current-limit protection. When compared to other packaged products in Silego’s GFET3 portfolio with similar features, the 1.5 mm2 SLG59M1735C is a 50% smaller footprint. When compared to other 4 A WLCSP/DFN products in the market with similar protection features, the SLG59M1735C is a 14% to 32% smaller footprint.

Using Silego’s proprietary MOSFET design IP, these highly-reliable integrated protection devices offer world-class nFET and pFET low RDSON performance. Applying Silego’s proprietary CuFETTM technology, the Company’s design engineers deftly craft these products into very-small WLCSP footprints that maximize system-level performance while minimizing thermal gradients in space-constrained, medium-current applications.

Today, Transphorm Inc. announced that its second generation, JEDEC-qualified high voltage gallium nitride (GaN) technology is now the industry’s first GaN solution to earn automotive qualification—having passed the Automotive Electronics Council’s AEC-Q101 stress tests for automotive-grade discrete semiconductors.

Transphorm’s automotive GaN FET, the TPH3205WSBQA, offers an on-resistance of 49 milliOhms (mΩ) in an industry standard TO-247 package. The part initially targets on-board charger (OBC) and DC to DC systems for plug-in hybrid electric vehicles (PHEVs) and battery electric vehicles (BEV). Today, OBCs are uni-directional (AC to DC) using standard boost topologies. However, being that GaN FETs are bi-directional by nature, they become the perfect fit for the bridgeless totem-pole power factor correction (PFC) topology. Meaning, a bi-directional OBC can then be designed with GaN to reduce the number of silicon (Si) devices, weight and overall system cost of today’s solution.

“With the electrification of the automobile, the industry faces new system size, weight, performance, and cost challenges that can be addressed by GaN,” said Philip Zuk, Senior Director of Technical Marketing at Transphorm. “However, supplying this market means devices must meet the highest possible standards for Quality and Reliability, those set by the AEC. At Transphorm, we have a culture of Quality and Reliability. And, are proud to be leading the industry into the new era of in-vehicle power electronics.”

The automotive market is one of the fastest growing segments for all power semiconductors, with IHS Markit forecasting a $3 billion revenue by 2022. Due to its inherent attributes, Transphorm’s GaN can support a large portion of the market. When compared to incumbent tech such as superjunction MOSFETs, IGBTs and Silicon Carbide (SiC), those attributes include:

  • Up to 40 percent greater power density
  • Increased efficiency
  • Lower thermal budget
  • Reduced system weight
  • Up to 20 percent decrease in overall system cost
  • High volume manufacturing with 6-inch GaN on Silicon

As a result, Transphorm’s GaN can be used in other high voltage DC to DC automotive systems including air conditioning, heating, oil pumps and power steering.

Imec is granting its Lifetime of Innovation Award to Dr. Kinam Kim, President and General Manager of Semiconductor Business at Samsung Electronics. The selection recognizes Dr. Kim’s leadership and strategic vision, as well as his undeniable impact in the semiconductor industries.

The award ceremony will take place on May 16, during the global edition of the Imec Technology Forum (ITF), one of Europe’s leading tech events on technologies and solutions that will drive groundbreaking innovation across sectors in nano-electronics and the Internet of Things, smart health, smart cities, smart industries and smart energy.

“Dr. Kim has been a driving force at Samsung for more than 30 years, and the beacon the industry has used to navigate towards further innovations and technological breakthroughs in memory and computing,” states Luc Van den hove, president and CEO of imec. “His unparalleled contributions, leadership and strategic vision have not only paved the way for Samsung’s role as a world leader in the field, but have also shaped today’s society and our relation with computers, mobile and other similar devices.”

Dr. Kim joined Samsung Electronics in 1981, and led the development and advancement of various memory technologies such as DRAM and NAND flash, and logic technologies such as Application Processor and Communication Modem. As CEO of Samsung Advanced Institute of Technology (SAIT), he spearheaded the research and development of technologies that have significantly impacted the semiconductor industry, such as graphene, carbon nanotubes and quantum dots, advanced materials, 3D fusion technologies, batteries and printed electronics.

Imec’s Lifetime of Innovation Award was launched in 2015, in support of imec’s commitment to recognizing the prominent individuals who have made outstanding contributions to the industry. Previous recipients were Dr. Morris Chang in 2015 and Dr. Gordon Moore in 2016.

dr kim samsung

Brigham Young University researchers have developed new glass technology that could add a new level of flexibility to the microscopic world of medical devices.

A graduate student at BYU holds up a disc of microchips that have flexible glass membranes. Credit: Jaren Wilkey/BYU Photo

A graduate student at BYU holds up a disc of microchips that have flexible glass membranes. Credit: Jaren Wilkey/BYU Photo

Led by electrical engineering professor Aaron Hawkins, the researchers have found a way to make the normally brittle material of glass bend and flex. The research opens up the ability to create a new family of lab-on-a-chip devices based on flexing glass.

“If you keep the movements to the nanoscale, glass can still snap back into shape,” Hawkins said. “We’ve created glass membranes that can move up and down and bend. They are the first building blocks of a whole new plumbing system that could move very small volumes of liquid around.”

While current lab-on-a-chip membrane devices effectively function on the microscale, Hawkins’ research, recently published in Applied Physics Letters, will allow equally effective work at the nanoscale. Chemists and biologists could use the nanoscale devices to move, trap and analyze very small biological particles like proteins, viruses and DNA.

So why work with glass? According to lead study author and BYU Ph.D. student John Stout, glass has some great perks: it’s stiff and solid and not a material upon which things react, it’s easy to clean, and it isn’t toxic.

“Glass is clean for sensitive types of samples, like blood samples,” Stout said. “Working with this glass device will allow us to look at particles of any size and at any given range. It will also allow us to analyze the particles in the sample without modifying them.”

The researchers believe their device could also mean performing successful tests using much smaller quantities of a substance. Instead of needing several ounces to run a blood test, the glass membrane device created by Hawkins, Stout and coauthor Taylor Welker would only require a drop or two of blood.

Hawkins said the device should also allow for faster analysis of blood samples: “Instead of shipping a vial of blood to a lab and have it run through all those machines and steps, we are creating devices that can give you an answer on the spot.”

There is an increased demand for portable on-site rapid testing in the healthcare industry. Much of this is being realized through these microfluidic systems and devices, and the BYU device could take that testing to the next level of detail.

“This has the promise of being a rapid delivery of disease diagnosis, cholesterol level testing and virus testing,” Hawkins said. “In addition, it would help in the process of healthcare knowing the correct treatment method for the patient.”

Hydrogen is both the simplest and the most-abundant element in the universe, so studying it can teach scientists about the essence of matter. And yet there are still many hydrogen secrets to unlock, including how best to force it into a superconductive, metallic state with no electrical resistance.

“Although theoretically ideal for energy transfer or storage, metallic hydrogen is extremely challenging to produce experimentally,” said Ho-kwang “Dave” Mao, who led a team of physicists in researching the effect of the noble gas argon on pressurized hydrogen.

It has long been proposed that introducing impurities into a sample of molecular hydrogen, H2, could help ease the transition to a metallic state. So Mao and his team set out to study the intermolecular interactions of hydrogen that’s weakly-bound, or “doped,” with argon, Ar(H2)2, under extreme pressures. The idea is that the impurity could change the nature of the bonds between the hydrogen molecules, reducing the pressure necessary to induce the nonmetal-to-metal transition. Previous research had indicated that Ar(H2)2 might be a good candidate.

Surprisingly, they discovered that the addition of argon did not facilitate the molecular changes needed to initiate a metallic state in hydrogen. Their findings are published by the Proceedings of the National Academy of Sciences.

The team brought the argon-doped hydrogen up to 3.5 million times normal atmospheric pressure–or 358 gigapascals–inside a diamond anvil cell and observed its structural changes using advanced spectroscopic tools.

What they found was that hydrogen stayed in its molecular form even up to the highest pressures, indicating that argon is not the facilitator many had hoped it would be.

“Counter to predictions, the addition of argon did not create a kind of ‘chemical pressure’ on the hydrogen, pushing its molecules closer together. Rather, it had the opposite effect,” said lead author Cheng Ji.

Transition metal oxides (TMO) are extensively studied, technologically important materials, due to their complex electronic interactions, resulting in a large variety of collective phenomena. Memory effects in TMO’s have garnered a huge amount of interest, being both of fundamental scientific interest and technological significance.

Dr. Amos Sharoni of Bar-Ilan University’s Department of Physics, and Institute of Nanotechnology and Advanced Materials (BINA), has now uncovered a new kind of memory effect, unrelated to memory effects previously reported.

Dr. Sharoni, together with his student Naor Vardi, and supported by theoretical modelling by Yonatan Dubi of Ben-Gurion University in the Negev, utilized a simple experimental design to study changes in the properties of two TMOs, VO2 and NdNiO3, which undergo a metal-insulator phase-transition. Their results, just published in the journal Advanced Materials, not only demonstrate a new phenomenon but, importantly, also provide an explanation of its origin.

Ramp reversal memory

Metal-insulator transitions are transitions from a metal (material with good electrical conductivity of electric charges) to an insulator (material where conductivity of charges is quickly suppressed). These transitions can be achieved by a small variation of external parameters such as pressure or temperature.

In Sharoni’s experiment, when heated the studied TMOs transit from one state to another, and their properties undergo a change, beginning in a small area where “islands” develop and then grow, and vice-versa during cooling, similar to the coexistence of ice and water during melting. Sharoni cooled his samples while transition was in process, and then examined what happened when they were reheated. He found that when the reheated metal-oxide reached the temperature point at which re-cooling had occurred, that is, in the phase coexistence state – an increase in resistance was measured. And this increase in resistance was observed at each different point at which cooling was initiated. This previously unknown and surprising phenomenon demonstrates the creation of a “memory”.

Sharoni explains: “When the temperature ramp is reversed, and the sample is cooled rather than heated, the direction change creates a “scar” wherever there is a phase-boundary between the conducting and insulating islands. The ramp reversal sequence “encrypts” in the TMO a “memory” of the reversal temperature, which is manifested as increased resistance”. Moreover, it is possible to create and store more than one “memory” in the same physical space.

Sharoni likens the creation of a “scar” to the motion of waves on the seashore. A wave rushes up the beach and as it recedes it leaves a small sandy mound at the furthest point that it reached. When the wave returns it slows and brakes as it reaches the mound obstacle in its path. However, if a strong wave follows, it rushes over the mound and destroys it. Similarly, Sharoni found that further heating the TMO enables it to complete transition and to cross the scarred boundaries, “healing” the scars and immediately erasing the memory. In contrast cooling does not erase them.

Technology and security

The results of Sharoni’s work will have important impact on additional research, both experimental and theoretical, and the simplicity of the experimental design will enable other groups studying relevant systems to perform similar measurements with ease.

The multi-state nature of the memory effect, whereby more than one piece of information can coexist in the same space, could be harnessed for memory technology. And while deleted computer data is not secure and can be recovered, at least partially, by talented hackers, the “erase-upon-reading” property of this system could make an invaluable contribution to security technologies.