Tag Archives: letter-semi-top

10:30 am -12:30 pm
Digital Medicine and Remote Patient Monitoring
Moscone North, TechXPOT North

10:30 am – 12:30 pm
Materials & Packaging for Automotive
Meet the Experts Theater Moscone North, Smart Transportation Pavilion

10:30 am – 12:55 pm
Lithography at 5nm and Below
Moscone South, TechXPOT South

10:30 am – 12:30 pm
New Monitoring and Metrology Technologies, Wet and Dry
Meet the Experts Theater Moscone South, Smart Manufacturing Pavilion

1:30 pm – 4:00 pm
Connected Car to Connected World – The Road to Monetization
Meet the Experts Theater Moscone North, Smart Transportation Pavilion

2:00 pm – 4:00 pm
Data and AI: Ahead of the Curve — Applications Already Incorporating Big Data and AI
Moscone North, TechXPOT North

2:00pm to 4:00pm
Scaling Every Which Way!
Moscone South, TechXPOT South

By Shannon Davis

Steve Jobs. Benjamin Franklin. Albert Einstein. Marie Curie. What do these world-changers all have in common? Where did their drive to innovate come from? Melissa Schilling, PhD, had to find out.

“Innovation and creativity has been a hot area of research for a long time, but we don’t tend to study outliers and in part that’s because there’s methodological challenges with that,” she explained to the audience during her keynote address on Tuesday at SEMICON West 2018.

Melissa Schilling, PhD, New York University

So, the New York University professor created a multiple case study research project to tackle these questions, which are addressed at length in her latest book, “Quirky: The Remarkable Story of the Traits, Foibles, and Genius of Breakthrough Innovators Who Changed the World.” Her book invites us into the lives of eight world-famous game-changers — Albert Einstein, Benjamin Franklin, Elon Musk, Dean Kamen, Nikola Tesla, Marie Curie, Thomas Edison, and Steve Jobs – and identifies the common traits and experiences that drove them to make spectacular breakthroughs, again and again. Schilling believed that once we understand what makes someone a serial innovator; we can also understand the breakthrough innovation potential in all of us.

The first common trait Schilling identified in her research was a sense of separateness – a discovery that she found remarkable.

“I thought most people would be super connected with lots of diverse connections,” she said. “I was wrong about that. Every single person I studied, with the exception of Benjamin Franklin, had this…feeling of detachment.”

Einstein, said Schilling, even went so far as to say he didn’t need direct contact with individual humans, even his own family. Marie Curie and her husband eventually sent both of their daughters to be raised by their grandparents, so that they could devote more time to their research. Dean Kamen’s feelings of separateness helped to shield him when his peers didn’t believe it was possible to create a two-wheeled wheelchair (which we now know as the Segway).

What can we learn from this? “First thing we have to learn is that we need norms that permit people to be unorthodox,” said Schilling. “We need to be able to embrace weirdness.”

Schilling pushed back against the idea of brainstorming teams in the tech world, a practice she says has potential innovators stuck putting out ideas that are more likely to get consensus from the rest of their team. She instead suggested to allow employees to work alone first, to commit to an idea and elaborate on it before sharing it with a team.

“Brainstorming teams cause people to come to mediocre compromises,” she said.

The second shared trait of serial innovators Schilling discussed was self-efficacy.

“Self-efficacy is that faith you have that you can overcome obstacles to achieve your goals and it makes you take on bigger projects,” Schilling explained.

She pointed to Elon Musks’ persistence in developing reusable rockets, in spite of NASA’s claims that it couldn’t be done, and Nikola Tesla’s dream of harnessing the power of Niagara Falls to provide electricity, despite having only seen a picture of Niagara on a postcard when he was a child in Croatia.

“Encourage people to try even if they fail,” she said, and warned against rescuing people who could benefit from learning things on their own.

The third trait Schilling outlined was one she said seven of the eight innovators possessed, which was having an intensely idealistic goal that mattered more to them than just about anything else.

“When you have an idealistic goal that people in your company can identify with, they’re going to work harder, they’re going to work longer, they’re going to think bigger, and they’re going to love it more,” she said.

And while timing and luck often did play an undeniable role in many of the serial innovators lives, Schilling was most surprised to learn that access to capital didn’t affect her research subjects’ abilities to innovate.

“Every single one of these people… started out flat broke,” she said. “They did not become innovators because they had access to capital.”

What was more important, she said, was their access to other people who had resources.

“One of the most valuable things you can do is help connect people to the other people they need,” she concluded.

By Ed Korczynski

As the commercial IC fabrication industry continues to shrink field-effect transistor (FET) sizes, 2D planar structures evolved into 3D fins which are now evolving into 3D stacks of 2D nano-sheets. While some researchers continue to work on integrating non-silicon “alternate channel” materials into finFETs for next generation logic ICs, published results from labs around the world now show that nano-wires or nano-sheets of silicon will likely follow silicon finFETs in high-volume manufacturing (HVM) fabs. 

Today’s finFETs are formed using self-aligned multi-patterning (SAMP) process flows with argon-fluoride immersion (ArFi) deep ultra-violet (DUV) steppers to provide arrays of equal-width lines. A block-mask can then pattern sets of lines into different numbers of fins per transistor to allow for different maximum current flows across the chip. When considering the next CMOS device structure to replace finFETs in commercial HVM we must anticipate the need to retain different current flows (ION) across the IC.

Gate-all-around (GAA) FETs can provide outstanding ION/IOFFratios, and future logic ICs could be built using either horizontal or vertical GAA devices. While vertical-GAA transistors have been explored for memory chips, their manufacturing process flows are significantly different from  those used to form finFETs. In contrast, horizontal-GAA FETs processing can be seen as a logical extension of flows already developed and refined for fin structuring.

“With a number of scaling boosters, the industry will be able to extend finFET technology to the 7 or even 5nm node,” said An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the finFET process steps.”

The figure shows simplified cross-sections of a finFET with fin height (FH) of 50 nm along with two different stacks of lateral nano-sheets (LNS, also known as horizontal nano-sheets or HNS), where the current flows would be normal to the cross-section. HNS are variations of horizontal nano-wires (HNW) with the wires widened, shown as 11nm and 21nm in the figure. The HNS are epitaxial-silicon grown separated by sacrificial sacrificial silicon-germanium (SiGe) spacer layers.

Cross-sectional schematics of idealized (left) 50nm high finFET, (center) 5nm high by 11nm wide lateral-nano-sheets at 12-18nm vertical pitch, and (right) lateral-nano-sheets 21nm wide. (Source: imec)

In an exclusive interview with Solid State Technology, Steegen discussed a few details of the process extensions needed to convert finFETs into HNS-FETs. The same work-function ALD metals can be used to tune threshold voltages such that one epi-stack process can grow silicon for both n-type and p-type FETs. Happily, no new epitaxial reactors nor precursor materials are needed. Isotropic etch of the SiGe vertical spacers, and then filling the spaces with a dielectric deposition may be the only new unit-processes needed.

Alternate channel wires and sheets

At the 2018 Symposia on VLSI Technology and Circuits, imec presented two papers on germanium as an alternate channel material for nanowire pFET devices. In the first paper they studied the electrical properties of strained germanium nanowire pFETs as high-end analog and high-performance digital solutions. The second paper demonstrated vertically-stacked GAA highly-strained germanium nanowire pFETs.

The commercial IC fab industry has considered use of alternate channels for planar devices and for finFETs, yet so far has found extensions of silicon to work well-enough for pFETs. Likewise, the first generation of HNS will likely use silicon channels for both nFETs and pFETs. Germanium GAA pFETs thus represent the ability to shrink HNS devices for future nodes.

9:00 am – 9:35 am
KEYNOTE: Machine Learning The Potential to Transform the Semiconductor Industry
Mark Papermaster, Advanced Micro Devices
Yerba Buena Theater

9:35 am – 9:50 am
KEYNOTE: The Future of Autonomy: Semiconductors in the Driver’s Seat
Wolfgang Juchmann, AutonomouStuff
Yerba Buena Theater

9:50 am – 10:30 am
KEYNOTE: Industrial AI Applications and Edge Intelligence
Amir Husain, SparkCognition
Yerba Buena Theater

10:30 am – 12:30 pm
SMART MANUFACTURING: Machine Learning and AI in Microelectronics Manufacturing
Moscone South, Smart Manufacturing Pavilion

10:30 am – 11:30 am
PANEL: Federal Strategy for Semiconductor and Microelectronics Innovation
Yerba Beuna Theater

2:00 pm – 4:00 pm
SMART TRANSPORTATION: Future of Automobility Supply Chain: Semiconductors and the New Technology Stack
Moscone North, TechXPOT North

Data economy era begins

July 10, 2018

By Shannon Davis

Speaking at imec ITF Forum on Tuesday, Scott DeBoer, Executive Vice President of Technology Development at Micron opened his keynote address with a video that featured astounding statistics: Micron memory and storage is a part of storing the data generated by practically every type of smart device and high speeding computer processing – nearly 2.5 quintillion bytes per day.

“We’re turning information into insights and activating data to reach your higher realms of productivity and innovation,” the video’s narrator said. “We are Micron, and we are transforming how the world uses information to enrich lives.”

This would be the central theme of DeBoer’s talk, as he outlined the disruptive technology advancements taking place in the memory world and the markets they impact. According to DeBoer, we are in the early stages of the data economy.

The data economy in 2017, DeBoer indicated in his presentation, reported about 22,000 billion gigabytes created that year, compared to previous computer eras in the earlier part of the century, when about 250 billion gigabytes were created per year on average. The early stages of artificial intelligence, smart businesses, smart homes, and the interconnection of so many devices led DeBoer to make an astonishing prediction.

“Looking forward to 2021,” he said, “I’m projecting now: 62,000 billion gigabytes [per year]. Just a phenomenal growth path.”

DeBoer said continued scaling of DRAM and 3D NAND as well as the emergence of 3D XPoint memory technology would be responsible for helping maintain this kind of explosive growth in the memory sector. 3D XPoint memory technology is considered a storage class memory, and, according to DeBoer, is the only emerging memory currently.

“The way that we approach memory technology today…is quite different,” said DeBoer.

DRAM technology 15 years ago, he said, was built around enabling a personal computer system, where the quality requirements for power and performance were well-defined, and scaling continued along an expected path for many years. Today, however, the broad spectrum of technologies available and emerging markets today puts varying requirements on DRAM technology

“The same DRAM component that is ideal for a data center is absolutely not ideal for either automotive or for a mobile kind of application,” said DeBoer.

In addition to scaling, Micron has had to identify different kinds of innovations, thinking outside the box to get the kinds of performance and cost effectiveness through the years in ways that were different than just scaling memory chips.

“It’s not just about scaling, it’s about coming up with other kinds of ideas for being able to improve performance and cost structure to get those high densities for these applications,” DeBoer said. One example of this he discussed was CMOS under array, which is taking 3D technology and performance to a new level: “By taking that logic technology and putting it all underneath your array and changing the architecture of the memory, you can fundamentally change the cost structure and you fundamentally changed the performance.”

DeBoer explained that this technology take a manufacturable density of NAND and basically uses the infrastructure of that technology, and the new technology is simply the interconnect between the two layers. This, he said, takes the pressure off of the equipment industry in terms of a variety of process capabilities. It also paves the way for future NAND scaling.

Near the end of his presentation, the audience chuckled along with him as DeBoer talked about building a computer at home with his son over the fourth of July holiday weekend.

“I’m probably one of the only people that actually appreciated the fact that the memory cost was very high,” he laughed.

9:00 am – 9:30 am
KEYNOTE: Breakthrough Innovators Who Changed the World
Melissa Schilling, PhD, New York University and Author
Yerba Buena Theater

9:45 am – 10:10 am
KEYNOTE: The Era of Artificial Intelligence
Dr. John E. Kelly, III, Cognitive Solutions and IBM Research
Yerba Buena Theater

10:10 am – 11:00am
PANEL: AI Design Forum—Overcoming the Memory Wall
Yerba Buena Theater

11:00 am – 11:25 am
KEYNOTE: AI—The Perfect Storm—An Industry Call to Action
Gary Dickerson, Applied Materials
Yerba Buena Theater

2:00 pm – 2:30 pm
KEYNOTE: William Dally, Efficient Hardware and Methods for Deep Learning
Yerba Buena Theater Tuesday, July 10

2:30 pm –  3:30 pm
SEMI Bulls & Bears
Yerba Buena Theater Tuesday, July 10 2:30pm to

5:00 pm – 9:00 pm
Leti Workshop
W Hotel – 181 3rd St., San Francisco

By Paula Doe

Chip testing is becoming smarter and more complex, creating growing requirements to stream data in real time and ensure it is ready to use for analysis, regardless of the vendor source.

Adaptive testing using machine learning to predict die performance in a downstream test can reduce the number of cycles by as much as 40 per cent without compromising test performance, notes Dan Sebban, VP of data analysis, OptimalPlus, who’ll speak on machine learning challenges at SEMICON West’s Test Vision 2020 program. “As devices and their test requirements grow in complexity, the motivation for automating adaptive test greatly increases,” he states, adding that characteristics such as die location on the wafer, defects on neighboring die, condition of the tester, and test values near the specification limits can help predict which die are likely to be good.

“The big issue we see is that while everyone likes the idea of machine learning, it remains a black box model, with little visibility into why it makes the decisions it does,” adds Sebban. In addition, a suitable infrastructure to run, deploy and assess a machine learning model in real time is required. “There is still some hesitation to adopt machine learning. It’s a big change of mindset. While building the confidence to use machine learning will take time and experience, using the technology to automate big data analysis with the relevant infrastructure may be our best alternative to reduce test cost.”

Systems test and parts-per-billion quality become the rule

Systems test will continue to become more prominent and more complex as chips and packages shrink, affirms Stacy Ajouri, Texas Instruments system integration engineer and Test Vision 2020 event chair. “Even IC makers now need to start doing more systems test.” And as more ICs are used in automotive applications, the distinction between consumer and automotive requirements is blurring, driving demand in other markets for higher precision test with parts-per-billion defectivity requirements.

“Intelligent test gets increasingly challenging as devices become more complex and as testing moves from distinguishing good from bad devices to figuring out how to repair and trim marginal devices to make them good,” adds Derek Floyd, Advantest director of business development, this year’s program chair.

“We’re highlighting efforts to create the infrastructure the industry needs to manage big data for machine learning with test platforms from different vendors,” says Ajouri, citing work on new standards for streaming data from the testers and labeling critical steps in consistent language to simplify the use of data from different platforms in real time. “I have 10 platforms from multiple vendors, and I need them to mean exactly the same thing by ‘lot’ so I don’t have to sort it out before I can use the data,” she says.

Are devices becoming too complicated to test at the required price point?

Can testing be economical with up to a million die per wafer, 50 data points per die, a requirement for parts-per-billion accuracy, and the need to identify parts that test good now but that might fail in the future? Organizers of the event invite chipmakers and test suppliers to debate the issue. “The speed of innovation in the semiconductor industry challenges test to keep pace,” notes Floyd. “The product we’re testing is always ahead of the product we have to test it with.”

The two-day event features sessions on automotive test; big data and machine learning for adaptive test; handling and interface issues such as over-the-air testing;  and a general session covering memory and RF test.

By Paula Doe, SEMI

With artificial intelligence (AI) rapidly evolving, look for applications like voice recognition and image recognition to get more efficient, more affordable, and far more common in a variety of products over the next few years. This growth in applications will drive demand for new architectures that deliver the higher performance and lower power consumption required for widespread AI adoption.

“The challenge for AI at the edge is to optimize the whole system-on-a-chip architecture and its components, all the way to semiconductor technology IP blocks, to process complex AI workloads quickly and at low power,” says Qualcomm Technologies Senior Director of Engineering Evgeni Gousev, who will provide an update on the progress of AI at the edge in a Data and AI program at SEMICON West, July 10-12 in San Francisco.

Qualcomm Snapdragon 845 uses heterogeneous computing across the CPU, GPU, and DSP for power-efficient processing for constantly evolving AI models. Source: Qualcomm

A system approach that optimizes across hardware, software, and algorithms is necessary to deliver the ultra-low power – to a sub 1-milliwatt level, low enough to enable always-on machine vision processing – for the usually energy-intensive AI computing. From the chip architecture perspective, processing AI workloads with the most appropriate engine, such as the CPU, GPU, and DSP with dedicated hardware acceleration, provides the best power efficiency – and flexibility for dealing with rapidly changing AI models and growing diversity of applications.

“But we’re going to run out of brute force options, so the future opportunity is more innovations with new architectures, dedicated hardware, new algorithms, and new software.” – Evgeni Gousev, Qualcomm Technologies

“So far it’s been largely a brute force approach using conventional architectures and cloud-based infrastructure,” says Evgeni. “But we’re going to run out of brute force options, so future opportunities lie in developing innovative architectures, dedicated hardware, new algorithms, and new software. Innovation will be especially important for AI at the edge and applications requiring always-on functionality. Training is mostly in the cloud now, but in the near future it will start migrating to the device as the algorithms and hardware improve. AI at the edge will also  remove some privacy concerns,  an increasingly important issue for data collection and management.”

Practical AI applications at the edge where resources are constrained run the gamut, spanning smartphones, drones, autonomous vehicles, virtual reality, augmented reality and smart home solutions such as connected cameras. “More AI on the edge will create a huge opportunity for the whole ecosystem – chip designers, semiconductor and device manufacturers, applications developers, and data and service providers. And it’s going to make a significant impact on the way we work, live, and interact with the world around us,” Evgeni said.

Future generations of chips may need more disruptive systems-level change to handle high data volumes with low power

A next-generation solution for handling the massive proliferation of AI data could be a nanotechnology system, such as the collaborative N3XT (Nano-Engineered Computing Systems Technology) project, led by H.S. Philip Wong and Subhasish Mitra at Stanford. “Even with next-generation scaling of transistors and new memory chips, the bottlenecks in moving data in and out of memory for processing will remain,” says Mitra, another speaker in the SEMICON West program. “The true benefits of nanotechnology will only come from new architectures enabled by nanosystems. One thing we are certain of is that massively more capable and more energy-efficient systems will be necessary for almost any future application, so we will need to think about system-level improvements.”

Major improvement in handling high volumes of data with low high energy use will require system-level improvements, such as monolithic 3D integration of carbon nanotube transistors in the multi-campus N3XT chip research effort. Source: Stanford University

That means carbon nanotube transistors for logic, high density non-volatile MRAM and ReRAM for memory, fine-grained monolithic 3D for integration, new architectures for computation immersed in memory, and new materials for heat removal. “The N3XT approach is key for the 1000X energy efficiency needed,” says Mitra.

“One thing we are certain of is that massively more capable and more energy efficient systems will be necessary for almost any future application, so we will need to think about system-level improvements.” – Subhasish Mitra, Stanford University

Researchers have demonstrated improvements in all these areas, including multiple hardware nanosystem prototypes targeting AI applications. The researchers have transferred multiple layers of as-grown carbon nanotubes to the target wafer to significantly improve CNT density. They have developed a low-power TiN/HfOx/Pt ReRAM whose low-temperature CNT and ReRAM processes enable multiple vertical layers to be grown on top of one another for ultra-dense and fine-grained monolithic 3D integration.

Other speakers at the Data and AI TechXpot include Fram Akiki, VP Electronics, Siemens; Hariharan Ananthanarayanan, motion planning engineer, Osaro; and David Haynes, Sr. director, strategic marketing, Lam Research.  See SEMICONWest.org.

By Lynnette Reese

On Wednesday, Intel Corporation’s Katherine Winter, Vice President of the Automated Driving Group, delivered a keynote that many would think is off-topic from the usual at SemiCon West: ”Big Data in Autonomous Driving.” She revealed that autonomous driving will shift the semiconductor industries’ focus to processing terra flops of data at blinding speeds with low latency. Winter stated, “A lot of the testing that’s going on today is to find what is the right level of MIPS to have the safest possible drive.” Winter addressed the need for computing power by the semiconductor industry to meet the challenges that autonomous driving for the passenger economy will pose. Intel, in working with Strategy Analytics, finds that the Passenger Economy may be worth $7 trillion by 2050. The largest factor holding this new business space back may very well be consumer acceptance.

The burden on semiconductor processors and supporting ICs will be driven part by data. Massive amounts of data will be driven by multiple sensors, “so that you, if you are riding in it, you trust that the vehicle knows what it’s doing…you want to know that it can handle snow and ice.” The sensors complement each other. “As we go through more and more testing, and there’s more of those vehicles out there, we are learning about the combinations, how much redundancy, things like that, that you actually need in the vehicle.” Emerging pedestrians, variable weather conditions, and myriad navigation issues from differing state regulations to undocumented construction and potholes also contribute to the need for data from differing variables aimed at every possibility.

Such enormous amounts of data come not only as technical data from sensors on the car and from infrastructure, but from crowd-sourced data as well as personal data for drivers and passengers. Crowd-sourced data might include reporting new obstacles or construction to be incorporated into the AV’s navigating knowledge. The autonomous learning cycle continues as cars upload data to the cloud, which shares and uses the data to train other vehicles on the new information. Personal data gathered from within the car includes information about the passengers which will be critical to the new passenger economy as AVs become the foundation for new markets for services formed for passengers within the vehicle. New applications like robo-taxis, managing fleets of delivery trucks, and crowd-sourcing data for navigation and finding parking are within reach.

Challenges translate to the semiconductor industry as we try and solve associated problems. How do we store and share the data? What do we do with the data, and what data is saved? Areas of focus in this developing economy will be the speed of critical information and processing workload. Security is also a critical part of the AV vision. Both privacy and overall resistance to cyberattacks are of genuine concern. “How do we keep it secure? How do we make sure that there’s not a way for cyberattacks once those vehicles are out there?” posed Winter. In short, how do we trust autonomous vehicles in every way?

As we get to thousands and millions of autonomous vehicles, we will also need to understand how many we want to manage at one time. At scale, we can share safety data, create standards, and even promote an industry platform. Winter acknowledged that the semiconductor industry is not new to challenges, but indicated that the landscape will change, “We think we know what the sensors are, we think we know that kind of data is generated, but we can’t imagine what we are going to know in two years based on the speed of acceleration that we have seen so far developing in this space.”

The “Passenger Economy,” a term coined by Intel CEO Brian Krzanich, is estimated at $7 trillion by 2050. (Source: Strategy Analytics).

The “Passenger Economy,” a term coined by Intel CEO Brian Krzanich, is estimated at $7 trillion by 2050. (Source: Strategy Analytics).

8:30 am –12:30 pm
Get Smart: SEMI/Gartner, Bulls & Bears Industry Outlook
Yerba Buena Theater

10:30 am – 12:30 pm
SMART Automotive
Meet the Expert Theater, Moscone West

10:30 am – 12:30 pm
The Economics of Choosing a Lithography Strategy
Moscone West, TechXPOT West

10:30 am –12:35 pm
5G Communications and the Next-generation Cloud
Moscone North, TechXPOT North

2:00 pm – 4:00 pm
The Economics of Density Scaling
Moscone West, TechXPOT West

2:00 pm – 4:00 pm
Exploring Electronics Requirements & Solutions for Medical Technology
Moscone North, TechXPOT North