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200mm fabs reawakening


July 13, 2016

By David Lammers, Contributing Editor

Buoyed by strong investments in China, 200mm wafer production is seeing a re-awakening, with overall 200mm capacity expected to match its previous 2006 peak level by 2019 (Figure 1).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to  open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Speaking at a SEMI/Gartner market symposium at SEMICON West, SEMI senior analyst Christian Dieseldorff said over the next few years “we don’t see 200mm fabs closing, in fact we see new ones beginning operation. To me, that is just amazing.”

The numbers back up the rebound. Excluding LEDs, the installed capacity of 200mm fabs will reach about 5.3 million wafers per month (wspm) in 2018, almost matching the 2007 peak of 5.6 million wspm. As shown in Figure 1, By 2019 as new 200mm fabs start up in China, 200mm wafer production will surge beyond the previous 2007 peak, a surprising achievement for a wafer generation that began more than 25 years ago. Figure 2 shows how capacity, which held steady for years, is now on the increase.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Case in point: On the opening day of Semicon West, Beijing Yangdong Micro announced a new OLED 200mm fab that will be opening in the second half of 2018 to make OLED drivers, according to Dieseldorff.

Over the past few years, Japan-based companies have closed 10 200mm fabs, mostly outdated logic facilities, while expanding production of discrete power and analog ICs on 200mm wafers. But with China opening several new 200mm fabs and the expansions of existing 200mm fabs worldwide, SEMI sees an additional 274,000 wafer starts per month of 200mm production over the 2015-2018 period, adding expansions and additional fabs, and subtracting closed facilities.

“One message from our research is that we believe the existing 200mm fabs are full. Companies have done what they can to expand and move tools around, and that is coming to an end,” he said. SEMI reckons that 19 new 200mm fabs have been built since 2010, at least six of them in China.

SEMI’s Christian Dieseldorff.

SEMI’s Christian Dieseldorff.

Dieseldorff touched on a vexing challenge to the 200mm expansion: the availability of 200mm equipment. “People have problems getting 200mm equipment, used and even new. The (200mm) market is not well understood by some companies,” he said. With a shortage of used 200mm equipment likely to continue, the major equipment companies are building new 200mm tools, part of what Dieseldorff described as an “awakening” of 200mm manufacturing.

 

China is serious

Sam Wang, a research vice president at Gartner who focuses on the foundry sector, voiced several concerns related to 200mm production at the SEMI/Gartner symposium. While SMIC (which has a mix of 200mm and 300mm fabs) has seen consistently healthy annual growth, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

The challenge, he said, is for China’s foundries which rely largely on legacy production to grow revenues in a competitive market. And things are not getting any easier. While production of has shown overall strength in units, Wang cautioned that price pressures are growing for many of the ICs made on 200mm wafers. Fingerprint sensor ICs, for example, have dropped in price by 30 percent recently. Moreover, “the installation of legacy nodes in 300mm fabs by large foundries has caused concern to foundries who depend solely on 200 mm.”

But Wang emphasized China’s determination to expand its semiconductor production. “China is really serious. Believe it,” he said.

New markets, new demand

The smart phone revolution has energized 200mm production, adding to a growing appetite for MEMS sensors, analog, and power ICs. Going forward, the Internet of Things, new medical devices, and flexible and wearable products may drive new demand, speakers said at the symposium.

Jason Marsh, director of technology for the government and industry-backed NextFlex R&D alliance based in San Jose, Calif., said many companies see “real potential” in making products which have “an unobtrusive form factor that doesn’t alter the physical environment.” He cited one application: a monitoring device worn by hospital patients that would reduce the occurrence of bed sores. These types of devices can be made with “comparatively yesteryear (semiconductor) technology” but require new packaging and system-level expertise.

Legacy devices made on 200mm wafers could get a boost from the increasing ability to combine several chips made with different technologies into fan out chip scale packages (FO CSPs). Bill Chen, a senior advisor at ASE Group, showed several examples of FO CSPs which combine legacy ICs with processors made on leading-edge nodes. “When we started this wafer-level development around 2000 we thought it would be a niche. But now about 30 percent of the ICs used in smart phones are in wafer-level CSPs. It just took a lot of time for the market forces to come along.”

More coverage from this year’s SEMICON West can be found here.

SEMI projects that the worldwide semiconductor equipment market will be flat this year and will rebound in 2017 according to the mid-year edition of the SEMI Capital Equipment Forecast, released today at the SEMICON West exposition. SEMI forecasts that the total semiconductor equipment market will grow 1 percent in 2016 (reaching $36.9 billion) after contracting 3 percent in 2015. An increase of 11 percent is expected in 2017 for the market to reach $41.1 billion.

The following results are given in terms of market size in billions of U.S. dollars and percentage growth over the prior year:

SEMI® 2016 Mid-Year Equipment Forecast by Market Region

By EQUIPMENT TYPE

year-over-year

year-over-year

2015

2016F

% Change

2017F

% Change

Wafer Processing

28.78

29.33

1.9%

33.09

12.8%

Test

3.33

3.36

0.9%

3.46

3.0%

Assembly & Packaging

2.51

2.39

-5.0%

2.48

4.0%

Other Front End

1.90

1.86

-2.1%

2.05

10.2%

Total 

36.52

36.94

1.1%

41.08

11.2%

 

By REGION year-over-year year-over-year

2015

2016F

% Change

2017F

% Change

China

4.90

6.41

30.8%

7.24

12.9%

Europe

1.95

2.07

6.2%

2.46

18.8%

Japan

5.49

5.08

-7.6%

4.72

-7.0%

Korea

7.46

6.17

-17.3%

7.99

29.5%

North America

5.12

4.62

-9.8%

4.97

7.6%

ROW

1.97

3.13

58.9%

3.68

17.6%

Taiwan

9.63

9.46

-1.8%

10.02

5.9%

Total

36.52

36.94

1.1%

41.08

11.2%

*Totals may not add due to rounding; Source: SEMI, July 2016; Equipment Market Data Subscription (EMDS)

Equipment spending had a slow start in the beginning of the year and is expected to accelerate in the second half of the year. Spending growth will continue into 2017 driven by foundries, memory (both 3D NAND and DRAM), MPU, Power, and investments in China. Front-end wafer processing equipment is forecast to grow 2 percent in 2016 to total $29.3 billion, up from $28.8 billion in 2015.  The Test equipment segment is expected to total $3.4 billion, essentially flat when compared to last year. Assembly and packaging equipment and Other Front End equipment are forecast to contract this year, falling to $2.4 billion (-5 percent) and $1.9 billion (-2 percent), respectively.

“After a tepid 2015, device manufacturers are beginning to ramp their investments in key industry segments,” said Denny McGuirk, president and CEO of SEMI. “We expect capital spending to improve for the remainder of 2016 and into 2017.”

Taiwan is forecast to continue as the world’s largest spender with $9.5 billion estimated for 2016 and $10.0 billion for 2017. In 2016, China is projected to be the second largest spender at $6.4 billion, followed by Korea at $6.2 billion. For 2017, Taiwan is projected to maintain its leading position while the market in Korea will nudge past the market in China.

In 2016, year-over-year increases are expected to be largest for Rest of World (59 percent), China (31 percent), and Europe (6 percent). Projected year-over-year percentage increases for 2017 are forecast to be largest for Korea (30 percent increase), Europe (19 percent), Rest of World (18 percent) and China (13 percent). Visit www.semi.org/en/MarketInfo for more information.

By Pete Singer, Editor-in-Chief

On Monday, imec – the Leuven Belgium-based research consortium – hosted its annual imec Technology Forum (ITF) USA, a half-day conference at the Marriott Marquis. With the theme ‘Towards the Ultimate System’, imec’s speakers and industrial keynote speakers looked at the co-optimization of design and new technology, and how technology innovation can deliver the right building blocks to build these systems.

Delivering the keynote address at the event was Luc Van den hove, President and CEO of imec. He talked about how the world was in the middle of a decade of digital disruption brought about by integrated circuit innovation. He then provided an outlook of how the industry could continue to stay on the path defined by Moore’s Law by moving to nanowires and the 3rd dimension.

Luc van den hove, president and CEO of imec, tipped his hat to Gordon Moore, showing a short video clip and describing a future where Moore’s Law will live on through 3D integration.

Luc van den hove, president and CEO of imec, tipped his hat to Gordon Moore, showing a short video clip and describing a future where Moore’s Law will live on through 3D integration.

Van den hove noted what he said were obvious example of disruption today: Uber, the world’s largest taxi company that doesn’t own any taxis. Airbnb, the world’s largest accommodation provider that doesn’t own any real estate. Facebook, the world’s largest media provider, that doesn’t generate any media content.

“These are just a few examples, but we will see this kind of disruption everywhere, in every market and every segment,” he said. “Companies will have to adapt. They will have to reposition themselves in the value chain and come up with new business models. This is just the beginning.”

What’s made this disruption possible is IC technology and ubiquitous mobile computing. What’s been particularly beneficial over the last 50 years is that, in addition to the increased functionality that comes with scaling, there were advantages of faster operation at lower power. “This combination of effects that occurs simultaneously with scaling has resulted in the phenomenal evolution,” he said.
After a short video clip of Gordon Moore talking about the benefits of microprocessors, Van den hove give a realistic view of the future.

“Today, there is a lot of debate about the continuity of Moore’s Law. Yes, we’re faced with several tradeoffs. It’s getting harder and harder (to scale) and when we scale down our transistors we do not automatically the performance improvement that we used to with previous generations,” he said. “But we are sure there are sufficient solutions out there that will allow us to continue Moore’s legacy for several more decades. I am convinced that scaling will not only continue, it has to continue. If you want to enable the IoT wave, we will have to succeed in extending Moore’s law to generate the required compute power and storage capacity.”

Van den hove added that Moore’s Law is on the verge of morphing. “We will need other techniques in order to realize this complexity increase,” he said. “We will continue 2D scaling. It will evolve from the FinFET that is in mass production today towards horizontal nanowires, towards most likely vertical nanowires. This will bring us to at least the 3nm generation if not one or two generations more. This will keep us busy for the next 10-15 years.”

He stood by his past comments on the production-worth status of EUV. “To enable this, we will need a cost-effective lithography. We absolutely need EUV lithography to make this happen. I’m sure, based on the progress I’ve seen over the last 12 months, that EUV is ready to enter manufacturing. But we have to be realistic. Eventually, 2D scaling will slow down. I’m not saying it’s going to stop. But it’s getting harder and harder and hence it will require more time to transition from one geometry-based node to the next geometry node. We will need other ways to compensate for this gradual slowdown. One of the obvious ways to do so is to start using more extensively the third dimension, as the memory guys have started to do already,” he said.

Van den hove presented a future where devices are stacked on top of one another like Lego blocks. “Once we are using these vertical nanowires, it’s not so difficult to imagine that we may be stacking those transistors on top of each other – stack an n-FET on top of a p-FET and realize an SRAM cell. It’s obvious that such a 3D version of an SRAM cell has a much smaller footprint than its 2D equivalent. Once we can do that, we can even imagine that we may start stacking some of these building blocks on top of each other,” he said.

“It’s more straightforward to imagine that this can be done with a regular structure such as an SRAM design, but also FPGAs are very regular structures. We can even imagine that we could design random logic and design standard cells within the constraints of such a 3D Lego block and build up a logic circuit with these Lego blocks in a 3D fabric,” he continued.

Heterogeneous integration with photonics is also on the drawing board. “We will combine this also with 3D heterogeneous integration where we will be using chip stacking technology with high bandwidth, high density through silicon vias. We can then combine all these layers with 3D stacking and through-silicon vias, integrate all of this on an interposer, which can also be the substrate to integrate these 3D cubes,” he said. “By adding also photonics on such an interposer, we can also realize optical IOs. This is just another rendition of Moore’s Law which will allow more complexity in a smaller form factor.”

By Ed Korcynzski, Sr. Technical Editor

The near-term outlook for semiconductor manufacturing is challenging, with revenues down slightly but equipment spending up a bit, as reported by experts during the SEMI/Gartner Market Symposium held yesterday afternoon. The global economy is facing extreme uncertainty and is still recovering from the 2008/2009 financial crisis. Duncan Meldrum, Chief Economist with Hilltop Economics, explained why the after-shocks of the 2008/2009 global financial crisis combined with current political uncertainties result in a difficult investment environment. Compared to the 1993-2007 era when world real GDP was +3.2%, there are many indicators that the current ~2.3% GDP growth is the ‘new normal.’

“Rolling recessions in different regions have been pulling down global growth,” explained Meldrum. “Before the financial crisis, all the growth rates tended to be together in a coordinated global market. We’re actually seeing potential growth cut in half compared to what it was before the recession. That will create a new speed limit on the global economy, so it’ll be a tougher world than we’re used to.” These are high level macro-economic global investment numbers, but there’s a high correlation between these numbers and semiconductor industry silicon wafer processing in Millions of Square Inches (MSI).

Capital equipment forecast

Bob Johnson, Gartner research vice president, presented the outlook for semiconductor capital equipment, based on Garner’s economic model assumptions:

  • Consumer demand will remain weak,
  • High inventory of chips in all channels,
  • NAND and DRAM in oversupply for the rest of 2016,
  • Demand weakness continues longer term,
  • No new significant demand driver, and
  • Uncertain global economic climate post-Brexit.

Gartner is not bullish on the Internet-of-Things (IoT) to provide a next wave of demand. Premium smart-phones are expected to soon saturate global markets, and PC markets see weak consumer demand. In emerging markets, smartphones will take the majority of disposable income, which lowers new PC and tablet purchases by 10% through 2020.

NAND Flash is the long-term bright spot in the industry, with most of the growth driven by solid-state drives (SSD). However short-term oversupply in the second-half of 2016 is expected due to weak end markets, and increased output of planar 3bit/cell products. 3D-NAND represents 19% of the PetaBytes (PB) of total demand in 2016, increasing dramatically to 70% by 2020. SSDs are not just for PCs and mobile devices, but are moving into the enterprise segment and data centers, and 84% of SSDS will use 3D-NAND by 2020.

“3D-NAND manufacturing represents a major shift from litho-centric to etch-centric processing,” reminded Johnson. “The cost structures is still not competitive with 2D-NAND, but there will still be ~300k wafer-starts-per-month in the fourths quarter of 2016. By 2018, 3D-NAND will be half of the total NAND bits produced.” In response to 3D-NAND competition, 2D-NAND suppliers will likely do another shrink using their fully depreciated fabs, which will contribute to short-term oversupply.

Chinese foundry plans

Sam Wong, Gartner research vice president, discussed challenges of the foundry market related to China’s plans to develop domestic IC fab capability that is globally competitive. “Believe that China is really serious this time, with $140B investment,” said Wong. “The SOC capability of China is world-standard.”

For foundry markets in general, with increases in the number of mask layers with successive nodes the selling prices for finished wafers has to continue increasing. Wafer costs for fabless customers buying from foundries are now <$4K for 28nm-node, and <$7K for 14nm-node. TSMC ramped 14nm in one-half-year, and reports unprecedentedly low defects per mask layer to allow them to produce large Apple chips with high yield.

Packaging trends and china

Jim Walker, Gartner vice president of research, presented on “Semiconductor Packaging: the crucial growth component in China’s electronics supply chain.” IC manufacturing is critical to the economic growth and national security of China, and it is part of the ‘made in China 2015’ plan issued by China’s State Council.

China todays has already invested sufficient resources to now have ~1/3 of the global floor-space in Outsourced Semiconductor Assembly and Test (OSAT) facilities, while the percent of global revenue taken by Chinese companies is still much less. Since China has updated investment plans earlier this year, both South Korea and Taiwan industry organizations issued public statements of the need for strategic counter-investments. The semiconductor industry production in Taiwan represents ~13% of its total GDP, so China’s investment into this market is seen as a major threat.

By Pete Singer, Editor-in-Chief

A new roadmap, the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS), aims to integrate fast optical communication made possible with photonic devices with the digital crunching capabilities of CMOS.

The roadmap, announced publicly for the first time at The ConFab in June, is sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI and the IEEE Electron Devices Society (EDS).

Speaking at The ConFab, Bill Bottoms, chairman and CEO of 3MT Solutions, said there were four significant issues driving change in the electronics industry that in turn drove the need for the new HITRS roadmap: 1) The approaching end of Moore’s Law scaling of CMOS, 2) Migration of data, logic and applications to the Cloud, 3) The rise of the internet of things, and 4) Consumerization of data and data access.

“CMOS scaling is reaching the end of its economic viability and, for several applications, it has already arrived. At the same time, we have migration of data, logic and applications to the cloud. That’s placing enormous pressures on the capacity of the network that can’t be met with what we’re doing today, and we have the rise of the Internet of Things,” he said. The consumerization of data and data access is something that people haven’t focused on at all, he said. “If we are not successful in doing that, the rate of growth and economic viability of our industry is going to be threatened,” Bottoms said.

These four driving forces present requirements that cannot be satisfied through scaling CMOS. “We have to have lower power, lower latency, lower cost with higher performance every time we bring out a new product or it won’t be successful,” Bottoms said. “How do we do that? The only vector that’s available to us today is to bring all of the electronics much closer together and then the distance between those system nodes has to be connected with photonics so that it operates at the speed of light and doesn’t consume much power. The only way to do this is to use heterogeneous integration and to incorporate 3D complex System-in-Package (SiP) architectures.

The HITRS is focused on exactly that, including integrating single-chip and multi­chip packaging (including substrates); integrated photonics, integrated power devices, MEMS, RF and analog mixed signal, and plasmonics. “Plasmonics have the ability to confine photonic energy to a space much smaller than wavelength,” Bottoms said. More information on the HITRS can be found at: http://cpmt.ieee.org/technology/heterogeneous-integration-roadmap.html

Bottoms said much of the technology exists today at the component level, but the challenge lies in integration. He noted today’s capabilities (Figure 1) include Interconnection (flip-chip and wire bond), antenna, molding, SMT (passives, components, connectors), passives/integrated passive devices, wafer pumping/WLP, photonics layer, embedded technology, die/package stacking and mechanical assembly (laser welding, flex bending).

Building blocks for integrated photonics.

Building blocks for integrated photonics.

“We have a large number of components, all of which have been built, proven, characterized and in no case have we yet integrated them all. We’ve integrated more and more of them, and we expect to accelerate that in the next few years,” he said.

He also said that all the components exist to make very complex photonic integrated circuits, including beam splitters, microbumps, photodetectors, optical modulators, optical buses, laser sources, active wavelength locking devices, ring modulators, waveguides, WDM (wavelength division multiplexers) filters and fiber couplers. “They all exist, they all can be built with processes that are available to us in the CMOS fab, but in no place have they been integrated into a single device. Getting that done in an effective way is one of the objectives of the HITRS roadmap,” Bottoms explained.

He also pointed to the potential of new device types (Figure 2) that are coming (or already here), including carbon nanotube memory, MEMS photonic switches, spin torque devices, plasmons in CNT waveguides, GaAs nanowire lasers (grown on silicon with waveguides embedded), and plasmonic emission sources (that employ quantum dots and plasmons).

New device types are coming.

New device types are coming.

The HITRS committee will meet for a workshop at SEMICON West in July.

By Paula Doe, SEMI

With many disruptive changes occurring in the electronics supply chain, the one with the biggest impact may come from smart manufacturing and the emergence of the digital supply chain.

“The digital supply chain is the next breakthrough opportunity for the industry,” says John Kern, Cisco Systems SVP, Supply Chain, who will give the opening keynote at SEMICON West 2016 (July 12-14) at Moscone Center in San Francisco. “It’s the biggest area of investment for us now because it’s where we see the most potential.” The ability to leverage data, cloud, collaboration and mobility are making it possible to eliminate, simplify and automate processes, orchestrate activities across the supply chain in real time, and empower the workforce to focus on higher value work.

Cisco began its own journey to a digital supply chain with an update of its enterprise resource planning (ERP) system.It targeted several use cases to improve processes, such as using data to manage energy consumption within a factory to drive productivity and improve sustainability. Another was automating test processes to improve quality and reduce capital costs. But now Cisco has moved on to a broader view, of automating systems so employees don’t have to spend time gathering the information, but instead can focus on analyzing the information presented to them. “That will be the big game changer,” Kern contends.

Another example is the Cisco Supplier Collaboration Platform, which allows suppliers to see directly into their supply chain data so they can fix issues that arise, such as over or under supply directly ─ without all the usual escalations, email exchanges and delays. “There’s one single source of truth for ‘supply and demand’ that everyone can see, minimizing ‘the bull whip’ effect and enabling real-time response,” he notes.

This Supply Chain digitization is happening in concert with a disruption in business models all across the sector, as users shift from buying physical assets to buying outcomes, and paying as they receive the benefits. “The impact of the cloud and the service model is changing the way we think about supply chains,” say Kern. “We need to be able to offer any options our customers want, whether it’s hardware, software or solutions, and in any way they want to consume. Our supply chain has to adapt rapidly to enable these multiple business models.” Kern will elaborate on the topic at SEMICON West on July 12 as part of the executive events. SEMICON West also will be presenting eight business and technology forums. To register for SEMICON West 2016, visit www.semiconwest.org. For a limited time, register for only $100 (includes admission to keynotes, TechXPOTs, Silicon Innovation Forum, World of IoT Theater, 700 exhibits, and Intersolar).

Research reported in the Japanese Journal of Applied Physics by researchers at Mitsubishi Electric Corporation describes the development of a new power module made from a SiC metal-oxide-semiconductor field-effect transistor and a SiC Schottky barrier diode. The team successfully trialed the module in a train traction inverter — a device used to convert the direct current from the power source to three-phase alternating current suitable for driving the propulsion motors — with promising results.

Power electronics: Silicon carbide gains traction
Next-generation power electronics capable of reducing energy consumption are in high demand, particularly in the transportation industries. A key way of saving energy in electronics is by reducing the losses inherent in switching processes and power conversion. Much attention is now being given to a compound form of silicon and carbon called silicon carbide (SiC) for electronic components, a material whose properties outperform conventional silicon in terms of thermal conductivity, loss reduction and the ability to withstand high voltages.

Researchers in Japan have developed new power modules comprising all silicon carbide (SiC) MOSFETs (a) and SBDs (b). The power modules show great promise in improving the performance and efficiency of traction inverters for trains, reducing switching losses by 55% compared with conventional inverters.

Researchers in Japan have developed new power modules comprising all silicon carbide (SiC) MOSFETs (a) and SBDs (b). The power modules show great promise in improving the performance and efficiency of traction inverters for trains, reducing switching losses by 55% compared with conventional inverters.

Satoshi Yamakawa and co-workers at Mitsubishi Electric Corporation have developed a new power module made from a SiC metal-oxide-semiconductor field-effect transistor (MOSFET) and a SiC Schottky barrier diode (SBD). The team successfully trialed the module in a train traction inverter – a device used to convert the direct current from the power source to three-phase alternating current suitable for driving the propulsion motors — with promising results.

For a power module in a traction inverter, low power loss, miniaturization, high voltage rating, and high temperature environmental resistance are required.

Yamakawa and his team prepared the SiC MOSFET for the power module by n-type doping the junction field-effect transistor region: this reduced on-resistance of the device at high temperatures. By combining the SiC MOSFET with a SiC SBD — a diode which allows for fast and efficient switching — the team created a power module for a traction inverter rated at 3.3kV/1500A.

A new traction inverter system equipped with their power module is stable, highly efficient and reduces switching losses by 55% compared with conventional silicon-based inverters.

Reference and affiliation
Kenji Hamada1, Shiro Hino1,2, Naruhisa Miura1,2, Hiroshi Watanabe1,2, Shuhei Nakata1,2, Eisuke Suekawa3, Yuji Ebiike3, Masayuki Imaizumi3, Isao Umezaki3, and Satoshi Yamakawa1,2. 3.3kV/1500A power modules for the world’s first all-SiC traction inverter. Japanese Journal of Applied Physics  54 04DP07 (2015) http://dx.doi.org/10.7567/JJAP.54.04DP07

1. Advanced Technology R&D Center, Mitsubishi Electric Corporation, Amagasaki, Hyogo 661-8661, Japan
2. R&D Partnership for Future Power Electronics Technology (FUPET), Minato, Tokyo 105-0001, Japan
3. Power Device Works, Mitsubishi Electric Corporation, Fukuoka 819-0192, Japan

This research is featured in the September 2015 issue of the JSAP Bulletin.

When the world’s leading scientists and engineers in micro/nanoelectronics convene in Washington, D.C. this December for the 61st annual IEEE International Electron Devices Meeting (IEDM), the subjects under discussion will encompass a range of topics critical to the continuing progress of the industry:

  • how to make transistors that are vanishingly small
  • a growing emphasis on low-power devices for mobile & Internet of Things (IoT)
  • alternatives to silicon transistors
  • 3D IC technology
  • a broad range of papers that address some of the fastest-growing specialized areas in micro/nanoelectronics, including silicon photonics, physically flexible circuits and brain-inspired computing.

The 2015 IEDM will take place at the Washington D.C. Hilton Hotel from December 7-9, 2015, preceded by day-long short courses on Sunday, Dec. 6 and a program of 90-minute tutorials on Saturday, Dec. 5. In addition to a technical program of some 220 papers, other events will take place during the meeting, including evening panels, special focus sessions, IEEE awards, and an entrepreneurial luncheon sponsored by IEDM and IEEE Women in Engineering.

Back for the third year, the 2015 IEDM will feature a slate of designated focus sessions on topics of special interest. This year’s topics are:

  • Neural-Inspired Architectures: From Ultra-Low Power Devices To Applications
  • 2D Layered Materials And Applications
  • Power Devices And Their Reliability On Non-Native Substrates
  • Flexible Hybrid Electronics
  • Silicon-Based Nano-Devices For Detection Of Biomolecules And Cell Functions

“From its inaugural meeting until today, the IEDM conference has been the place where breakthroughs that drive the electronics industry forward are unveiled,” said Mariko Takayanagi, IEDM 2015 Publicity Chair and Senior Manager at Toshiba. “For example, at the IEDM in 1975 Intel’s Gordon Moore gave a talk that refined his earlier prediction of transistor scaling into what has since become known as Moore’s Law. That tradition of attracting the best speakers and a large, diverse audience from around the world continues, with a focus this year on devices intended to support the Internet of Things and other emerging areas of importance that depend upon advances in semiconductor technology.”

Samsung Electronics, a global producer of semiconductor and display solutions, formally opened the doors to its new Device Solutions America headquarters in San Jose, Calif., setting the stage for a new wave of innovation across the digital landscape.

Located on the same corner in San Jose’s tech corridor where Samsung’s original campus was first built more than 30 years ago, the new headquarters symbolizes both Samsung’s long heritage in Silicon Valley and the company’s focus on innovation and growth.

Samsung Electronics’ semiconductor operations’ has long been innovating and with the new America headquarters for its components business, Samsung’s R&D efforts will be bolstered substantially. Innovation and advanced technologies for next-generation devices generated at the new facility will help make a contribution to providing the critical competitive advantage that the company’s U.S. and global customers seek.

Speaking before an audience of more than 800 at the site’s grand opening ceremony, Oh-Hyun Kwon, Vice Chairman and CEO of Samsung Electronics, said “We are transforming Samsung into a world-class example of a truly market-focused technology company.” He further said that the company is “laying the groundwork for a more aggressive pace of growth over the next several decades.”

While Samsung Electronics’ Device Solutions Division has experienced growth since its arrival in Silicon Valley in 1983, it has created multiple organizations dispersed throughout the region. The move brings more than 700 employees together in one location, enhancing efficiency that is crucial in creating technologies and products at the cutting edge of technology. The 1.1-million-square-foot building will house various research labs dedicated to semiconductors, LEDs and displays, as well as staff in sales, marketing and other support areas.

Complete with gardens and open air space within the building, its new design increases collaboration by encouraging more spontaneous encounters between staff, while also bringing nature closer to the workplace to increase employees’ contentment and creativity.

Samsung’s President of its Device Solutions America operations, Jaesoo Han, said, “Today represents a major milestone as we open our most strategically important Samsung facility in the U.S. and also our biggest investment in Silicon Valley.” He went on to say that “Samsung’s goal is nothing less than to develop the best next-generation technologies for device solutions.”

Dignitaries in attendance at the grand opening for Samsung’s new headquarters included the current mayor of San Jose, the Honorable Sam Liccardo; former San Jose mayor, the Honorable Chuck Reed; State Senator Bob Wieckowski; San Jose State University President Susan Martin; and San Francisco Korean Consul General Dongman Han.

In keeping with the company’s corporate social responsibility (CSR) initiatives, Samsung announced a number of contributions to the Silicon Valley community. The company donated $100,000 to the Family Giving Tree and another $100,000 to the Second Harvest Food Bank.

Samsung Electronics has also established a $1 million STEM College Education Scholarship Fund to celebrate its latest expansion. Deserving university students who are currently enrolled in STEM-focused programs at a California State or University of California school will benefit from this program, beginning with a $50,000 gift to San Jose State University this year. Each scholarship will cover tuition and living expenses for one year.

The first all-optical permanent on-chip memory has been developed by scientists of Karlsruhe Institute of Technology (KIT) and the universities of Münster, Oxford, and Exeter. This is an important step on the way towards optical computers. Phase change materials that change their optical properties depending on the arrangement of the atoms allow for the storage of several bits in a single cell. The researchers present their development in the journal Nature Photonics.

Light determines the future of information and communication technology: With optical elements, computers can work more rapidly and more efficiently. Optical fibers have long since been used for the transmission of data with light. But on a computer, data are still processed and stored electronically. Electronic exchange of data between processors and the memory limits the speed of modern computers. To overcome this so-called von Neumann bottleneck, it is not sufficient to optically connect memory and processor, as the optical signals have to be converted into electric signals again. Scientists, hence, look for methods to carry out calculations and data storage in a purely optical manner.

Scientists of KIT, the University of Münster, Oxford University, and Exeter University have now developed the first all-optical, non-volatile on-chip memory. “Optical bits can be written at frequencies of up to a gigahertz. This allows for extremely quick data storage by our all-photonic memory,” Professor Wolfram Pernice explains. Pernice headed a working group of the KIT Institute of Nanotechnology (INT) and recently moved to the University of Münster. “The memory is compatible not only with conventional optical fiber data transmission, but also with latest processors,” Professor Harish Bhaskaran of Oxford University adds.

The new memory can store data for decades even when the power is removed. Its capacity to store many bits in a single cell of a billionth of a meter in size (multi-level memory) also is highly attractive. Instead of the usual information values of 0 and 1, several states can be stored in an element and even autonomous calculations can be made. This is due to so-called phase change materials, novel materials that change their optical properties depending on the arrangement of the atoms: Within shortest periods of time, they can change between crystalline (regular) and amorphous (irregular) states. For the memory, the scientists used the phase change material Ge2Sb2Te5 (GST). The change from crystalline to amorphous (storing data) and from amorphous to crystalline (erasing data) is initiated by ultrashort light pulses. For reading out the data, weak light pulses are used.

Permanent all-optical on-chip memories might considerably increase future performance of computers and reduce their energy consumption. Together with all-optical connections, they might reduce latencies. Energy-intensive conversion of optical signals into electronic signals and vice versa would no longer be required.