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By Girolamo Di Francia, ENEA & EU-PVTP expert, Italy

Introduction

The photovoltaic (PV) sector has now reached a good maturity characterized by a worldwide installed capacity of 180 GWp, increasing at a constant rate of about 35 GWp/yr during the last three years and by an annual turnover of about 45 B$, a trend that also seems confirmed for the current year. More than 85% of all the PV plants are realized by means of PV modules based on crystalline and polycrystalline silicon (cSi solar cell technology), an industrial sector dominated by Chinese companies with a 60% of the market share. In comparison, less than 20% of the photovoltaic modules are produced in the European Union (EU) and the United States (US). Vice versa EU and US are the most relevant markets for photovoltaic products with almost 70% of the installed capacity being located in those areas (EPIA 2013, Eurobarometer 2015).

On the history and the development of such a strongly unbalanced situation, several papers have been published (see for instance: de la Tour, 2011). As a matter of fact, the question is not a minor one. Photovoltaic is indeed an important product segment of the semiconductor industry, accounting, in 2014, for about a 5% of the whole 300 B$ sales of this sector and, by now, rapidly becoming comparable to other more confirmed electronic device markets, such as those related to memories or analog devices. A very intense debate is, therefore, in progress focused on the possible strategies the US and EU should undertake in order to revitalize their photovoltaic industries so that a more suitable equilibrium between China and EU/US production is set. In this respect, it seems natural to try to learn from the historical development of the electronic industry, if similar problems have occurred in that case, and if the solutions they implemented could be transferred to the photovoltaic case.

Table 1. 2014 world leading photovoltaic manufacturers

Company Country Location of production lines
Trina Solar China China
Yingli Green Energy China China
Canadian Solar Canada, China Canada, China
Jinko Solar China China
JA Solar China China
Renesola China Poland, South Africa, India, Malaysia, South Korea, Turkey, Japan
Sharp Corporation Japan Japan, US
Motech Taiwan Taiwan, China, Japan, USA
First Solar US Malaysia, US
Sun Power US US, Philippines

Indeed, a similar situation occurred in the US semiconductor industry in the late 1980s, when it had become evident that the competition with Asian electronic chips manufacturers (memories and analog devices) was going to be lost. Most of the US electronic companies decided then to shift their production from that class of chips to new products (mainly microprocessors), also through the support of national governments initiatives. This change of approach was sustained by a growing demand for the new products that, in turn, supported the creation of a local industry of production equipment specialized for those kinds of applications (Pillai 2014). Product innovation was, therefore, in that situation, the solution to cope with the asian competition, at least temporarily.

Discussion

Whether this approach can be applied to the PV industry, as well, and innovation in solar cell technology be used to revitalize the US and EU photovoltaic industries is, however, a matter of debate. Before that paradigm can be adopted, it is important to understand the extent that the photovoltaic and the electronic sectors are similar and, in this respect, a few issues need to be more deeply discussed.

1. Technological issues

Although the basic material and processing technologies are similar, the actual fabrication processes for a cSi solar cell and an electronic chip are very different, as shown in Table 2. In the case of a solar cell, a single device is obtained out of the processing of a single silicon wafer (true large area devices) while in electronics, thousands of chips are fabricated on a single substrate (high volume production). Of course, device processing resolution requirements are also very different. For a solar cell, the minimum line to be processed is, at most, in the hundreds of microns range, while for a memory chip even less than 20 nm could be required. Both resolution and number of devices to be processed per single wafer change, in turn, the basic Fabrication Yield (FY) requirements for the two devices: for a solar cell, the FY is mainly limited by wafer handling failure, with less concern with the fabrication environment.

Table 2. A comparison of the main features of a solar cell and an electronic device

Photovoltaic Electronic
Basic Fab. Proc. = =
Large Area True large area High volume
Resolution 0.1 mm 20 nm
Reliability 25 yr/80% 5 yr (Memory card)
Operating Conditions -40 °C/+80 °C -10 °C/+50 °C
Fab. Yield Limit. Handling Wafer processing

For an electronic device, particle contamination control is critical, perhaps even more than wafer handling, and highly controlled environments (clean rooms ISO 1 and ISO 2) are mandatory. But it is, perhaps, in terms of device reliability that the two classes of devices mainly differentiate. A solar cell has to continuously work for at least 25 years in an operating temperature range that can change from – 40°C up to + 80°C, and with an end life efficiency that has to not be less than 80% of its starting one. On the contrary, an electronic device, a memory card for instance, is warranted to operate for about five years and in much less stringent operating conditions (-10 °C up to + 50 °C). It is worth noting, in this respect, that for many other electronic devices (mobile phones for instance) the full functionalities are assured for not more than two years.

2. Product innovation issues

In the electronic sector, the capacity a new product has to enter the market is, first of all, connected to its innovative performance, perhaps even more than to its cost. Let us, for instance, consider again the case of memory cards, one of the most reliable devices, as stated above. As shown in Figure 1, in the last 12 years the average product has increased its performance by a factor of 1,000, increasing its capacity from an average of 128 Mb in the year 2003, to today’s 128 GB.

Figure 1. The increase in size for an average memory card and the corresponding decrease of its cost/Mb, 2003-2014.

Figure 1. The increase in size for an average memory card and the corresponding decrease of its cost/Mb, 2003-2014.

Correspondingly, a twofold decrease in the cost/Mb has been observed, although in this same period a more limited decrease in the average product cost is actually observed (McCallum 2015).

On the contrary PV solar modules have experienced in the same period a one fold decrease (from 6 $/Wp to 0.6 $/Wp) in their average cost, but the conversion efficiency, the main technological characteristic fingerprint of the innovation for this sector, has only observed a modest 30% increase (see Figure 2).

Figure 2. The increase of the average cSi solar module conversion efficiency and the decrease of the cost/Wp, 2003-2014.

Figure 2. The increase of the average cSi solar module conversion efficiency and the decrease of the cost/Wp, 2003-2014.

Innovation, therefore, does not seem to have played a key role in the development of the photovoltaic sector and, effectively, it has been reported that the major role in PV cost reduction is due to economies of scale (ISE 2013, Goodrich 2012).

Conclusions

Sic reris stantibus, it is questionable to what extent innovation in the PV sector can effectively support the further diffusion of this form of energy and help the EU and US industries cope with the Chinese competition. Recently, for instance, it has been observed that while a certain level of product innovation can be necessary, excessive innovative technological scenarios could even be detrimental (Goodrich 2012) with respect to a more capillar photovoltaic diffusion.

The point that is important to keep in mind is that the end user of a PV module is an energy producer, and since the fuel (the solar radiation) is available at no cost, once the system used for the conversion is such that the cost of the electricity produced becomes competitive with that of other energy sources, as it is now effectively observed in several countries, the only other issue to be considered is the long-term system reliability. As the solar modules actually on the market have shown in the last 40 years, to fully comply with this requirement, it is difficult to conceive an innovative product capable of revitalizing the US or EU photovoltaic industries that is, at the same time, truly different from that classical, very sound, product. Finally, it is worth noting that it has also been demonstrated that there is no practical economical advantage in setting up a PV industry in China with respect to any other US or EU region (Goodrich 2013). This suggests that revitalizing the US or EU industries could be more a question of further supporting the diffusion of photovoltaic energy than of pushing too hard on the innovative character of the PV productions. In this respect, it is perhaps more urgent to find innovative financial schemes, sustainable from the point of view of public spending, and also capable of supporting the expansion of a sector that has become relevant for EU and US industrial and environmental policies, than to pay too much attention to the innovative characteristics of a product that seems, at present, to fully satisfy most market expectations.

References

de la Tour A., Glachant M., and Ménière Y. 2011. Innovation and international technology transfer: The case of the Chinese photovoltaic industry, Energy Policy 39 (2): 761-770.

EPIA Global market outlook for photovoltaics 2013-2017. Available at: http://www.epia.org/fileadmin/user_upload/Publications/GMO_2013_-_Final_PDF.pdf

Eurobarometer 2015. Barometre photovoltaique Eurobserver Avril 2015. Available at : http://eurobserv-er.info/photovoltaic-barometer-2015/

Goodrich A., Hacke P., Wang Q., Sopori B., Margolis R., James T.L., and Woodhouse M. , (2012) A wafer-based monocrystalline silicon photovoltaics road map: Utilizing known technology improvement opportunities for further reductions in manufacturing costs. Solar Energy Materials & Solar Cells 114: 110–135

Goodrich A., Powell D. M., James T. L., Woodhouse M. and Buonassisi T., (2013) Assessing the drivers of regional trends in solar photovoltaic manufacturing. Energy Environ. Sci., 6 : 2811-2821

ISE-Photovoltaic Report, Photovoltaic Report 2014, Ise Fraunhofer, 2014.

McCallum J.C. 2015 Flash Memory Prices (2003-2014). http://www.jcmit.com/index.htm (last accessed june 2015)

Pillai U., Querques N., and Haldar P. 2014 The U.S. Photovoltaic Manufacturing Consortium: Lessons from the Semiconductor Industry. InterPV.net – Global PhotoVoltaic Business Magazine. Available at: http://www.interpv.net/market/market_print.asp?idx=666&part_code=03

 

 

London, UK and San Jose, California – Dialog Semiconductor and Atmel Corporation announced today that Dialog has agreed to acquire Atmel in a cash and stock transaction for total consideration of approximately $4.6 billion. The acquisition creates a global leader in both Power Management (defined as power management solutions for mobile platforms including smartphones, tablets, portable PCs and wearable-type devices) and Embedded Processing solutions. The transaction results in a company that supports Mobile Power, IoT and Automotive customers. The combined company will address a market opportunity of approximately $20 billion by 2019.

Dialog will complement its position in Power Management ICs with a portfolio of proprietary and ARM (R) based Microcontrollers in addition to high performance ICs for Connectivity, Touch and Security. Dialog will also leverage Atmel’s established sales channels to diversify its customer base. Through realized synergies, the combination could deliver an improved operating model and enable new revenue growth opportunities.

“The rationale for the transaction we are proposing today is clear – and the potential this combination holds is exciting. By bringing together our technologies, world-class talent and broad distribution channels we will create a new, powerful force in the semiconductor space. Our new, enlarged company will be a diversified, high-growth market leader in Mobile Power, IoT and Automotive. We firmly believe that by combining Power Management, Microcontrollers, Connectivity and Security technologies, we will create a strong platform for innovation and growth in the large and attractive market segments we serve. This is an important and proud milestone in the evolution of our Dialog story,” said Jalal Bagherli, Dialog Chief Executive Officer.

“This transaction combines two successful companies and will create significant value for Atmel and Dialog shareholders, customers and employees. Adding Dialog’s world-class capabilities in Power Management with Atmel’s keen focus on Microcontrollers, Connectivity and Security will enable Dialog to more effectively target high-growth applications within the Mobile, IoT and Automotive markets,” said Steven Laub, Atmel President and Chief Executive Officer.

The transaction is expected to close in the first quarter of the 2016 calendar year. In 2017, the first full year following closing, the transaction is expected to be accretive to Dialog’s underlying earnings. Dialog anticipates achieving projected annual cost savings of $150 million within two years. The purchase price implies a total equity value for Atmel of approximately $4.6 billion and a total enterprise value of approximately $4.4 billion after deduction of Atmel’s net cash. Dialog expects to continue to have a strong cash flow generation profile and have the ability to substantially pay down the transaction debt approximately three years after closing.

The transaction has been unanimously approved by the boards of directors of both companies and is subject to regulatory approvals in various jurisdictions and customary closing conditions, as well as the approval of Dialog and Atmel shareholders. Jalal Bagherli will continue to be the Chief Executive Officer and Executive Board Director of Dialog. Two members of Atmel’s existing Board will join Dialog’s Board following closing. The transaction is not subject to a financing condition.

By Zvi Or-Bach, Contributor

The upcoming IEEE S3S Conference 2015 in Sonoma, CA, on October 5-8, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those that drive the high-volume PC and smart-phone market. The Gartner slide below illustrates this industry bifurcation where traditional mass products follow the ever more expensive scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek a place near its minimum.

S3S_Gartner

The current high-volume market is focused on a few foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs and a broad range of process options, and has many more players both at the foundry side and the design side.

The key enabling technologies for the IoT market are extremely low power as enabled by SOI and sub-threshold design, integrated with multiple sensor and communication technologies that are both enabled by 3D integration. All of these combine in forming the IEEE S3S unified conference.

This year’s conference includes many exciting papers and invited talks. It starts with three plenary talks:

  • Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  • Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  • Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration

The following forecast from BI Intelligence suggest that the semiconductor technologies that are a good fit for the future market of IoT should be of prime interest for the semiconductors professional.

S3S_BI

Jim Walker, Research VP at Gartner, argued at the “Foundry vs. SATS: The Battle for 3D Wafer Level Supremacy” market symposium that 3D ICs are the key enabler of performance and small form factor of products required for IoT.

The upcoming IEEE S3S conference provides an important opportunity to catch up and learn about these technologies.

Let me share with you some nuggets from the monolithic 3D integration part of the conference:

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” which will present a process technology to fabricate flexible devices 6-20 microns thin. This process flow is currently in manufacturing in their Stuttgart fab, as depicted below:

S3S_Fig3

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor”. These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

In his invited talk “Emerging 3DVLSI: Opportunities and Challenges” Dr. Yang Du will share  Qualcomm’s views on monolithic 3D IC, which they term 3DVLSI and illustrate below, which seems very fitting for IoT applications.

S3S_Fig2

Globalfoundries will present joint work with Georgia Tech on “Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”. This work again shows that monolithic 3D can provide a compelling alternative to dimensional scaling as illustrated by the following chart.

S3S_Fig4

Monolithic 3D will present “Modified ELTRAN (R) – A Game Changer for Monolithic 3D” that shows a practical flow for existing fabs to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. The following slide illustrates the original ELTRAN flow.

S3S_Final

By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short courses on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future.

Thursday, July 16, 2015

10:00 am – 12:30 pm
STS MORNING SESSION:
A Path to Future Interconnects
Moscone North, Hall E, Room 133

11:00 am – 3:00 pm
CMP Technical and Market Trends
TechXPOT North, Moscone North Hall
Session Partner: NCCAVS CMP User Group

12:00 pm – 4:00 pm
UNIVERSITY DAY
Career Expo
Esplanade, Room 300

1:00 pm – 3:00 pm
The Factory of the (Near) Future: Disruptive Technologies from IoT to 3D Printing Impact the Semiconductor Manufacturing Sector
TechXPOT South, Moscone South Hall
Session Sponsor: Air Liquide

1:20 pm – 4:45 pm
STS AFTERNOON SESSION:
Flexible Hybrid Electronics for Wearable Applications – Challenges and Solutions
Moscone North, Hall E, Room 132

The ClassOne Technology Solstice S4 won the Best of West award, presented by Solid State Technology and SEMI. The award was presented to Byron Exarcos, president of ClassOne, at the company’s booth in the North Hall on Wednesday afternoon.

Byron Exarcos, president of ClassOne Technology; Karen Salava, president of SEMI Americas; and Pete Singer, Editor-in-Chief of Solid State Technolgy

Byron Exarcos, president of ClassOne Technology; Karen Salava, president of SEMI Americas; and Pete Singer, Editor-in-Chief of Solid State Technolgy

Solstice S4 is the first automated plating tool that delivers advanced performance on smaller substrates at affordable prices. Described as “advanced plating for the rest of us,” Solstice is designed specifically for the smaller-substrate users in emerging technologies such as MEMs, LEDs, Power Devices, RF Communications, Interposers, Photonics and Microfluidics. Solstice sets new standards for plating performance and affordability.

“There’s a convergence of forces for the different trends that we all see in the market, and right now, it’s the internet of things, it’s the More than Moore, and it’s the flexibility of the manufacturers to achieve all these things,” said Kevin Witt, chief technology officer at ClassOne Technology, after the award presention. “We’ve felt that we had a product that reflected a lot of what those requirements were.”

Witt said there’s a lot of work being done at the cutting edge of 300mm, as well it should. “But there’s an equally important 200mm and below surge. Those folks need equipment. What they can buy now is from the ‘90s,” he said.

Until now, with the Solstice. “The people that are building the 200mm and below fabs need the modern capability of wafer level packaging and interfacing for chip stacking. They need something that fits their budget profile, that is not a 300mm tool that has been repurposed for 200mm,” he said.

Witt concluded: “We went for best of show in the hopes that the world would see that there are companies that are focused on meeting the needs of the smaller level producers that are the next growth area.”

Designed for high-performance, cost-efficient ≤200mm electroplating, Solstice systems are priced at less than half of what similarly configured plating tools from the larger manufacturers would cost — which is why Solstice has been described as delivering “Advanced Plating for the Rest of Us.” Solstice can electroplate many different metals and alloys in a spectrum of processes, on transparent or opaque substrates. ClassOne now offers three Solstice models: the LT for plating process development, the S4 for mid-volume production, and the S8 for high-volume, cassette-to-cassette production, with throughput of up to 75 wph.

Earlier this week, at SEMICON West, ClassOne Technology announced a configuration for optimizing Through Silicon Via (TSV) and Through Wafer Via (TWV) processes on its Solstice® electroplating systems. The Solstice family, introduced last year, is designed to provide advanced yet cost-efficient plating for MEMS, Sensors, RF, Interposers and other emerging technologies for ≤200mm wafers. Flexibly configurable, the Solstice for TSV/TWV combines chambers for the critical blind via pre-wet operation with advanced copper plating on the robust and reliable automation frame that is the heart of the Solstice.

“In recent months customer requests for TWV, whether alone or in combination with forming redistribution layers (RDL), have skyrocketed,” said Witt. “Many of our smaller-wafer customers seek the advantages of 2.5 and 3D packaging needed for their next generation products; and cost-effective TSV or TWV processing is mission critical. The new Solstice configuration addresses their needs effectively and elegantly with a plating tool that is affordably priced for 200mm and smaller substrates.”

Witt explained that the new Solstice TSV configuration, which has already been sold to customers, employs a unique, high-efficiency but simple vacuum pre-wet chamber followed by copper via electroplating. This combination of capabilities enables the ClassOne tool to routinely produce fully-filled or lined vias with widths ranging from 5 to 250 micron having aspect ratios as high as 9:1. Traditionally, this level of performance has been challenging even for plating systems costing twice as much as Solstice. The Solstice can also be configured to perform additional downstream processing such as resist strip and seed layer etch making it a cluster tool that delivers a suite of critical processes, reducing cycle time and saving money. This technology makes it possible to process TSV alone or TSV and redistribution layers simultaneously to provide a complete solution on a single tool.

By Shannon Davis, Web Editor

Fifty years of technological developments following Moore’s Law has changed our world in some phenomenal ways, but Intel’s Doug Davis believes the time has come to change the way we think about developing new solutions.

At SEMICON West 2015 on Wednesday morning, Intel’s Internet of Things Senior Vice President and General Manager challenged attendees to broaden their thinking on the potential of the IoT and examine their own roles in bringing about global change through new, innovative technology.

“The question is not how do we make these devices smart? The question becomes what are the problems that we can work together to solve?” Davis said.

Davis’ presentation addressed four complex issues the world is currently facing: an aging population, climate change, the urban boom, and how we feed the planet, offering real IoT solutions that could impact these growing concerns.

IoT and an aging population

Since 1950, the average lifespan has increase by more than 20 years. By the year 2050, more people on the planet will be over the age of 60 than under the age of 14.

“As we’re all living healthier, longer lives, we also have to reflect that as a society we’re unprepared to provide care for these kinds of numbers,” said Davis.

Even if the infrastructure were available, if you talk to seniors, they’d rather live out their lives at home, Davis pointed out. How can the IoT help us with this challenge? Davis offered up MimoCare as an example pioneering technology that addresses this.

MimoCare is an IoT technology currently available that uses analytics to provide the caregiver with a unique monitoring solution. Using a network of motion, door, and presence sensors, MimoCare will unobtrusively provide data on what is normal in the home and what changes are occurring, which allows the caregiver to make decisions if they are concerned. The result: seniors are enabled to live in the comfort of their own homes longer.

IoT and climate change

No matter where you stand on global warming, there’s no arguing that air quality is becoming a serious issue in an increasing number of cities in the world, Davis said.

He challenged his audience to also think about this problem differently, posing the question, “What if we reduced emissions at every point in the supply chain?”

Davis cited Intel’s own predictive analytics solutions, which have been used in a number of their fabs around the world.

“Engineers at one Intel fab have used this data to reduce maintenance time by 50%, parts replacement by 20%,” Davis said. “They were able to reduce non-genuine yield loss by as much as 20%.”

With this kind of increase in efficiencies, Davis said Intel believes this also helps to reduce their carbon footprint.

IoT and the urban boom

“We’re undergoing the fastest rural to urban migration in human history,” Davis explained. “City populations are growing by 65 million people per year – that’s seven new Chicagos every year.”

And there are a lot of growing concerns that go along with this boom, from traffic problems to pollution. To address these issues, Davis said Intel has pilot programs now in the UK that are beginning to capture data on traffic patterns, air quality, water supply and more, and overlaying that data with public service agencies, which would allow these agencies and eventually citizens to make real-time decisions and changes.

IoT and how we feed the planet

Davis argued that the real problem the world is facing isn’t how to feed the planet, but the amount of food wasted while so many people go hungry.

“The World Bank says that we’re currently wasting 1/4 to 1/3 of the food that’s being produced on the planet today,” said Davis. “We have to get better at distributing food.”

Davis shared one example of improved agricultural performance through IoT solutions installed in rice fields in Malaysia, where farmers used ground water and weather forecasting analytics to monitor and make decisions about crop management. In the end, Davis said, farmers were able to see water savings of up to 10% and rice production increase of 50%.

What’s possible in the next five years?

It’s hard to imagine what the world will look like after another 50 years of technological developments, so Davis concluded his presentation with market research that demonstrates the dramatic impact these Internet of Things systems can have in just five years.

According to recent studies by Juniper, he reported, the world’s healthcare systems could save $36B by implementing remote patient monitoring technologies. Predicted maintenance could have as much as 1,000 times return on investment, when we think about the total impact those solutions could deliver. Smart city traffic management could reduce cumulative global emissions by 164 million metric tons, the equivalent to taking 35 million cars off the road. Improved data collection, weather forecasting, and precision agriculture could decrease agricultural losses by as much as 25% percent.

“The genius of Moore’s Law showed us what was possible and set the pace for us,” Davis said. “Over the next 50 years, think about what’s possible – think beyond just the device and into the end-to-end solutions we can create, and we can tackle these huge challenges worldwide.”

Wednesday, July 15, 2015

9:00 am – 10:00 am
KEYNOTE: The Internet of Things and the Next Fifty Years of Moore’s Law
Speaker: Doug Davis, Senior Vice President, General Manager, Internet of Things Group, Intel
Moscone North, Hall E, Room 135

10:30 am – 12:30 pm
Subsystem and Component Suppliers at Critical Crossroads to Deliver on Yield and Productivity
TechXPOT South, South Hall
Session Sponsor: Advanced Energy

1:30 pm – 3:30 pm
Packaging: Auto Utopia: Gearing up Semiconductor to Turn Dreams to Reality
TechXPOT North, North Hall
Session Partner: Meptec

2:00 pm – 4:30 pm
STS SESSION:
Scaling Transistors: HVM Solutions Below 14nm; Getting to 5nm
Moscone North, Hall E, Room 133
Session Sponsor: Lam Research

3:30 pm – 4:30 pm
SILICON INNOVATION FORUM:
INNOVATE Keynote
Speaker: Stephen Forrest, Ph.D., Professor, Dept. of Engineering, University of Michigan
Moscone North, Hall E, Room 135

4:30 pm – 6:00 pm
SILICON INNOVATION RECEPTION
Innovation Village

By Jeff Dorsch, Contributing Editor

When Gordon Moore of Fairchild Semiconductor published his famous article on chip scaling and costs in 1965, gasoline in the U.S. was 31 cents per gallon, the Dow Jones Industrial Average was under 1,000, and a house could be purchased for $13,000 or so, noted Denny McGuirk, president and CEO of SEMI, at Tuesday morning’s press conference opening the SEMICON West 2015 conference and exhibition.

It’s the 45th anniversary of SEMI itself and the annual SEMICON show in Northern California during 2015, he added.

Karen Savala, president of SEMI Americas, reviewed SEMICON West events for this week and new aspects of the show, such as the Career Exploration Forum.

Dan Tracy, SEMI’s senior director of industry research and statistics, presented the market forecast for semiconductor equipment and materials. Foundry and memory chip manufacturers will primarily drive this year’s growth for wafer fabrication equipment, he said.

SEMI is forecasting capital equipment revenue will reach about $40 billion worldwide this year, with 8 percent growth for all equipment and 10 percent growth for wafer fab equipment.

SEMI Press Conference Highlights Market Forecast, Economic Conditions Figure 1

The global materials market is predicted to increase 4 percent in revenue this year, according to Tracy, to $46 billion for all packaging and semiconductor materials.

The SEMI executive focused on fan-out wafer-level packaging, which will increase dramatically over the next four years, according to TechSearch International. WLFO is primarily meant for mobile applications, “driven by consumer demand,” Tracy noted. Such consumer products will bring “a lot of pricing pressure,” he added.

Tracy also highlighted the currency situation presented by a strong dollar, which is having adverse effects on the euro and the yen. The Semiconductor Equipment Association of Japan estimates 2014 billings grew by 37 percent when measured in yen, and only 26 percent measured in U.S. dollars.

SEMI Press Conference Highlights Market Forecast, Economic Conditions Figure 2

By Pete Singer, Editor-in-Chief

SEMICON West 2015 kicked off Tuesday morning with a keynote panel session that addressed the challenges of “Scaling the Walls of Sub-14nm Manufacturing.” The general consensus was that future progress is dependent on better coordination and collaboration between design, manufacturing and packaging companies and people.

The panel consisted of Jo de Boeck, Senior Vice President, Corporate Technology at imec, who acted as the moderator; Gary Patton, Chief Technology Officer and Head of Worldwide Research and Development at GLOBALFOUNDRIES; Michael Campbell, Senior VP Engineering at Qualcomm; Calvin Cheung, Vice President, Business Development and Engineering at ASE and Subhasish Mitra, Associate Professor, Dept. of EE and CD at Stanford University.

Tuesday panel

Patton said the end of scaling was nowhere in sight. “People have talked about the end of scaling. Scaling is not going to end. I am not worried about solving the physics challenges,” he said. “We have run into many barriers over the years and we always find a way to get around it.

Patton said what worries him is doing it in a way “that can deliver to our customers a real value proposition for going to that next technology node. The cost of doing design in these nodes is increasing at a pretty rapid rate and we have to provide them with a return on investment. It’s becoming more challenging,” he said.

He noted that in the past most breakthroughs, such as high-k metal gates, took over 10 years in the research stage before they were ready for manufacturing. That was one reason behind the merger between IBM and GLOBALFOUNDRIES: access to 16,000 some IBM patents. Patton also mentioned IBM’s expertise in a ASICs business, differentiated IP, RF technology – both silicon germanium as well as RFSOI – as well as 3D and 2.5D technologies.

Qualcomm’s Mike Campbell said the biggest threat to Moore’s Law is yield. “Yield is now an end-to-end question,” he said. “That doesn’t just mean semiconductor yield today. It’s the package yield on top of that and then the systems yield.”

Campbell said he’d like to see that end-to-end yield contained in a productivity model. “If you have a 10nm or 7nm silicon piece and it works to the spec at the silicon level, but then we change the stress characteristics because we have to saw and dice it up into a package. Then we put it into a 2.5D or 3D package and change the stress levels again. The yields change at every level,” he said.

Campbell believes that the whole system has to be interactive. “Until 28nm, you didn’t need to have that interactivity. But as we go deeper and deeper into submicron technology, the interactivity between the package, the system and the silicon itself—and the basic R&D for the silicon – all have to start to play together or else at the end we’ll end up with gaps in the system which will then add cost to the deliverables that we have to bring to the marketplace,” he said.

ASE’s Calvin Cheung said the company’s biggest concern was CPI (chip package interaction). “We are really pushing assembly and test technology capabilities,” he said. “In the case of 2.5D, we have connect a couple hundred thousand interconnects and put them on a very, very small space. With the scaling, the die is getting smaller but your I/O density continues to increase.”

By Pete Singer, Editor-in-Chief

The expansion of fan-out is finally coming, says Rich Rogoff, Vice President and General Manager, Lithography Systems Group at Rudolph Technologies.

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.

It was originally introduced by Infineon in the fall of 2007. Called eWLB, or embedded wafer-level ball grid array technology, it enables all operations to be performed highly parallel at wafer level. In August of 2008, STMicroelectronics, STATS ChipPAC, and Infineon signed an agreement to jointly develop the next-generation eWLB, based on Infineon’s first-generation technology.

Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

STATS ChipPAC’s eWLB high volume manufacturing process, for example, today includes automated wafer reconstitution (including wafer-level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 200mm and 300mm diameters can be supported.

According to a recent report from Yole Développement, the fan-out WLP (FOWLP) market will reach almost $200M in 2015, with 30% CAGR in the coming years. Yole analysts say FOWLP started volume commercialization in 2009/2010 and started promisingly, with an initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. In 2012 big fabless wireless/mobile players started slowly volume production after qualifying the technology.

It faced strong competition from other packaging technologies, such as wafer-level chip scale packaging (WLCSP) in 2013/2014. Intel Mobile also backed off from the technology, and the main manufacturers reduced their prices in 2014, creating a transition phase with low market growth.

Strong growth is now expected, hoped in part by the arrival of 2nd generation FOWLP. “Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size”, explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement.

Rudolph’s Rogoff believes it will be implemented in a wafer form for the next year or two, but will ultimately transition to a panel-based approach. “The big question for the industry is are they going to move to panels?” Rogoff asked. “From a lithography perspective, the tools are ready today. As the demand goes up, there will be a push also for a switch,” he said. “Development of panels has already started and will continue to increase in activity over the next year.”

In an article in Solid State Technology published in 2014, titled “A square peg in a round hole: The economics of panel-based lithography for advanced packaging,” Rogoff said moving from round wafers to rectangular panels (“panel-ization”) saves corner space, delivering a roughly 10% improvement in surface utilization. The larger size of the substrate and the improved fit between the mask and substrate reduce the transfer overhead by a factor of 5. The potential reduction in throughput resulting from an increase in the number of alignment points is more than offset by the improvements in throughput. Compared to a 1X stepper on wafers, panel-based processes can reduce lithography cost per die by as much as 40%.

One of the advantage of Rudolph Technologies’ JetStep Panel System (JetStep S3500) is that it can handle such rectangular panels. Both the panel and wafer 2X reduction steppers offer many advantages — based in part on Azores’ 6700 platform which was developed for LCDs — including the largest printable field-of-view, programmable aperture blades and large on-tool reticle library, large depth-of-focus along with autofocus to accommodate 3D structures in advanced packaging, very large working distance, and warped substrate handling (+/- 6mm). The wafer system (JetStep W2300) features programmable wafer edge protection, enabling a variable edge exclusion zone of 0.5-5 mm. The systems also feature a large (17mm) working distance between the lens and the substrate, which helps avoid a common maintenance issue on 1X systems.

Rogoff said the ability to handle warped wafers is increasingly important. “We’ll always be putting the best focus point in the middle of our depth of focus range. If there’s any variation due to substrate warp, we can go up a little and down a little and we’re still going to be in focus,” he said.

The large working distance helps eliminate problems with thick resists, which can outgas and potentially contaminate the lens. “We’re so far away — and we also have some purging in the area – we don’t have that issue. The less you have to take the machine down to clean it, the better,” he said.

When it comes to fan-out, the challenge is being able to manage the overlay performance over a large field area. “Our competitors like to say it can’t be done, yet we prove it can,” Rogoff said. “The larger the field is, the more die you get in it, so the more variations you’re likely to see. With our ability to correct for intrafield parameters, we can extract out that variation so what’s left is just random noise.”

If the random noise gets too high, another solution Rudolph can provide is a combination of stepper modeling capability with inspection. “You can measure the die placement on a high speed inspection tool, throw that data into the modeling software and spit out the stepping model for the stepper,” Rogoff explained. “This is something we’re continuing to develop. The first round is available and as the fan-out technology gets more complex, we’re continuing to expand on that.”