Tag Archives: letter-wafer-tech

Band gaps, made to order


September 28, 2017

Control is a constant challenge for materials scientists, who are always seeking the perfect material — and the perfect way of treating it — to induce exactly the right electronic or optical activity required for a given application.

One key challenge to modulating activity in a semiconductor is controlling its band gap. When a material is excited with energy, say, a light pulse, the wider its band gap, the shorter the wavelength of the light it emits. The narrower the band gap, the longer the wavelength.

As electronics and the devices that incorporate them — smartphones, laptops and the like — have become smaller and smaller, the semiconductor transistors that power them have shrunk to the point of being not much larger than an atom. They can’t get much smaller. To overcome this limitation, researchers are seeking ways to harness the unique characteristics of nanoscale atomic cluster arrays — known as quantum dot superlattices — for building next generation electronics such as large-scale quantum information systems. In the quantum realm, precision is even more important.

New research conducted by UC Santa Barbara’s Department of Electrical and Computer Engineering reveals a major advance in precision superlattices materials. The findings by Professor Kaustav Banerjee, his Ph.D. students Xuejun Xie, Jiahao Kang and Wei Cao, postdoctoral fellow Jae Hwan Chu and collaborators at Rice University appear in the journal Nature Scientific Reports.

Their team’s research uses a focused electron beam to fabricate a large-scale quantum dot superlattice on which each quantum dot has a specific pre-determined size positioned at a precise location on an atomically thin sheet of two-dimensional (2-D) semiconductor molybdenum disulphide (MoS2). When the focused electron beam interacts with the MoS2 monolayer, it turns that area — which is on the order of a nanometer in diameter — from semiconducting to metallic. The quantum dots can be placed less than four nanometers apart, so that they become an artificial crystal — essentially a new 2-D material where the band gap can be specified to order, from 1.8 to 1.4 electron volts (eV).

This is the first time that scientists have created a large-area 2-D superlattice — nanoscale atomic clusters in an ordered grid — on an atomically thin material on which both the size and location of quantum dots are precisely controlled. The process not only creates several quantum dots, but can also be applied directly to large-scale fabrication of 2-D quantum dot superlattices. “We can, therefore, change the overall properties of the 2-D crystal,” Banerjee said.

Each quantum dot acts as a quantum well, where electron-hole activity occurs, and all of the dots in the grid are close enough to each other to ensure interactions. The researchers can vary the spacing and size of the dots to vary the band gap, which determines the wavelength of light it emits.

“Using this technique, we can engineer the band gap to match the application,” Banerjee said. Quantum dot superlattices have been widely investigated for creating materials with tunable band gaps but all were made using “bottom-up” methods in which atoms naturally and spontaneously combine to form a macro-object. But those methods make it inherently difficult to design the lattice structure as desired and, thus, to achieve optimal performance.

As an example, depending on conditions, combining carbon atoms yields only two results in the bulk (or 3-D) form: graphite or diamond. These cannot be ‘tuned’ and so cannot make anything in between. But when atoms can be precisely positioned, the material can be designed with desired characteristics.

“Our approach overcomes the problems of randomness and proximity, enabling control of the band gap and all the other characteristics you might want the material to have — with a high level of precision,” Xie said. “This is a new way to make materials, and it will have many uses, particularly in quantum computing and communication applications. The dots on the superlattice are so close to each other that the electrons are coupled, an important requirement for quantum computing.”

The quantum dot is theoretically an artificial “atom.” The developed technique makes such design and “tuning” possible by enabling top-down control of the size and the position of the artificial atoms at large scale.

To demonstrate the level of control achieved, the authors produced an image of “UCSB” spelled out in a grid of quantum dots. By using different doses from the electron beam, they were able to cause different areas of the university’s initials to light up at different wavelengths.

“When you change the dose of the electron beam, you can change the size of the quantum dot in the local region, and once you do that, you can control the band gap of the 2-D material,” Banerjee explained. “If you say you want a band gap of 1.6 eV, I can give it to you. If you want 1.5 eV, I can do that, too, starting with the same material.”

This demonstration of tunable direct band gap could usher a new generation of light-emitting devices for photonics applications.

Making a magnet from a piece of iron and a coil or wire, or another magnet, is a simple experiment. An external electric or magnetic field can align groups of atoms in the iron over time so that they take on their own permanent magnetic field. A similar accelerated process stores information on computer hard disks. A special case of magnetism, known as ferrimagnetism, could enable even faster switching of magnetism, leading to massive improvements in the way computers handle information.

Now, an international research group, led by Osaka University physicists, has provided new insight into how the composition of ferrimagnetic materials can affect their interactions with light. They recently reported their findings in Applied Physics Express.

“We know that laser pulses can reverse the magnetization in certain ferrimagnetic alloys, but light also affects other properties of the material,” coauthor Hidenori Fujiwara says. “To learn more about the interactions of the magnetism with light, we studied the spin dynamics of ferrimagnetic thin films containing different proportions of gadolinium.”

Ferrimagnetic materials can be thought of as a mixture of electrons spinning at different sites in the material. Some of the spins might cancel each other out, but a certain residual magnetization will remain. Firing an ultra-fast laser pulse at the material may completely flip the spin direction, reversing the magnetism, or may disrupt the spins, causing a kind of wobbling known as spin precession. The type of behavior shown strongly depends on the material’s temperature and composition.

The researchers used an advanced synchrotron measurement setup developed in their previous studies to show that slightly varying the composition of an alloy dramatically changed its response to the laser pulse. Slightly more gadolinium in the films led to flipping of the magnetic spin; slightly less led to spin precession at room temperature.

The researchers’ setup could also visualize the wave-like nature of the spin precession over a few nanoseconds following the laser pulse. They showed that the angle of precision, or the angle of the spin wobble, was the largest reported to date.

“These are complex systems with many different interacting properties, but we have extracted some clear relationships between the composition of a ferrimagnetic alloy and its magnetic interactions with light,” coauthor Akira Sekiyama says. “Understanding these behaviors is important from a fundamental physics standpoint, and essential for applying these material systems in advanced electronic devices.”

Understanding the impact of valve flow coefficient (Cv) in fluid systems for microelectronics manufacturing

BY STEPHANE DOMY, Saint-Gobain Performance Plastics,

When scaling up, or down, a high-purity liquid installation – many complex factors need to be considered from ensuring the integrity of the transported product to the cleanliness of the environment for both the safety of the process and the operator [1]. In my 15 years working in the semiconductor fluid handling component industry, I’ve learned that the Cv is a bit misunderstood. Given the Cv formula can be used for any flow component in a fluid line, most are familiar with it, yet few consider how it relates to their specific installation. Therefore, this article will focus on factors that pertain to achieving a specific flow performance and specifically the flow coefficient (Cv) as it relates to valves.

Cv empirical explanation and more

As we know, when working on a turbulent flow the Cv formula is: Cv= Q√(SG / ∆P) where Q is the flow going through the valve in gallons per minute (GPM), SG is the specific gravity of the fluid and ∆P is the pressure drop in PSI through the component. In the semiconductor industry, due to the low velocity of the transported fluid the high purity chemistry and slurries are mostly in a semi–turbulent state or a laminar state. Yet you’ll notice there is not a single link to the viscosity of the transported product in the Cv formula. This is significant given the viscosity directly impacts the Cv value when the flow is in a semi-turbulent or laminar mode. Consider that if you calculate the pressure drop in your system with the formula above you could end up with a result that is 4 to 5 times lower. No doubt this inaccuracy can cause significant issues in your installation.

To take this further, let’s analyze how pressure drop based on flow evolves through a valve by comparing a Saint-Gobain Furon® Q-Valve (1⁄2” inner flow path and 1⁄2” pipe connection) to a standard semiconductor industry valve of the same size. The Saint-Gobain valve, which meets the requirements of the semiconductor industry (metal free, 100% fluoropolymer flow path and so on), has a Cv of 3.5 – one of the best for its dimensions. To ease the calculation, we will use deionized (DI) water, which will free us of the specific gravity or impact of the viscosity if we are not in the right state.

As we can see on the graph in FIGURE 1, at a normal flow rate used in micro-e for 1⁄2” 5 to 10 lpm; the pressure drop difference between a standard valve and a Saint-Gobain valve is in the range of 0.1 to 0.3 PSI. At first glance, this does not appear to be much. However, let’s factor in a viscous product and that you have a number of these lines in your flow line — now the numbers start to accumulate. And by moving from a standard valve to a Saint-Gobain valve, as described above, you start to see a significant difference in pressure drop, which could occur across your installation. That being said, up to a certain limit (defined by another component in your installation, such as your pump pressure capability or some more delicate device) an “easy” counter is to increase the pressure through put of your pump but it is at the expense of wasting energy and adding the potential for additional shearing or particle generation in your critical fluid. Now that we have reviewed, the impact of the Cv on our flow and how this could impact our installation, let’s see what can potentially impact the Cv.

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Design impact on Cv and resulting trade-off

The first impact that may come to mind is a larger orifice – and it’s correct. The size of the orifice can benefit flow through and directly relates to the volume of your valve. However there are trade-offs for this improved Cv. The first is cost increase. A higher volume requires a larger valve, which can cost up to 50% more than the initial valve due to specific material and process requirements. Additionally, as highlighted in “Design Impact for Fluid Components” by increasing the size of the component (due to the specific micro-e material requirements), you could lose pressure rating performance [1]. Also when increasing the inner volume of your valve, you potentially increase volume retention as well as particle generation, given that using larger actuation systems results in more points of contact and creates a hub for generating particles. Another possible drawback is significant velocity loss, but that will have to be addressed in another article. The critical point to be taken here is the importance of choosing the right size orifice – too small and flow can be restricted too much and too big and you may end up paying for other problems.

Another potential impact to Cv is the difference in valve technology. Though there more, I’ll specifically cover stopcock/ball valves, weir style valves; and diaphragm valves. Other valve technologies, such as the butterfly valve, will not be discussed because their construction materials are generally not used for fluid handling components for the semiconductor industry.

Starting with the simplest design, the stopcock/ball valve provides by far the best Cv of the three technologies mentioned. Considering the premium Cv achieved, you would assume they are expensive. Instead they are generally the cheapest of the three values mentioned. One drawback in using stopcock valves is the need for a liquid oring on the fluid path which may create compatibility issues. The exception is the Furon® SCM Valve, a stopcock valve that employs a PFA on PTFE technology and allows for oring-free sealing. Additionally, stopcock valves can lower pressure/ temperature ratings and have a tendency to generate a great deal of particles when actuated. This occurs when the key or ball is rotating inside the valve body. Both drawbacks are related to the PTFE/PFA construction materials required for the flow path by the micro-e industry.

The weir style valve, if done properly, should provide a very good Cv – perhaps not as good as a stopcock/ball valve, but still very good. And although liquid orings are not an issue, these valves have other drawbacks. In a weir style valve the diaphragm is generally a sandwich structure consisting of a thin layer of PTFE that is backed by an elastomeric component in which a metal pin is embedded to connect the membrane to the valve actuating system. It is the sandwich materials that generate a number of potential issues when used on critical, high purity chemistry. Specifically, the delamination of the sandwich creates the possi- bility of multiple points of contamination to the liquid (metal & elastomer). In addition, the significant surface contact between the membrane and the valve seat, which is necessary to secure a full seal, generates a lot of particles – though significantly less than a stopcock/ball valve.

The diaphragm valve is the most commonly used valve in the semiconductor industry as it offers a great balance in terms of the issues previously identified: potential contami- nation, materials and particle generation. The trade-off is that the construction of these valves is more complex and as a result they are priced higher than the average cost of the other valves. Additionally, the Cv performance is well below a stopcock/ball valve and slightly below a weir style valve. However, by using Saint-Gobain’s patented rolling diaphragm technology this does not have to be an issue. In fact, with this technology, we can offer the equivalent Cv of a weir style valve in combination with premium pressure and temperature capabilities as well as the cleanest valve technology – all of which allows for a system design with the lowest impact possible on the transported fluid.

As demonstrated in this document, understanding the Cv rating and the impacts that could affect that rating as it relates to valves is critical when optimizing an installation for fluid and energy efficiency. Cost aside, there are a number of issues that are unique to the semiconductor industry that ultimately guide and often restrict installation choices, such as: dead volume, particle generation, cleanliness as well as the physical and mechanical properties of appropriate polymers. Additionally, choosing the appropriate valve for your installation goes far beyond the simple notion that if “I need more flow, I will get a larger valve.” Most likely the residual effect of that choice will affect the performance of the system, particularly regarding cleanliness. Instead critical adjustments to your valve actuation mechanism and valve flow path designs as well as to your valve technology may allow you to achieve the required results – even if the installation still uses the same 1⁄2” valve…but more on this point in another article.

References

1. www.processsystems.saint-gobain.com/sites/imdf.processsystems. com/files/2015-12-03-part-one-design-impact-for-fluid-components.pdf

Over the past half-century, scientists have shaved silicon films down to just a wisp of atoms in pursuit of smaller, faster electronics. For the next set of breakthroughs, though, they’ll need novel ways to build even tinier and more powerful devices.

A study led by UChicago researchers, published Sept. 20 in Nature, describes an innovative method to make stacks of semiconductors just a few atoms thick. The technique offers scientists and engineers a simple, cost-effective method to make thin, uniform layers of these materials, which could expand capabilities for devices from solar cells to cell phones.

Stacking thin layers of materials offers a range of possibilities for making electronic devices with unique properties. But manufacturing such films is a delicate process, with little room for error.

“The scale of the problem we’re looking at is, imagine trying to lay down a flat sheet of plastic wrap the size of Chicago without getting any air bubbles in it,” said Jiwoong Park, a UChicago professor with the Department of Chemistry, the Institute for Molecular Engineering and the James Franck Institute, who led the study. “When the material itself is just atoms thick, every little stray atom is a problem.”

Today, these layers are “grown” instead of stacking them on top of one another. But that means the bottom layers have to be subjected to harsh growth conditions such as high temperatures while the new ones are added — a process that limits the materials with which to make them.

Park’s team instead made the films individually. Then they put them into a vacuum, peeled them off and stuck them to one another, like Post-It notes. This allowed the scientists to make films that were connected with weak bonds instead of stronger covalent bonds–interfering less with the perfect surfaces between the layers.

“The films, vertically controlled at the atomic-level, are exceptionally high-quality over entire wafers,” said Kibum Kang, a postdoctoral associate who was the first author of the study.

Kan-Heng Lee, a graduate student and co-first author of the study, then tested the films’ electrical properties by making them into devices and showed that their functions can be designed on the atomic scale, which could allow them to serve as the essential ingredient for future computer chips.

The method opens up a myriad of possibilities for such films. They can be made on top of water or plastics; they can be made to detach by dipping them into water; and they can be carved or patterned with an ion beam. Researchers are exploring the full range of what can be done with the method, which they said is simple and cost-effective.

“We expect this new method to accelerate the discovery of novel materials, as well as enabling large-scale manufacturing,” Park said.

A research group consisting of scientists from Tomsk Polytechnic University, Germany and Venezuela proved vulnerability of a two-dimensional semiconductor gallium selenide in air. This discovery will allow manufacturing superconducting nanoelectronics based on gallium selenide, which has never been previously achieved by any research team in the world.

The study was published in Semiconductor Science and Technology.

One of the promising areas of modern materials science is the study of two-dimensional (2D) materials, i.e. thin films consisting of one or several atomic layers. 2D materials due to their electrical superconductivity and strength could be a basis for modern nanoelectronics. Optic applications in nanoelectronics require advanced materials capable of ‘generating’ great electron fluxes upon light irradiation. Gallium selenide (GaSe) is one of the 2D semiconductors that can cope with this problem most efficiently.

‘Some research teams abroad tried to create electronic devices based on GaSe. However, despite extensive theoretical studies of this material, which were published in major scientific journals, the stability of the material in real devices remained unclear,’ says Prof. Raul Rodriguez, the Department of Lasers and Lighting Engineering.

The research team revealed the reasons behind this. They studied GaSe by means of Raman spectroscopy and x-ray photoelectron spectroscopy that allowed proving the existence of chemical bonds between gallium and oxygen. Photoluminescence in oxidized substance is absent that also proves the formation of oxides. It means that the scientists revealed that GaSe oxidizes quickly in air and loses its electrical conductivity necessary for creating nanoeletronic devices.

‘GaSe monolayers become oxidized almost immediately after being exposed to air. Further research of GASe stability in air will allow making proposals how to protect it and maintain its optoelectronic properties,’ emphasize the authors.

According to Prof. Rodriguez, for GaSe not to lose its unique properties it should be placed in a vacuum or inert environment. For example, it can be applied in encapsulated devices that are vacuum-manufactured and then covered with a protective layer eliminating air penetration.

This method can be used to produce next generation optoelectronics, detectors, light sources and solar batteries. Such devices of ultra-small sizes will have very high quantum efficiency, i.e. they will be able to generate large electron fluxes under small external exposure.

GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications.

GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design.

“GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.”

“This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.”

GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs.

SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com.

Modern life will be almost unthinkable without transistors. They are the ubiquitous building blocks of all electronic devices: each computer chip contains billions of them. However, as the chips become smaller and smaller, the current 3D field-electronic transistors (FETs) are reaching their efficiency limit. A research team at the Center for Artificial Low Dimensional Electronic Systems, within the Institute for Basic Science (IBS), has developed the first 2D electronic circuit (FET) made of a single material. Published on Nature Nanotechnology, this study shows a new method to make metal and semiconductor from the same material in order to manifacture 2D FETs.

In simple terms, FETs can be thought as high-speed switches, comprised of two metal electrodes and a semiconducting channel in between. Electrons (or holes) move from the source electrode to the drain electrode, flowing through the channel. While 3D FETs have been scaled down to nanoscale dimensions successfully, their physical limitations are starting to emerge. Short semiconductor channel lengths lead to a decrease in performance: some electrons (or holes) are able to flow between the electrodes even when they should not, causing heat and efficiency reduction. To overcome this performance degradation, transistor channels have to be made with nanometer-scale thin materials. However, even thin 3D materials are not good enough, as unpaired electrons, part of the so-called “dangling bonds” at the surface interfere with the flowing electrons, leading to scattering.

Passing from thin 3D FETs to 2D FETs can overcome these problems and bring in new attractive properties. “FETs made from 2D semiconductors are free from short-channel effects because all electrons are confined in naturally atomically thin channels, free of dangling bonds at the surface,” explains Ji Ho Sung, first author of the study. Moreover, single- and few-layer form of layered 2D materials have a wide range of electrical and tunable optical properties, atomic-scale thickness, mechanical flexibility and large bandgaps (1~2 eV).

The major issue for 2D FET transistors is the existence of a large contact resistance at the interface between the 2D semiconductor and any bulk metal. To address this, the team devised a new technique to produce 2D transistors with semiconductor and metal made of the same chemical compound, molybdenum telluride (MoTe2). It is a polymorphic material, meaning that it can be used both as metal and as semiconductor. Contact resistance at the interface between the semiconductor and metallic MoTe2 is shown to be very low. Barrier height was lowered by a factor of 7, from 150meV to 22meV.

IBS scientists used the chemical vapor deposition (CVD) technique to build high quality metallic or semiconducting MoTe2 crystals. The polymorphism is controlled by the temperature inside a hot-walled quartz-tube furnace filled with NaCl vapor: 710°C to obtain metal and 670°C for a semiconductor.

The scientists also manufactured larger scale structures using stripes of tungsten diselenide (WSe2) alternated with tungsten ditelluride (WTe2). They first created a thin layer of semiconducting WSe2 with chemical vapor deposition, then scraped out some stripes and grew metallic WTe2 on its place.

It is anticipated that in the future, it would be possible to realize an even smaller contact resistance, reaching the theoretical quantum limit, which is regarded as a major issue in the study of 2D materials, including graphene and other transition metal dichalcogenide materials.

Entegris Inc. (NASDAQ: ENTG), a specialty materials provider, announced at SEMICON Taiwan today the availability of its Oktolex membrane technology for advanced point-of-use photolithography applications. Oktolex’s membranes remove critical photochemical contaminants by enhancing the native retention mechanisms of each membrane type to match the needs of each chemistry. By matching membrane characteristics with specific contaminant-adsorption mechanisms, Oktolex membranes further optimize removal performance with no adverse interactions with the chemical composition.

“Breaking from convention, we’ve developed a cleaner, faster, and more effective way to remove the most challenging contaminants with a tailored approach to the specific contamination control needs of ArF, KrF, and EUV applications for Logic, DRAM, and 3D NAND devices,” noted Entegris Senior Vice President and General Manager of Microcontamination Control, Clint Haris. “The true advantage of this technology is its ability to create membranes that effectively remove the targeted contaminants, while not altering the chemical composition. This combination enables us to collaborate with customers to create precise contaminant removal solutions that meet the needs of advanced nodes and reduce tool downtime.”

Oktolex technology is currently available in Entegris Impact 8G point-of-use photochemical filters.

TowerJazz, the global specialty foundry, today announced the release of its advanced 5V 65nm power process providing customers with multiple advantages over 0.18um 5V technologies. The advanced 5V 65nm technology increases TowerJazz’s footprint in the 5V power market by offering enhanced Rdson efficiency with an attractive die cost advantage over 0.18um 5V processes. This technology is based on TowerJazz’s automotive 300mm 65nm process platform manufactured in its Uozu, Japan facility and supports both best in class quality and manufacturing cycle time.

The advanced 5V 65nm contains a rich portfolio of analog features and many different metal combinations to optimize cost/performance for any application. The first products, for several strategic customers, were already prototyped with outstanding performance. The technology is now fully released and supports Multi-layer Masking (MLM) and an MPW option to reduce engineering costs. The first MPW is targeted for November 2017.

TowerJazz’s 5V 65nm power technology offers high Rdson efficiency using tighter design rules for power devices, and a thick copper top metal for large current applications, enabling the 5V transistors using a 65nm design to achieve dense digital capabilities and a dense analog periphery, with a low number of manufacturing masks. The technology offers an average of 30% area reduction for a given 5V power transistor and typically a 35% die size reduction for a mixed-signal chip. An optimization effort to minimize cost and manufacturing layers needed to support 5V enables highly competitive solutions for many different markets such as automotive, industrial and consumer. The advanced 5V 65nm supports high current power applications such as PMIC, DC/DC converters, load switches and point of load ICs using single and dual 3.3um thick copper metal layers.

“Streamlining our feature rich automotive quality 65nm technology allows TowerJazz to provide very attractive 5V power and mixed-signal solutions with the high quality standard set required for servicing the automotive market,” said Shimon Greenberg, Vice President and General Manager of Mixed-Signal and Power Management Business Unit, TowerJazz. “This technology is utilized for relatively high current power ICs at 5V which have large growth drivers to advanced analog and mixed-signal ICs.”

Researchers from North Carolina State University are rolling out a new manufacturing process and chip design for silicon carbide (SiC) power devices, which can be used to more efficiently regulate power in technologies that use electronics. The process – called PRESiCE – was developed with support from the PowerAmerica Institute funded by the Department of Energy to make it easier for companies to enter the SiC marketplace and develop new products.

“PRESiCE will allow more companies to get into the SiC market, because they won’t have to initially develop their own design and manufacturing process for power devices – an expensive, time-consuming engineering effort,” says Jay Baliga, Distinguished University Professor of Electrical and Computer Engineering at NC State and lead author of a paper on PRESiCE that will be presented later this month. “The companies can instead use the PRESiCE technology to develop their own products. That’s good for the companies, good for consumers, and good for U.S. manufacturing.”

Power devices consist of a diode and transistor, and are used to regulate the flow of power in electrical devices. For decades, electronics have used silicon-based power devices. In recent years, however, some companies have begun using SiC power devices, which have two key advantages.

First, SiC power devices are more efficient, because SiC transistors lose less power. Conventional silicon transistors lose 10 percent of their energy to waste heat. SiC transistors lose only 7 percent. This is not only more efficient, but means that product designers need to do less to address cooling for the devices.

Second, SiC devices can also switch at a higher frequency. That means electronics incorporating SiC devices can have smaller capacitors and inductors – allowing designers to create smaller, lighter electronic products.

But there’s a problem.

Up to this point, companies that have developed manufacturing processes for creating SiC power devices have kept their processes proprietary – making it difficult for other companies to get into the field. This has limited the participation of other companies and kept the cost of SiC devices high.

The NC State researchers developed PRESiCE to address this bottleneck, with the goal of lowering the barrier of entry to the field for companies and increasing innovation.

The PRESiCE team worked with a Texas-based foundry called X-Fab to implement the manufacturing process and have now qualified it – showing that it has the high yield and tight statistical distribution of electrical properties for SiC power devices necessary to make them attractive to industry.

“If more companies get involved in manufacturing SiC power devices, it will increase the volume of production at the foundry, significantly driving down costs,” Baliga says.

Right now, SiC devices cost about five times more than silicon power devices.

“Our goal is to get it down to 1.5 times the cost of silicon devices,” Baliga says. “Hopefully that will begin the ‘virtuous cycle’: lower cost will lead to higher use; higher use leads to greater production volume; greater production volume further reduces cost, and so on. And consumers are getting a better, more energy-efficient product.”

The researchers have already licensed the PRESiCE process and chip design to one company, and are in talks with several others.

“I conceived the development of wide bandgap semiconductor (SiC) power devices in 1979 and have been promoting the technology for more than three decades,” Baliga says. “Now, I feel privileged to have created PRESiCE as the nation’s technology for manufacturing SiC power devices to generate high-paying jobs in the U.S. We’re optimistic that our technology can expedite the commercialization of SiC devices and contribute to a competitive manufacturing sector here in the U.S.,” Baliga says.

The paper, “PRESiCE: PRocess Engineered for manufacturing SiC Electronic-devices,” will be presented at the International Conference on Silicon Carbide and Related Materials, being held Sept. 17-22 in Washington, D.C. The paper is co-authored by W. Sung, now at State University of New York Polytechnic Institute; K. Han and J. Harmon, who are Ph.D. students at NC State; and A. Tucker and S. Syed, who are undergraduates at NC State.