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A novel SACVD PMD invention sets the benchmark for helium reduction efforts by achieving four key objectives: cost reduction, quality, process robustness and productivity.

BY JAE HEE KIM, Thin Film Dielectric Fabrication Engineering, Texas Instruments, Dallas, TX

The United States is the world’s largest helium supplier and half of its supply comes from a helium reserve regulated by the Bureau of Land Management just outside of Amarillo, Texas. As many predict, at the current rate of production the maximum expected life of this reserve is 2020. As a result of a shortage that began in 2013, the cost of bulk helium has been increasing significantly (FIGURE 1).

Helium 1

Considering semiconductor manufacturing is one of largest helium consuming industries [2], it becomes crucial to invest continuous efforts to minimize helium usage during wafer fabrication processes and to identify new opportunities for helium reduction. In this article, we’ll take a look at a new innovative process to do just that.

Sub-Atmospheric Chemical Vapor Deposition (SACVD) for pre-metal layer consumes a significant amount of helium to assist in process gas delivery during deposition and in-situ chamber clean which makes the best candidate for helium reduction effort benchmarking. Also, SACVD Pre-Metal Dielectric (PMD) consists of various processes including phosphosilicate glass (PSG) and borophospho-silicate glass (BPSG) which makes the fan-out process more applicable for a bigger impact on helium reduction. So how do we do it?

Objectives

There are four key objectives to a new SACVD PMD process development that my team has looked at: cost, quality, process robustness, and productivity. First, a new carrier gas was identified to maximize helium usage reduction. Second, solutions to both new hardware and process conditions were developed for quality improvement. A new blocker plate was qualified to improve within wafer thickness uniformity. Additionally, gas conditions were developed to improve the gap-fill capability for leakage reduction. Third, a new pressure condition was qualified for process robustness improvement. An old two-step baseline process was designed for better gap fill by depos- iting initial 4kA film at 700Torr for lower deposition rate and the rest of the film at BKM pressure, 200Torr for better cycle time. However, this baseline two-step process, which operates at near atmospheric pressure on a sub-atmospheric CVD tool platform, is marginal for pumping speed degradation which leads to inline defect. Susceptibility of defect formation was reduced by lowering process pressure from 700Torr to 600Torr during the initial PMD layer. Last, overall process conditions were evaluated to achieve a desirable deposition rate in order to ensure comparable manufacturing throughput. Furthermore, a new process condition was selected to avoid process chamber restriction for flexibility of manufacturing.

New process carrier gas identification

Initial process development was divided into two categories: BPSG and PSG. Development began with PSG since there is one less process parameter, Boron compared to BPSG process. Preliminary tests showed that a 100 percent N2 carrier drives an unstable film thickness range. Based on findings, a helium and nitrogen mix carrier gas was selected for further process evaluation. The main focus at this stage of evaluation were to identify process conditions including a helium and nitrogen mix carrier gas flow to achieve maximum helium savings, comparable cycle time, and thickness uniformity improvement.

Process condition development

Based on design of experiments (DOE) with four key process parameters (N2, He, O3, spacing), we learned that deposition rate is faster with increasing He and slower with increasing N2 and O3. Thickness uniformity degrades with total carrier gas flow. Based on DOE results, initial proposed condition was carrier 5500sccm (3:1 = N2:He), O3 3000sccm, spacing 200mils for better thickness uniformity and shorter cycle time while saving the maximum amount of helium.

Unfortunately, this condition degraded at baseline margin to form voids in 700Torr deposition film due to faster deposition rate. Focus was then shifted to identify a recipe condition that lowers the deposition rate during 700Torr deposition for a better gap fill capability which also can be used for both 200Torr PSG and two-step PSG to ensure manufacturing flexibility.

Based on deposition rate DOE with three parameters including Ozone, tetraethyl orthosilicate (TEOS) and spacing (TABLE 1), ozone flow has first-order effects on the deposition rate, and spacing has second-order effects. TEOS flow has third-order effects on deposition rates but also reduces dopant concentration of film. Temperature change was not considered since it affects other recipe conditions at a greater degree. Increasing pressure was also not considered since the process already operates at a high pressure of 700Torr.

Helium Table 1

Then it was decided to include Ozone and spacing, in addition to helium and nitrogen, into further process characterization. We ran comprehensive three factorial DOE to deposit 4kA PSG film at 700Torr at various settings of total carrier flow, spacing, and ozone. This was in order to achieve a lower deposition rate for better gap fill and good thickness uniformity. DOE conditions were determined based on JMP prediction profiler and calculators to evaluate a wide spectrum of different deposition rates at 700Torr and thickness range.

To evaluate the DOE result, two techniques were used. First, wafer samples were prepared by sputtering top down until they reached the very initial layer of PMD to open up any voids that are present in PSG film. Effectiveness of gap-fill capability was rated by quantifying a number of voids on the scanning electron microscopy (SEM) images captured at same magnification on the consistent location of the wafer sample. This is a more effective technique than collecting transmission electron microscopy (TEM) on a defined location on samples since top down SEM can capture broader areas of wafer samples. Second, wafers were also submitted for dynamic secondary ion mass spectrometry (SIMS) to ensure if the dopant profile throughout PSG film is comparable to the baseline. This critical step is to verify that there is no sign of unstable dopant distribution that could lead to any adverse effects, such as increased etch selectivity or poor gettering (FIGURE 2).

Helium 2

Based on DSIMS collected, it was found that the dopant concentration profile becomes unstable if the total carrier gas flow is less than 5500sccm. Phosphorous (P) concentration profile shows fluctuation all throughout the film at a total carrier gas flow less than 5500sccm while phosphorous percent profile was steady at total carrier gas at 5500sccm or higher (FIGURE 3).

Helium 3

Among many conditions that satisfy a total carrier gas flow of less than 5500sccm, when ozone flow is 5000sccm and total carrier gas is 5500sccm with a 3:1 ratio of nitrogen to helium, the top down SEM result shows a greatly reduced number of voids in film. This means the deposition rate during 700Torr is slow enough to improve gap-fill capability. At the same time, Ozone flow at 5000sccm was fast enough during 200Torr to maintain a comparable cycle time. Therefore, this condition can be used for both single step PSG and two-step PSG which allows flexibility for manufacturing to run both processes without equipment restriction. Dynamic SIMS also verified that this condition provided a stable dopant profile. Thickness uniformity was also comparable to the baseline on this recipe condition. Therefore, spacing 200mils, ozone 5000sccm, and a total carrier flow 5500sccm was chosen as a finalized new PSG condition.

For the BPSG process, the same technique was used for evaluation. DSIMS was used to ensure both Boron and phosphorous concentration profiles are comparable. The same carrier gas conditions with nitrogen and helium at a ratio of 3:1 of 5500sccm and Ozone 5000sccm were selected for the final condition. TEOS was increased from 600mgm to 800mgm to make sure the deposition rate is comparable to maintain manufacturing cycle time at PMD (TABLE 2).

Helium Table 2

Flash parametric legacy issue improvement

A high aspect ratio of device structure can cause voids in PMD that lead to poor isolation and yield loss. There are many contributing factors that modulate PMD voids, including a stacked gate vertical profile and a sidewall spacer profile. Among all contributing factors, however, a void-free PMD process was proven to be the most effective way to minimize leakage. The void-free PMD was achieved by qualifying a new two-step PSG process with a mix carrier gas.

The new two-step PSG process with a mix carrier greatly lowers the deposition rate during the initial PMD layer. This helps deposit film more uniformly at higher pressures to minimize voids, while depositing the rest of the PMD at a faster deposition rate at lower pressure helps to compensate cycle time loss from the initial deposition.

The new two-step PSG alleviates leakage susceptibility on the wafer edge and reduces sensitivity to the PMD void-contributing factors by adding significant margins to leakage failure due to voids. Notably, the PMD gap-fill improvement added significant integration marginality between the sidewall spacer profile and the PMD which led to lower process and tool sensitivity at the sidewall spacer etch. This increases manufacturing capacity by releasing sidewall spacer etch process chambers with historical leakage failure susceptibility to production. Most importantly, parametric outlier probability was greatly improved by 20 percent and a zero standard parametric failure rate was achieved by qualifying void-free PMD (FIGURE 4).

FIGURE 4. Void-free PMD (right) shows excellent gap fill while baseline PMD (left) shows a void filled with W [3].

FIGURE 4. Void-free PMD (right) shows excellent gap fill while baseline PMD (left) shows a void filled with W [3].

Process robustness improvement

There were technical challenges with center cluster defects on the new two-step process. Center cluster defects affected isolation contact resistance. Based on TEM (FIGURE 5), defects formed around where a low deposition rate completed and a faster deposition rate resumed. Dynamic SIMS showed a phosphorous concen- tration peak at the defect which explained why this defect had a high contact etch selectivity.

Helium 5

After exposing the test wafer for 24 hours at atmosphere, haze was formed on its substrate. Time of flight secondary ion mass spectroscopy showed that haze was caused by a reaction between excessive phosphorous and atmospheric moisture. Additionally, a repeatability test showed that the tail of cluster defects extended towards gas exhaust. Based on these findings, this baseline two-step process which operates at near-atmospheric pressure on a sub-atmospheric CVD tool platform is marginal to maintain sufficient pumping speed during pressure transition from high process pressure to low process pressure (FIGURE 6). This significantly increased the chances of forming center cluster defects with a heavier carrier gas. This is because the pumping speed is lower at a higher pressure and mean residence time is longer at a higher pressure. Additionally, conductance is lower with N2 than with He due to heavier molecular weight.

Helium 6

In order to address this issue, the new two-step process was reevaluated and a new process condition was developed. As summarized in TABLE 3, it was decided to maintain the same carrier gas flow to maintain bulk helium savings. Pressure condition for the first deposition step was modified from 700Torr to 600Torr. This new two-step process improved robustness by reducing risks of pumping speed degra- dation during the pressure transition from 600Torr to 200Torr. The new two-step process is also able to deliver a strong PMD void-fill improvement by maintaining a zero parametric failure rate for leakage.

Helium Table 3

Thickness uniformity improvement

The new SACVD PMD invention took part not only in process development but also in hardware improvement. The new process with a baseline helium blocker plate that helps uniform process gases dispersion showed higher within wafer thickness range which appeared on wafer substrate as in forms of lightly discolored spots. Based on Energy Disperse Spectroscopy (EDS) and Dynamic SIMS, defects were a part of the top 270A of PSG film. The location of spots were nicely matched to the hole pattern of the helium blocker plate. The nitrogen blocker plate was qualified as it consisted of the same material as the helium blocker plate but had a more dense hole pattern. It was not only able to eradicate the anomaly on the surface film but also to alleviate the baseline starburst pattern on the deposited film.

DSIMS confirmed that the dopant profiles on the nitrogen blocker plates are comparable to the ones on the helium blocker plate. The nitrogen blocker plate improved within wafer thickness uniformity by 35 percent on a new PSG film ranging from 12kA to 16kA compared to an old PMD baseline performance (FIGURE 7). Consequently, this improved the process capability index at post PMD Chemical Mechanical Polish (CMP) by improving process targeting based on improved thickness uniformity.

Helium 7

Manufacturing and engineering productivity increased, as well, due to reduced tool down time. New blocker plate qualification also alleviated the sensitivity of film thickness uniformity to the heater age and possibly helped to extend heater life on the PSG chambers and reduce tool down time for range failure.

Conclusion

This novel SACVD PMD invention successfully set the benchmark for helium reduction efforts by achieving four key objectives: cost reduction, quality, process robustness, and productivity. It brings a substantial impact on bulk helium gas savings with worldwide limited supplies and increasing demand. The new PMD reduces bulk helium usage by 80.4 percent and 77.1 percent for PSG and BPSG respectively during deposition and completely eliminates helium usage during in-situ chamber clean.

This new process achieved outstanding gap-fill capability by lowering the deposition rate at initial PMD layer. The process successfully eliminated leakage failure at parametric by adding significant process integration marginality for void formation. It also improves process robustness by reducing risks of pumping speed degra- dation during the pressure transition from 600Torr to 200Torr. Process conditions are carefully developed for comparable manufacturing throughput and harmonized between single step PSG and two-step PSG in order to ensure manufacturing flexibility. Lastly, new hardware qualification also helps improve quality and productivity by lowering within wafer thickness range.

References

[1] C. Kaneshige, 2013, an excerpt from GE Healthcare published in 2012
[2] Semiconductor Industry Association, August 1, 2012, Hearing on “Helium: Supply Shortages Impacting our Economy, National Defense and Manufacturing” (Hearing held on July 10, 2012). Testimony for the Record of the Semiconductor Industry Association.
[3] D. Rodriguez, 2014, unpublished

A research team at Umeå University in Sweden has showed, for the first time, that a very efficient vertical charge transport in semiconducting polymers is possible by controlled chain and crystallite orientation. These pioneering results, which enhance charge transport in polymers by more than 1,000 times, have implications for organic opto-electronic devices and were recently published in the journal Advanced Materials.

Conjugated semiconducting polymers (plastic) possess exceptional optical and electronic properties, which make them highly attractive in the production of organic opto-electronic devices, such as for instance photovoltaic solar cells (OPV), light emitting diodes (OLED) and lasers.

Polythiophene polymers, such as poly(3-hexylthiophene), P3HT, have been among the most studied semiconducting polymers due to their strong optical absorbance and ease of processing into a thin film from solution. In both OPVs and OLEDs, charges must be transported in the out of plane (vertical) direction inside the polymer film.

However, until now the vertical charge carrier mobility of organic semiconductors, i.e. the ability of charges to move inside the material, has been too low to produce fast charge transport in electronic devices. Faster charge transport can occur along the polymer chain backbone. However, a method to produce controlled chain orientation and high mobility in the vertical direction has remained elusive until now.

In the present work, a team of chemists and materials scientists, led by Professor David R. Barbero at Umeå University, has found a new method to align chains vertically and to produce efficient transport of electric charges through the chain backbone. In this new study, moreover, high charge transport and high mobility were obtained without any chemical doping, which is often used to artificially enhance charge transport in polymers.

“The transport of electric charge is greatly enhanced solely by controlled chain and crystallite orientation inside the film. The mobility measured was approximately one thousand times higher than previously reported in the same organic semiconductor,” says David Barbero.

In what way will these results affect the field of organic electronics?

“We believe these results will impact the fields of polymer solar cells and organic photodiodes, where the charges are transported vertically in the device. Organic-based devices have traditionally been slower and less efficient than inorganic ones (e.g. made of silicon), in part due to the low mobility of organic (plastic) semiconductors. Typically, plastic semiconductors, which are only semi-crystalline, have hole mobilities about 10,000 times lower than doped silicon, which is used in many electronic devices. Now we show it is possible to obtain much higher mobility, and much closer to that of silicon, by controlled vertical chain alignment, and without doping,” says David Barbero.

The charge transport was measured using nanoscopic electrical measurements, and gave a mobility averaging 3.1 cm2/V.s, which is the highest mobility ever measured in P3HT, and which comes close to a theoretical estimation of the maximum mobility in P3HT. Crystallinity and molecular packing characterisation of the polymer was performed by synchrotron X-ray diffraction at Stanford University’s National Accelerator (SLAC) and confirmed that the high mobilities measured were due to the re-orientation of the polymer chains and crystallites, leading to fast charge transport along the polymer backbones.

These results, published in Advanced Materials, may open up the route to produce more efficient organic electronic devices with vertical charge transport (e.g. OPV, OLED, lasers etc.), by a simple and inexpensive method, and without requiring chemical modification of the polymer.

Along with the fast development of modern information technology, charge-based memories, such as DRAM and flash memory, are being aggressively scaled down to meet the current trend of small size devices. A memory device with high density, faster speed, and low power consumption is desired to satisfy Moore’s law in the next few decades. Among the candidates of next-generation memory devices, cross-bar-shaped non-volatile resistive memory (memristor) is one of the most attractive solutions for its non-volatility, faster access speed, ultra-high density and easier fabrication process.

Conventional memristors are usually fabricated through conventional optical, imprint, and e-beam lithographic approaches. However, to meet Moore’s law, the assembly of memristors comprised of 1-dimensional (1D) nanowires must be demonstrated to achieve cell dimensions beyond limit of state-of-art lithographic techniques, thus allowing one to fully exploit the scaling potential of high density memory array.

Prof. Tae-Woo Lee (Dept. of Materials Science and Engineering) and his research team have developed a rapid printing technology for high density and scalable memristor array composed of cross-bar-shaped metal nanowires. The research team, which consists of Prof. Tae-Woo Lee, research professor Wentao Xu, and doctoral student Yeongjun Lee at POSTECH, Korea, published their findings in Advanced Materials.

They applied an emerging technique, electrohydrohynamic nanowire printing (e-NW printing), which directly prints highly-aligned nanowire array on a large scale into the fabrication of microminiature memristors, with cross-bar-shaped conductive Cu nanowires jointed with a nanometer-scale CuxO layer. The metal-oxide-metal structure resistive memory device exhibited excellent electrical performance with reproducible resistive switching behavior.

This simple and fast fabrication process avoids conventional vacuum techniques to significantly reduce the industrial-production cost and time. This method paved the way to the future down-scaling of electronic circuits, since 1D conductors represent a logical way to extreme scaling of data processing devices in the single-digit nanometer scale.

They also succeeded in printing memristor array with various shapes, such as parallel lines with adjustable pitch, grids, and waves which can offer a future stretchable memory for integration into textile to serve as a basic building block for smart fabrics and wearable electronics.

“This technology reduces lead time and cost remarkably compared with existing manufacturing methods of cross-bar-shaped nanowire memory and simplifies its method of construction,” said Prof. Lee. “In particular, this technology will be used as a source technology to realize smart fabric, wearable computers, and textile electronic devices.”

The Center for Integrated Nanostructure Physics (CINAP) within IBS has reported results correlating the flake merging angle with grain boundary (GBs) properties, and proven that increasing the merging angle of GBs drastically improves the flow of electrons. This correlates to an increase in the carrier mobility from less than 1 cm2V-1s-1 for small angles, to 16cm2 V-1s-1 for angles greater than 20°. The paper, entitled, ‘Misorientation-angle-dependent electrical transport across molybdenum disulfide grain boundaries’ is published in the journal Nature Communications.

According to the paper, it is essential to understand the atomic structures of GBs in order to control and improve electrical transport properties in both bulk and low-dimensional materials. Grain boundaries are the direction that atoms are arranged in a material. For the experiments undertaken by scientists at CINAP, a monolayer molybdenum disulfide (MoS2) was grown by chemical vapor deposition (CVD) and subsequently transferred to a substrate of silicon dioxide (SiO2). The team’s reasoning for using MoS2 is twofold: firstly, it is a 2D semiconductor that features high electrical conductance and, crucially, has a natural bandgap, which enables it to be tuned on and off and; secondly, the grain boundaries are well-defined. This is paramount for successful experiments. Previous research from Northwestern University found that the GBs of MoS2 provided a unique way to modulate resistance; this was achieved by using a large electric field to spatially modulate the location of the grain boundaries.

The Northwestern results, published last year in Nature Nanotechnology, opened a pathway for future research, but the debate regarding the transport physics at the GB is still under dispute. This is due to a large device-to-device performance variation, poor single-domain carrier mobility, and, most importantly, a lack of correlation between transport properties and GB atomic structures in MoS2 research. The CINAP team, headed by the Center’s director Young Hee Lee, overcame these obstacles by directly correlating four-probe transport measurements across single GBs with both high-resolution transmission electron microscopy (TEM) imaging and first-principles calculations. TEM is a microscopy technique whereby a beam of electrons is transmitted through an ultra-thin specimen, interacting with the specimen as it passes through. An exact atomic-scale image is formed from the interaction of the electrons transmitted through the specimen.

Identifying Grain Boundaries

GBs in the MoS2 layers were identified and regions with no sign of wrinkling or multilayers were then selected to prevent misinterpretations. Four-probe transport measurements were then performed on the substrate with surprising results; when measuring flake misorientations of 8-20o, mobility increased from much less than 1 cm2V-1s-1 up to 16cm2 V-1s-1. Above 20o field effect mobility saturates at a 16cm2 V-1s-1 intra-domain cutoff. Thus, GBs between flakes having a misorientation angle of 20-60o show better transport properties.

The team has, as reported in their paper, “provided a more unified picture of the relationship between mobility, merging angle and atomistic structures of the GBs of monolayer MoS2.” The results provide practical expectations regarding transport properties in large-area films, which will be restricted largely by the poor mobility across GBs. The results obtained in this work are applicable to other similar 2D systems, and contribute to the fundamental understanding of transport in semiconductors.

Making tiny switches do enormous jobs in a more efficient way than current technology allows is one of the goals of a research team led by Cornell engineering professor Huili (Grace) Xing.

Xing and her group – which includes her husband, Debdeep Jena, also an engineering professor at Cornell – have created gallium nitride (GaN) power diodes capable of serving as the building blocks for future GaN power switches. The group built a GaN power-switching device, approximately one-fifth the width of a human hair, that could support 2,000 volts of electricity.

With silicon-based semiconductors rapidly approaching their performance limits in electronics, GaN is seen as the next generation in power control and conversion. Applications span nearly all electronics products and electricity distribution infrastructure.

“With some of these new materials, it’s actually conceivable now to shrink medium-scale power-distribution systems onto a chip,” Jena said. “Looking into the future, this is one of the goals, and it’s not a moonshot. It’s possible, but the materials have to be right, the design has to be right.”

The team’s work was published Dec. 15 in the journal Applied Physics Letters, a publication of the American Institute of Physics. The group includes researchers from Cornell, the University of Notre Dame – from where Xing and Jena arrived at Cornell last year – and the semiconductor company IQE.

Xing said the key to her team’s discovery was building the device on a GaN base layer that contained relatively few energy-sapping defects, in comparison to traditional silicon-based substrates.

“We’re going to take the defects, some of them anyway, out of the equation,” said Xing, the Richard Lundquist Sesquicentennial Professor of Electrical and Computer Engineering and a professor of materials science and engineering. “Nothing can be 100 percent [free of defects], but we’re talking about improvements along an order of magnitude of up to 10,000 times.”

The team used a couple of indicators to determine the defect level in the GaN diode, including “diode ideality factor” as measured by the Shockley-Read-Hall recombination lifetime. The SRH lifetime is the average time it takes positively and negatively charged particles to move around before recombining at defects, which creates inefficiency.

The team’s work yielded near-ideal performance in all aspects, spawning hope for the future of GaN power diodes.

“Our results are an important step toward understanding the intrinsic properties and the true potential of GaN,” said Zongyang Hu, a Cornell postdoctoral associate and the paper’s co-lead author.

While much of energy-related research and development is focused on alternative energy sources, such as wind and solar, the Xing team’s efforts in power transmission are just as important, Jena said.

“Power generation gets a lot of press, and it should,” he said. “But once the power is generated, the amount of power that is lost because of inefficiencies is mind-bogglingly large. This problem is about conservation rather than generating power, which is really the same thing.

“And the scale of losses today actually far surpasses the total of renewable energies combined,” he said. “And it’s a clear and present solution; it’s not like we have to discover something fundamental.”

The team’s work is supported in part by the U.S. Department of Energy’s Advanced Research Projects Agency-Energy (ARPA-E) “SWITCHES” program. SWITCHES stands for Strategies for Wide Bandgap, Inexpensive Transistors for Controlling High-Efficiency Systems.

“Leading one of these projects, we at Cornell – in collaboration with our industrial partners – have established an integrated plan to develop three terminal GaN power transistors, package them, and insert them into circuits and products,” Xing said.

The team’s paper is titled “Near unity ideality factor and Shockley-Read-Hall lifetime in GaN-on-GaN p-n diodes with avalanche breakdown.” Cornell collaborators included Kazuki Nomoto and Vladimir Protasenko, research associates in the School of Electrical and Computer Engineering, and graduate students Bo Song and Mingda Zhu. The team also included Jena’s Ph.D. student Meng Qi at the University of Notre Dame, and engineers Ming Pan and Xiang Gao of IQE.

Cypress Semiconductor Corp., today announced the addition of wafer products to its industry-leading nonvolatile random access memory (NVRAM) portfolio. Cypress’s NVRAM portfolio, which includes Ferroelectric-RAM (F-RAM) and nonvolatile static RAM (nvSRAM) devices, offers reliable protection of critical data during a power failure. Many mission-critical applications that require the unique benefits of F-RAM and nvSRAM also require bare die for small or unique packaging options.

Cypress F-RAM is the most energy-efficient NVRAM technology in the industry with a virtually unlimited 100 trillion write cycle endurance. The ferroelectric material in F-RAM memory cells is highly resistant to data corruption caused by radiation or magnetic field exposure, providing soft error rate immunity for medical, aerospace and defense applications. Cypress nvSRAM is the fastest NVRAM technology in the industry, with access times as low as 20 ns. It provides nonvolatile data retention without the need for additional batteries and also provides unlimited endurance.

“Enabling wafer sales for our NVRAM portfolio allows us to address a wider range of customer needs,” says Sonal Chandrasekharan, Senior Business Unit Director of the Nonvolatile Products Business Unit at Cypress. “Customers can now take advantage of the high performance of nvSRAM or energy efficiency of F-RAM in the exact form factor they require for a specific application.”

Target dates are critical when the semiconductor industry adds small, enhanced features to our favorite devices by integrating advanced materials onto the surfaces of computer chips. Missing a target means postponing a device’s release, which could cost a company millions of dollars or, worse, the loss of competitiveness and an entire industry. But meeting target dates can be challenging because the final integrated devices, which include billions of transistors, must be flawless – less than one defect per 100 square centimeters.

Researchers at the University of Chicago and the U.S. Department of Energy’s Argonne National Laboratory, led by Juan de Pablo and Paul Nealey, may have found a way for the semiconductor industry to hit miniaturization targets on time and without defects.

Researchers from the University of Chicago and Argonne use the supercomputing resources at the Argonne Leadership Computing Facility to predict the path molecules must follow to find defect-free states and designed a process that delivers industry-standard nanocircuitry that can be scaled down to smaller densities without defects. Credit: de Pablo et al.

Researchers from the University of Chicago and Argonne use the supercomputing resources at the Argonne Leadership Computing Facility to predict the path molecules must follow to find defect-free states and designed a process that delivers industry-standard nanocircuitry that can be scaled down to smaller densities without defects. Credit: de Pablo et al.

To make microchips, de Pablo and Nealey’s technique includes creating patterns on semiconductor surfaces that allow block copolymer molecules to self-assemble into specific shapes, but thinner and at much higher densities than those of the original pattern. The researchers can then use a lithography technique to create nano-trenches where conducting wire materials can be deposited.

This is a stark contrast to the industry practice of using homo-polymers in complex “photoresist” formulations, where researchers have “hit a wall,” unable to make the material smaller.

Before they could develop their new fabrication method, however, de Pablo and Nealey needed to understand exactly how block copolymers self-assemble when coated onto a patterned surface – their concern being that certain constraints cause copolymer nanostructures to assemble into undesired metastable states. To reach the level of perfection demanded to fabricate high-precision nanocircuitry, the team had to eliminate some of these metastable states.

To imagine how block copolymers assemble, it may be helpful to picture an energy landscape consisting of mountains and valleys where some valleys are deeper than others. The system prefers defect-free stability, which can be characterized by the deepest (low energy) valleys, if they can be found. However, systems can get trapped inside higher (medium energy) valleys, called metastable states, which have more defects.

To move from a metastable to stable state, block copolymer molecules must find ways to climb over the mountains and find lower energy valleys.

“Molecules in these metastable states are comfortable, and they can remain in that state for extraordinarily long periods of time,” said de Pablo of the University of Chicago’s and Argonne’s Institute for Molecular Engineering. “In order to escape such states and attain a perfect arrangement, they need to start rearranging themselves in a manner that allows the system to climb over local energy barriers, before reaching a lower energy minimum. What we have done in this work is predict the path these molecules must follow to find defect-free states and designed a process that delivers industry-standard nanocircuitry that can be scaled down to smaller densities without defects.”

Using an INCITE grant, de Pablo and his team used the Mira and Fusion supercomputers at the Argonne Leadership Computing Facility, a DOE Office of Science User Facility. There, the team generated molecular simulations of self-assembling block polymers along with sophisticated sampling algorithms to calculate where barriers to structural rearrangement would arise in the material.

After all the calculations were done, the researchers could precisely predict the pathways of molecular rearrangement that block copolymers must take to move from a metastable to stable state. They could also experiment with temperatures, solvents and applied fields to further manipulate and decrease the barriers between these states.

To test these calculations, de Pablo and Nealey partnered with IMEC, an international consortium located in Belgium. Their commercial-grade fabrication and characterization instruments helped the researchers perform experiments under conditions that are not available in academic laboratories. An individual defect measures only a handful of nanometers; “finding a defect in a 100 square centimeter area is like finding a needle in hay stack, and there are only a few places in the world where one has access to the necessary equipment to do so,” says de Pablo.

“Manufacturers have long been exploring the feasibility of using block copolymer assembly to reach the small critical dimensions that are demanded by modern computing and higher data storage densities,” de Pablo said. “Their biggest challenge involved evaluating defects; by following the strategies we have outlined, that challenge is greatly diminished.”

John Neuffer, president and CEO of the Semiconductor Industry Association (SIA), says industry is relentlessly focused on designing and building chips that are smaller, more powerful and more energy-efficient. “The key to unlocking the next generation of semiconductor innovation is research,” he said. “SIA commends the work done by Argonne National Laboratory and the University of Chicago, as well as other critical scientific research being done across the United States.”

De Pablo, Nealey and their team will continue their investigations with a wider class of materials, increasing the complexity of patterns and characterizing materials in greater detail while also developing methods based on self-assembly for fabrication of three-dimensional structures.

Their long-term goal, with support from the DOE’s Office of Science, is to arrive at an understanding of directed self-assembly of polymeric molecules that will enable creation of wide classes of materials with exquisite control over their nanostructure and functionality for applications in energy harvesting, storage and transport.

Argonne National Laboratory seeks solutions to pressing national problems in science and technology. The nation’s first national laboratory, Argonne conducts leading-edge basic and applied scientific research in virtually every scientific discipline. Argonne researchers work closely with researchers from hundreds of companies, universities, and federal, state and municipal agencies to help them solve their specific problems, advance America’s scientific leadership and prepare the nation for a better future. With employees from more than 60 nations, Argonne is managed by UChicago Argonne, LLC for the U.S. Department of Energy’s Office of Science.

Stanford University researchers sponsored by Semiconductor Research Corporation (SRC) have developed a new area selective atomic layer deposition (ALD) process that promises to accelerate the manufacturing of higher performing, more energy efficient semiconductors.

It is well known that next-generation electronic, optoelectronic and sensing devices that contain nanoscale dimensions face increasingly difficult materials and fabrication challenges as the downward scaling of these devices continues. Conventional semiconductor manufacturing processes are time-consuming and expensive, in part due to the need for lithographic patterning. The Stanford research leverages simple ALD and etching processes that eliminate this lithography step and improve selective deposition of dielectric materials by more than 10 times in film thickness compared to similar advanced processes.

Due to difficulties of current top-down fabrication processes that contain multiple deposition, lithography and etching steps, along with problems with misalignment in lithography, using an alternative approach in which the desired materials are directly and selectively deposited would significantly facilitate the process, according to the Stanford team.

“Our technology is a promising candidate for overcoming the challenges of top-down processing and misalignment because it greatly improves the ability to perform selective deposition of materials. This research introduces a novel processing method to meet the increasingly difficult materials challenges associated with new devices,” said Dr. Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.

Current approaches utilize lithography for nanoscale patterning. Using lithography and etching for fabrication of 2D or 3D structures often results in misaligned features and causes a risk of shorting or high resistant areas. However, selective deposition using ALD can reduce these risks and reduce the process time and steps.

Bent explained that selective deposition allows layers of material to be added onto a substrate only where desired without the need for additional lithography steps. However, the high level of selectivity needed for a manufacture-worthy process has not yet been achieved in area selective deposition studies. In addition, most methods for area selective deposition require long processing times.

The Stanford research has been focused on selective deposition of dielectric materials on metal/dielectric patterns. These type of structures can be found in interconnects and back-end-of-line (BEOL) processing. With ALD being used in other stages of the device fabrication process as well, the results from the Stanford experiments can potentially be applied to a variety of nanoscale electronic, optoelectronic and sensing devices.

The research developments occurred during the second year of research on the topic, and the Stanford team is continuing to explore new methods for area selective ALD to improve both selectivity and manufacturability.

“The Stanford team’s research has shown for the first time that, by following selective deposition of a dielectric material using pre-treatment by an inhibitory material, they can significantly reduce the process time (from 48 hours to less than 1 hour) and also improve the limits of selective deposition of dielectrics by more than 10 times,” said Kwok Ng, Senior Science Director of Nanomanufacturing Materials and Processes at SRC.

By Arnaud Furnemont, Department Director Memory at imec

Research in memory is really exciting these days: in parallel you have the scaling of classical memories (SRAM, DRAM, Flash) and the emergence of new memories capable of enabling new applications or even new system hierarchies. At imec, we mostly focus on three concepts which all come with different challenges.

First is Flash, and specifically 3D NAND. Here it’s the integration challenge that is keeping us all busy. Before, the focus was on device scaling, but now it’s all about stacking more layers. Last year, we explored new materials for the channel (e.g. III-V channel in 3D NAND) and for the trapping layer (YAlO instead of SiN), in parallel with device reliability characterization and modelling.

Another important memory type is STT-MRAM where a complex magnetic stack makes the scene. Focus here is on choosing the right material combination and developing the perfect stack (with perfect interfaces!). Over the last years, imec made a lot of progress to build a good stack. But even more challenging is the patterning of this multi-layers structure without affecting the magnetic properties of the device. Very recently we were able to demonstrate 45nm devices with good performance. Tool suppliers are improving the etch platforms and I expect STT-MRAM as embedded memory in the foundries by 2017 and as standalone memory by 2020. In the latter case, more scaling is necessary and this implies more etch issues which will have to be solved.

Thirdly, we explore resistive RAM. The challenge for this type of memory is picking the right combination out of the numerous kinds of stacks and materials. And to do this, you need a fundamental understanding of what happens inside each stack. Imec has developed in depth characterization and modelling on OxRAM and CBRAM memories, expected to be used in embedded applications. Globally, RRAM suffers from a trade-off between write energy and stability. VMCO is another RRAM variant developed at imec to break this trade-off. To be competitive in standalone applications, RRAM will also need to be combined with a selector, which requires again material selection and benchmarking. This is a role that imec is willing to take on for its partners.

Finally, there is also a high-level challenge that the memory researchers and developers are facing. It’s the changing landscape in which emerging memories have more and more impact on the system architecture. Before, the system hierarchy was built with the memory technologies that were available. In the future it might be the other way around: the system architects will tell us what to develop. A closer collaboration between the device team and system architects is therefore indispensable. Imec’s memory ‘insite’ activity will tackle this challenge. 

After a master in electro-mechanics, Arnaud Furnémont completed his PhD at IMEC, focusing on characterization of nitride-based memory such as NROM and TANOS. In 2008, he joined Intel in Boise (Idaho) and became responsible for 20nm planar Flash reliability, and later for an emerging memory concept. In 2013 he joined IMEC as memory characterization and integration teams manager. Since end of 2014, Arnaud serves as memory department director, MRAM and Flash program director at imec.

Greg McIntyre, Director Advanced Patterning, imec

The continuation of Moore’s Law requires a combination of both physical and functional scaling, where our main challenge in lithography is to continue pushing the physical scaling limits in a controlled and cost-effective way. By serving as the collaboration hub of the industry in this area, imec is playing a key role in helping the industry to address the major technical challenges towards continued physical scaling. This is being done on multiple fronts.

First, work is ongoing on optical lithography where we try to squeeze everything we can out of immersion lithography by both enhancing resolution and controlling variability. Resolution enhancement for immersion is being achieved through both an increasing degree of multiple patterning and by leveraging the unique properties of novel materials such as in directed self-assembly (DSA). In DSA, sub-resolution patterns are created by the micro-phase separation of specially engineered polymer chains called block copolymers, which are directed in specific orientations by lithographically generated guide patterns. Minimizing the impact of variability is done by first developing techniques to measure, optimize and control the patterning process window, as then by the employment of clever patterning tricks to neutralize any remaining variability. Examples of such tricks, or the co-optimization of multiple unit process steps (litho, etch, deposition, etc.), are the variety of self-aligned integration schemes that are being developed.

But, of course, all eyes are on EUV lithography as it appears a necessity for the continuation of cost-effective physical scaling. Research institutes such as imec are helping industry to understand when and how to insert this technology. Certainly the performance of the tool – or more specifically the ramp in stable power of the light source – is a prerequisite for EUV insertion. ASML has realized some very promising results in this field this past year. However, there is a whole ecosystem involved with EUV lithography, such as materials, masks, understanding the imaging fundamentals , and development of computational techniques – and it is that ecosystem that imec is focused on.

EUV resolution is currently material-limited, thus imec has set up a strong program to work with materials suppliers to develop novel photoresist platforms, and now serves as the centerpiece for such work in the industry. There is also work ongoing on various aspects of the photomask. Our strong collaboration with the Japanese consortium EIDEC is aimed at understanding the capabilities of new mask inspection systems and to link this with printing performance. Additionally, imec launched a very successful pellicle program in 2015, where the pellicle is a very thin free-standing film designed to protect the mask surface from particles. We are now exploring various novel films and have set up a testing facility for characterization of samples developed around the world. Finally, various efforts are focused on understanding the complex interactions between the light source, mask, lens system, and photoresist and to employ computational techniques to optimize the resulting pattern.

With all these technical issues in mind, it becomes clear that collaboration is key to continue the path of lithography. Many parties are involved that all have to work together and contribute their piece of the puzzle. It’s imec’s role to bring all these parties together and understand how all the pieces fit together. This is done in our core CMOS program where all the main chip manufacturers, tool and material suppliers are gathered. But also the supplier hub that imec set up a few years ago, has evolved as a very important aspect of the collaboration platform. Tool and material suppliers can evaluate their products in an early phase of technology development and get valuable feedback on how to further optimize them. In the collaboration process, they bring in not only state-of-the-art tools and materials, but also valuable insights and experiences that help fuel imec’s developments and thus strengthen the core CMOS program. In 2015, various supplier interactions ramped up and have definitely started to pay off. In summary, by serving as the collaboration hub of the industry, imec is playing a valuable role in pushing the limits of physical scaling.

Greg McIntyre is director of the advanced patterning department at imec and responsible for areas related to advanced lithography equipment and process development, patterning process control, computational lithography, and exploratory patterning materials. Prior to joining imec, he was the technical lead for various areas of advanced lithography, imaging and modeling within the IBM research alliance in Albany, New York. He has published over 60 papers, won 7 best paper awards, and has launched a successful startup in the field. Prior to becoming a lithographer, Greg served as a Captain in the US Army. There he held various leadership and management positions, such as directing the logistics for deployment of over 1700 soldiers and development of the US base camps in Kosovo. He holds a Ph.D. and M.S. in electrical engineering from the University of California, Berkeley, and a B.S. from the United States Military Academy at West Point.